refactor
This commit is contained in:
secXsQuared
parent
480e2dbf28
commit
1d4c7282b5
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@ -1,226 +1,2 @@
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#################
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||||
## secX makefile and bochs
|
||||
#################
|
||||
x64/target
|
||||
x64/*.ini
|
||||
x64/cmake-build-debug/*
|
||||
|
||||
#################
|
||||
## Eclipse
|
||||
#################
|
||||
|
||||
*.pydevproject
|
||||
.project
|
||||
.metadata
|
||||
bin/
|
||||
tmp/
|
||||
*.tmp
|
||||
*.bak
|
||||
*.swp
|
||||
*~.nib
|
||||
local.properties
|
||||
.classpath
|
||||
.settings/
|
||||
.loadpath
|
||||
|
||||
# External tool builders
|
||||
.externalToolBuilders/
|
||||
|
||||
# Locally stored "Eclipse launch configurations"
|
||||
*.launch
|
||||
|
||||
# CDT-specific
|
||||
.cproject
|
||||
|
||||
# PDT-specific
|
||||
.buildpath
|
||||
|
||||
|
||||
#################
|
||||
## Visual Studio
|
||||
#################
|
||||
|
||||
## Ignore Visual Studio temporary files, build results, and
|
||||
## files generated by popular Visual Studio add-ons.
|
||||
|
||||
# User-specific files
|
||||
*.suo
|
||||
*.user
|
||||
*.sln.docstates
|
||||
|
||||
# Build results
|
||||
|
||||
[Dd]ebug/
|
||||
[Rr]elease/
|
||||
[Bb]in/
|
||||
[Oo]bj/
|
||||
|
||||
# MSTest test Results
|
||||
[Tt]est[Rr]esult*/
|
||||
[Bb]uild[Ll]og.*
|
||||
|
||||
*_i.c
|
||||
*_p.c
|
||||
*.ilk
|
||||
*.meta
|
||||
*.obj
|
||||
*.pch
|
||||
*.pdb
|
||||
*.pgc
|
||||
*.pgd
|
||||
*.rsp
|
||||
*.sbr
|
||||
*.tlb
|
||||
*.tli
|
||||
*.tlh
|
||||
*.tmp
|
||||
*.tmp_proj
|
||||
*.log
|
||||
*.vspscc
|
||||
*.vssscc
|
||||
.builds
|
||||
*.pidb
|
||||
*.log
|
||||
*.scc
|
||||
|
||||
# Visual C++ cache files
|
||||
ipch/
|
||||
*.aps
|
||||
*.ncb
|
||||
*.opensdf
|
||||
*.sdf
|
||||
*.cachefile
|
||||
|
||||
# Visual Studio profiler
|
||||
*.psess
|
||||
*.vsp
|
||||
*.vspx
|
||||
|
||||
# Guidance Automation Toolkit
|
||||
*.gpState
|
||||
|
||||
# ReSharper is a .NET coding add-in
|
||||
_ReSharper*/
|
||||
*.[Rr]e[Ss]harper
|
||||
|
||||
# TeamCity is a build add-in
|
||||
_TeamCity*
|
||||
|
||||
# DotCover is a Code Coverage Tool
|
||||
*.dotCover
|
||||
|
||||
# NCrunch
|
||||
*.ncrunch*
|
||||
.*crunch*.local.xml
|
||||
|
||||
# Installshield output folder
|
||||
[Ee]xpress/
|
||||
|
||||
# DocProject is a documentation generator add-in
|
||||
DocProject/buildhelp/
|
||||
DocProject/Help/*.HxT
|
||||
DocProject/Help/*.HxC
|
||||
DocProject/Help/*.hhc
|
||||
DocProject/Help/*.hhk
|
||||
DocProject/Help/*.hhp
|
||||
DocProject/Help/Html2
|
||||
DocProject/Help/html
|
||||
|
||||
# Click-Once directory
|
||||
publish/
|
||||
|
||||
# Publish Web Output
|
||||
*.Publish.xml
|
||||
*.pubxml
|
||||
|
||||
# NuGet Packages Directory
|
||||
## TODO: If you have NuGet Package Restore enabled, uncomment the next line
|
||||
#packages/
|
||||
|
||||
# Windows Azure Build Output
|
||||
csx
|
||||
*.build.csdef
|
||||
|
||||
# Windows Store app package directory
|
||||
AppPackages/
|
||||
|
||||
# Others
|
||||
sql/
|
||||
*.Cache
|
||||
ClientBin/
|
||||
[Ss]tyle[Cc]op.*
|
||||
~$*
|
||||
*~
|
||||
*.dbmdl
|
||||
*.[Pp]ublish.xml
|
||||
*.pfx
|
||||
*.publishsettings
|
||||
|
||||
# RIA/Silverlight projects
|
||||
Generated_Code/
|
||||
|
||||
# Backup & report files from converting an old project file to a newer
|
||||
# Visual Studio version. Backup files are not needed, because we have git ;-)
|
||||
_UpgradeReport_Files/
|
||||
Backup*/
|
||||
UpgradeLog*.XML
|
||||
UpgradeLog*.htm
|
||||
|
||||
# SQL Server files
|
||||
App_Data/*.mdf
|
||||
App_Data/*.ldf
|
||||
|
||||
#############
|
||||
## Windows detritus
|
||||
#############
|
||||
|
||||
# Windows image file caches
|
||||
Thumbs.db
|
||||
ehthumbs.db
|
||||
|
||||
# Folder config file
|
||||
Desktop.ini
|
||||
|
||||
# Recycle Bin used on file shares
|
||||
$RECYCLE.BIN/
|
||||
|
||||
# Mac crap
|
||||
.DS_Store
|
||||
|
||||
#############
|
||||
## CLION
|
||||
#############
|
||||
#CMakeLists.txt
|
||||
.idea/
|
||||
|
||||
#############
|
||||
## Python
|
||||
#############
|
||||
|
||||
*.py[co]
|
||||
|
||||
# Packages
|
||||
*.egg
|
||||
*.egg-info
|
||||
dist/
|
||||
eggs/
|
||||
parts/
|
||||
var/
|
||||
sdist/
|
||||
develop-eggs/
|
||||
.installed.cfg
|
||||
|
||||
# Installer logs
|
||||
pip-log.txt
|
||||
|
||||
# Unit test / coverage reports
|
||||
.coverage
|
||||
.tox
|
||||
|
||||
#Translations
|
||||
*.mo
|
||||
|
||||
#Mr Developer
|
||||
.mr.developer.cfg
|
||||
|
||||
*.iso
|
||||
.idea
|
||||
cmake-build-debug
|
||||
|
|
|
|||
|
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@ -0,0 +1,55 @@
|
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ASM := nasm
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CC := /opt/x86_64-elf-gcc
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LD := /opt/x86_64-elf-gcc
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DUMP := /opt/x86_64-elf-objdump
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||||
|
||||
LD_SCRIPT := build/linker.ld
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||||
GRUB_CFG := build/grub.cfg
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||||
SOURCE_DIR := src
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||||
HEADER_DIRS := include
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||||
|
||||
C_WARNINGS := -Wall \
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-Werror \
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-Wextra \
|
||||
-Wpedantic \
|
||||
-Winit-self \
|
||||
-Wunused-parameter \
|
||||
-Wuninitialized \
|
||||
-Wfloat-equal \
|
||||
-Wshadow \
|
||||
-Wcast-qual \
|
||||
-Wcast-align \
|
||||
-Wstrict-prototypes \
|
||||
-Wpointer-arith \
|
||||
-Wno-comment
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||||
|
||||
C_FLAGS := -std=c11 \
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||||
-g \
|
||||
-c \
|
||||
-O2 \
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-mcmodel=kernel \
|
||||
-fno-exceptions \
|
||||
-ffreestanding \
|
||||
-mno-red-zone \
|
||||
-mno-mmx \
|
||||
-mno-sse \
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||||
-mno-sse2 \
|
||||
-masm=intel \
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||||
$(C_WARNINGS) \
|
||||
$(addprefix -I, $(HEADER_DIRS))
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|
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ASM_FLAGS := -w+all \
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-f elf64 \
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-F dwarf \
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-g \
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$(addprefix -I, $(ASM_HEADER_DIRS))
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LD_FLAGS := -lgcc \
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-nodefaultlibs \
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-nostartfiles \
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||||
-nostdlib \
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-Wl,-n \
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-Wl,--build-id=none
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|
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include Rules.mk
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@ -1,64 +0,0 @@
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#include "bifrost.h"
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static int count = 0;
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void timer_proc(void *kp, void *up)
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{
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hw_printf("SYS_TICK: %d . COUNT: %d.\n", ke_get_system_tick(), ke_interlocked_increment(&count, 1));
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}
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hw_handle_t event;
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void driver2(void* par)
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{
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hw_printf("Sleeping...Thread2\n");
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hw_thread_sleep(5);
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hw_printf("Signaling event..\n");
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hw_event_signal(event);
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hw_printf("Sleeping2...Thread2\n");
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hw_thread_sleep(5);
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hw_printf("Exiting..\n");
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hw_thread_exit(10);
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}
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void driver(void *par)
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{
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hw_handle_t timer;
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hw_timer_create(&timer, TIMER_TYPE_AUTO_RESET);
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hw_timer_set(timer, 2, true);
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while (count < 20)
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{
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timer_proc(NULL, NULL);
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hw_timer_wait(timer);
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}
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hw_timer_cancel(timer);
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hw_close_handle(timer);
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hw_printf("Sleeping for some cycles..\n");
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hw_thread_sleep(10);
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hw_printf("Hmmm... sound sleep...\n");
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if(ke_get_current_core() == 1)
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{
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hw_printf("Core1 finished...\n");
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}
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else
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{
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hw_event_create(&event, EVENT_TYPE_MANUAL);
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hw_handle_t thread2_handle;
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hw_thread_create(driver2, NULL, PRIORITY_DEFAULT, THREAD_DEFAULT_STACK_SIZE, &thread2_handle);
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hw_thread_start(thread2_handle);
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hw_printf("Waiting for event...\n");
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hw_event_wait(event);
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hw_printf("Waiting for driver2 exit...\n");
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hw_wait_for_thread_exit(thread2_handle);
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int32_t exit;
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hw_thread_get_exit_code(thread2_handle, &exit);
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hw_printf("Thread2 exited with %d\n", exit);
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hw_close_handle(thread2_handle);
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hw_close_handle(event);
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}
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hw_thread_exit(0);
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}
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@ -1,277 +0,0 @@
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#ifndef _BIFROST_H
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#define _BIFROST_H
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// =======================
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||||
// BIFROST User API header
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||||
// =======================
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||||
|
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// types
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#include <stdint.h>
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#include <stddef.h>
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#include <stdarg.h>
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#include <stdbool.h>
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typedef void (*hw_callback_func_t)(void *kernel_args, void *user_args);
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typedef uint32_t hw_handle_t;
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#define TRUE (true)
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#define FALSE (false)
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// =======================
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// Status Codes
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// =======================
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#define HW_RESULT_SEVERITY_SUCCESS 0
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#define HW_RESULT_SEVERITY_ERROR 1
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#define HW_SUCCESS(hr) (((uint16_t)(hr)) >> 15 == 0)
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#define HW_RESULT_CODE(hr) ((hr) & 0x7F)
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#define HW_RESULT_FACILITY(hr) (((hr) & 0x7F80) >> 7)
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#define HW_RESULT_SEVERITY(hr) (((hr) >> 15) & 0x1)
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#define MAKE_HW_RESULT(sev, fac, code) \
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(((uint16_t)(sev)<<15) | ((uint16_t)(fac)<<7) | ((uint16_t)(code)))
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#define HW_RESULT_FACILITY_THREAD 6
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#define HW_RESULT_FACILITY_DPC 1
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#define HW_RESULT_FACILITY_SEM 2
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#define HW_RESULT_FACILITY_REF 3
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#define HW_RESULT_FACILITY_APC 4
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#define HW_RESULT_FACILITY_EVENT 4
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#define HW_RESULT_FACILITY_TIMER 5
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#define HW_RESULT_NO_FACILITY 0
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typedef enum
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{
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STATUS_SUCCESS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_SUCCESS,
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HW_RESULT_NO_FACILITY, 0),
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THREAD_STATUS_INVALID_ARGUMENT = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_THREAD, 1),
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THREAD_STATUS_INVALID_STATE = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_THREAD, 2),
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THREAD_STATUS_UNINITIALIZED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_THREAD, 3),
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THREAD_STATUS_OUT_OF_MEMORY = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_THREAD, 4),
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THREAD_STATUS_ID_OVERFLOW = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_THREAD, 5),
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DPC_STATUS_NOT_ENOUGH_MEM = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_DPC, 1),
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DPC_STATUS_INVALID_ARGUMENTS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_DPC, 2),
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DPC_STATUS_NOT_INITIALIZED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_DPC, 3),
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SEM_STATUS_CANNOT_ALLOCATE_MEM = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_SEM, 1),
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SEM_STATUS_OCCUPIED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_SEM, 2),
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SEM_STATUS_INVALID_ARGUMENTS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_SEM, 3),
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SEM_STATUS_INVALID_CONTEXT = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_SEM, 4),
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||||
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||||
REF_STATUS_CANNOT_ALLOCATE_MEM = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_REF, 1),
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||||
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||||
REF_STATUS_HANDLE_NOT_FOUND = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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HW_RESULT_FACILITY_REF, 2),
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||||
|
||||
REF_STATUS_INVALID_ARGUMENTS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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||||
HW_RESULT_FACILITY_REF, 3),
|
||||
|
||||
REF_STATUS_HANDLE_DUPLICATE = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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||||
HW_RESULT_FACILITY_REF, 4),
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||||
|
||||
REF_STATUS_UNINITIALIZED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
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||||
HW_RESULT_FACILITY_REF, 5),
|
||||
|
||||
REF_STATUS_REF_FREED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_REF, 6),
|
||||
|
||||
REF_STATUS_NO_EFFECT = MAKE_HW_RESULT(HW_RESULT_SEVERITY_SUCCESS,
|
||||
HW_RESULT_FACILITY_REF, 7),
|
||||
|
||||
|
||||
APC_STATUS_CANNOT_ALLOCATE_MEM = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_APC, 1),
|
||||
|
||||
|
||||
APC_STATUS_INVALID_ARGUMENTS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_APC, 2),
|
||||
|
||||
APC_STATUS_NOT_INITIALIZED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_APC, 3),
|
||||
|
||||
|
||||
EVENT_STATUS_CANNOT_ALLOCATE_MEM = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_EVENT, 1),
|
||||
|
||||
|
||||
EVENT_STATUS_INVALID_ARGUMENTS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_EVENT, 2),
|
||||
|
||||
|
||||
TIMER_STATUS_SUCCESS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_SUCCESS,
|
||||
HW_RESULT_FACILITY_TIMER, 0),
|
||||
|
||||
TIMER_STATUS_CANNOT_ALLOCATE_MEM = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_TIMER, 1),
|
||||
|
||||
TIMER_STATUS_INVALID_ARGUMENTS = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_TIMER, 2),
|
||||
|
||||
TIMER_STATUS_NOT_INITIALIZED = MAKE_HW_RESULT(HW_RESULT_SEVERITY_ERROR,
|
||||
HW_RESULT_FACILITY_TIMER, 3),
|
||||
|
||||
} hw_result_t;
|
||||
|
||||
// =======================
|
||||
// Memory Allocation
|
||||
// =======================
|
||||
extern void *hw_alloc(size_t size);
|
||||
|
||||
extern void hw_free(void *ptr);
|
||||
|
||||
// =======================
|
||||
// Events
|
||||
// =======================
|
||||
typedef enum
|
||||
{
|
||||
EVENT_TYPE_MANUAL,
|
||||
EVENT_TYPE_AUTO
|
||||
} hw_event_type_t;
|
||||
|
||||
extern hw_result_t hw_event_wait(hw_handle_t event);
|
||||
|
||||
extern hw_result_t hw_event_reset(hw_handle_t event);
|
||||
|
||||
extern hw_result_t hw_event_signal(hw_handle_t handle);
|
||||
|
||||
extern hw_result_t hw_event_create(hw_handle_t *out, hw_event_type_t event_type);
|
||||
|
||||
|
||||
// =======================
|
||||
// HAL
|
||||
// =======================
|
||||
#define HW_CACHELINE_SIZE (64)
|
||||
|
||||
extern uint32_t ke_get_system_tick();
|
||||
|
||||
extern void ke_flush_addr(void *addr, uint32_t num_of_cacheline);
|
||||
|
||||
extern uint32_t ke_get_current_core();
|
||||
|
||||
extern int32_t ke_interlocked_exchange(int32_t *addr, int32_t val);
|
||||
|
||||
extern int32_t ke_interlocked_compare_exchange(int32_t *addr, int32_t compare, int32_t val);
|
||||
|
||||
extern int32_t ke_interlocked_increment(int32_t *addr, int32_t val);
|
||||
|
||||
// =======================
|
||||
// Print
|
||||
// =======================
|
||||
extern void hw_printf(const char *format, ...);
|
||||
|
||||
|
||||
// =======================
|
||||
// Handles
|
||||
// =======================
|
||||
extern hw_result_t hw_close_handle(hw_handle_t handle);
|
||||
|
||||
|
||||
// =======================
|
||||
// Semaphores
|
||||
// =======================
|
||||
extern hw_result_t hw_sem_create(hw_handle_t *out, int32_t count);
|
||||
|
||||
extern hw_result_t hw_sem_wait(hw_handle_t handle, int32_t quota);
|
||||
|
||||
extern hw_result_t hw_sem_signal(hw_handle_t handle, int32_t quota);
|
||||
|
||||
extern hw_result_t hw_sem_trywait(hw_handle_t handle, int32_t quota);
|
||||
|
||||
// =======================
|
||||
// stdlib
|
||||
// =======================
|
||||
extern int32_t hw_memcmp(const void *ptr1, const void *ptr2, const size_t len);
|
||||
|
||||
extern void hw_memset(void *ptr, uint8_t value, size_t len);
|
||||
|
||||
// =======================
|
||||
// threads
|
||||
// =======================
|
||||
#define THREAD_DEFAULT_STACK_SIZE 0x4000
|
||||
|
||||
#define THREAD_EXIT_CODE_TERMINATED 0xDEADDEAD
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PRIORITY_HIGHEST = 0,
|
||||
PRIORITY_HIGH,
|
||||
PRIORITY_DEFAULT,
|
||||
PRIORITY_LOW,
|
||||
PRIORITY_LOWEST,
|
||||
PRIORITY_LEVEL_NUM
|
||||
} hw_thread_priority_t;
|
||||
|
||||
extern int32_t hw_current_thread_id();
|
||||
|
||||
extern hw_handle_t hw_current_thread();
|
||||
|
||||
extern hw_result_t hw_wait_for_thread_exit(hw_handle_t handle);
|
||||
|
||||
extern hw_result_t hw_thread_sleep(uint32_t millis);
|
||||
|
||||
extern void hw_thread_exit(int32_t exit_code);
|
||||
|
||||
extern hw_result_t hw_thread_create(void (*proc)(void *),
|
||||
void *args,
|
||||
hw_thread_priority_t priority,
|
||||
uint32_t stack_size,
|
||||
hw_handle_t *thread_handle);
|
||||
|
||||
extern hw_result_t hw_thread_start(hw_handle_t thread_handle);
|
||||
|
||||
extern hw_result_t hw_thread_terminate(hw_handle_t thread_handle);
|
||||
|
||||
extern hw_result_t hw_thread_get_exit_code(hw_handle_t thread_handle, int32_t *exit_code);
|
||||
|
||||
extern hw_result_t hw_thread_open(int32_t thread_id, hw_handle_t *out);
|
||||
|
||||
// =======================
|
||||
// Timers
|
||||
// =======================
|
||||
typedef enum
|
||||
{
|
||||
TIMER_TYPE_MANUAL_RESET,
|
||||
TIMER_TYPE_AUTO_RESET
|
||||
} hw_timer_type_t;
|
||||
|
||||
extern hw_result_t hw_timer_create(hw_handle_t *out,
|
||||
hw_timer_type_t type);
|
||||
|
||||
extern hw_result_t hw_timer_wait(hw_handle_t timer_handle);
|
||||
|
||||
extern hw_result_t hw_timer_set(hw_handle_t timer_handle, uint32_t tick, bool periodic);
|
||||
|
||||
extern hw_result_t hw_timer_cancel(hw_handle_t timer_handle);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
#pragma once
|
||||
#define OBTAIN_STRUCT_ADDR(member_addr, member_name, struct_name) ((struct_name*)((char*)(member_addr)-(char*)(&(((struct_name*)0)->member_name))))
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <bifrost_types.h>
|
||||
|
||||
|
||||
typedef void HW_FUNC();
|
||||
typedef void HW_RUN_FUNC(uint32_t iteration);
|
||||
|
||||
typedef struct {
|
||||
HW_FUNC* pinit;
|
||||
HW_RUN_FUNC* prunTest;
|
||||
HW_FUNC* pcleanup;
|
||||
const char* testPathName;
|
||||
uint32_t testPathHash;
|
||||
} HW_XLIST;
|
||||
|
||||
#define HW_XLIST_TERMINATION (0xDEADBEEFul)
|
||||
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| atomic.c
|
||||
|
|
||||
| Atomic operations that use instructions specific to
|
||||
| the x86 ISA
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
|
||||
void hw_lock(hw_lock_t* lock, const bool yield)
|
||||
{
|
||||
const HW_TESTID id = hw_getMyInstanceID();
|
||||
while (HW_TESTID(-1) != hw_storeConditional(&lock->owner, HW_TESTID(-1), id))
|
||||
{
|
||||
// TODO: yield?
|
||||
}
|
||||
}
|
||||
|
||||
void hw_unlock(hw_lock_t* lock, const bool yield)
|
||||
{
|
||||
hw_assert(hw_getMyInstanceID() == lock->owner);
|
||||
const_cast<volatile HW_TESTID*>(&lock->owner)[0] = HW_TESTID(-1);
|
||||
}
|
||||
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| context.c
|
||||
|
|
||||
| Thread switching functions for 'x86' architecture.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
|
||||
EXTERN_C UINT32 ts_arch_startNextIteration_ASM(VOID* kernelRegs, VOID* testStackPtr, HW_RUN_FUNC* prunTest, UINT32 iteration);
|
||||
EXTERN_C UINT32 ts_arch_runIdleThread_ASM(VOID* kernelRegs, VOID (*prunTest)());
|
||||
EXTERN_C UINT32 ts_arch_enter_init_cleanup_ASM(VOID* kernelRegs, VOID* testStackPtr, HW_FUNC* prunTest);
|
||||
EXTERN_C UINT32 ts_arch_resume_test_ASM(VOID* curTestRegs, VOID *targetTestRegs);
|
||||
EXTERN_C VOID ts_arch_resume_kernel_ASM(VOID* testRegs, VOID *kernelRegs);
|
||||
|
||||
UINT32 ts_arch_enter_init_cleanup_test(HW_FUNC* prunTest, UINT32 testIdx)
|
||||
{
|
||||
// Get the test's stack pointer
|
||||
HW_TS_TESTDATA* testData = (HW_TS_TESTDATA*)hw_readptr(&testSlaveVars->testData);
|
||||
VOID *testStackPtr = (VOID*)hw_readptr(&testData[testIdx].testStackPtr);
|
||||
|
||||
// Transfer control
|
||||
ts_arch_enter_init_cleanup_ASM(&testSlaveVars->kernelRegs, testStackPtr, prunTest);
|
||||
|
||||
return 0; // We never actually hit this return, so the 0 is kind of bogus. Return is done from the _ASM
|
||||
}
|
||||
|
||||
UINT32 ts_arch_startNextIteration(HW_RUN_FUNC* prunTest, UINT32 iteration, UINT32 testIdx, VOID *curTestRegs)
|
||||
{
|
||||
// Get the test's stack pointer
|
||||
HW_TS_TESTDATA* testData = (HW_TS_TESTDATA*)hw_readptr(&testSlaveVars->testData);
|
||||
VOID *testStackPtr = (VOID*)hw_readptr(&testData[testIdx].testStackPtr);
|
||||
|
||||
//Enable preemptive tasking timer
|
||||
if(hw_pTestConfigs->bfinit.PREEMPTION_ON)
|
||||
{
|
||||
arch_int_startPreemptionTimer();
|
||||
}
|
||||
|
||||
hw_int_enable(1 << 0);
|
||||
|
||||
// Transfer control
|
||||
hw_errmsg( "%s: Error: ts_arch_startNextIteration was run and is not yet implemented.\n", __func__ );
|
||||
ts_arch_startNextIteration_ASM(curTestRegs, testStackPtr, prunTest, iteration);
|
||||
|
||||
return 0; // We never actually hit this return, so the 0 is kind of bogus. Return is done from the _ASM
|
||||
}
|
||||
|
||||
UINT32 ts_arch_runIdleThread(VOID (*prunTest)(), VOID *curTestRegs)
|
||||
{
|
||||
// Transfer control
|
||||
hw_errmsg( "%s: Error: ts_arch_runIdleThread was run and is not yet implemented.\n", __func__ );
|
||||
ts_arch_runIdleThread_ASM(curTestRegs, prunTest);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
UINT32 ts_arch_resume_test(VOID* curTestRegs, VOID *targetTestRegs)
|
||||
{
|
||||
ts_arch_resume_test_ASM(targetTestRegs, curTestRegs);
|
||||
|
||||
return 0; // We never actually hit this return, so the 0 is kind of bogus. Return is done from the _ASM
|
||||
}
|
||||
|
||||
VOID ts_arch_resume_kernel(VOID* testRegs, VOID *kernelRegs)
|
||||
{
|
||||
//Disable preemptive tasking timer
|
||||
if(hw_pTestConfigs->bfinit.PREEMPTION_ON)
|
||||
{
|
||||
arch_int_stopPreemptionTimer();
|
||||
}
|
||||
|
||||
// Transfer control to assembly handler
|
||||
ts_arch_resume_kernel_ASM(testRegs, kernelRegs);
|
||||
}
|
||||
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
.text
|
||||
.align 4
|
||||
.global ts_arch_startNextIteration_ASM
|
||||
.global ts_arch_enter_init_cleanup_ASM
|
||||
.global ts_arch_resume_test_ASM
|
||||
.global ts_arch_resume_kernel_ASM
|
||||
.global ts_arch_runIdleThread_ASM
|
||||
|
||||
// Possibly needs to save off program state and processor status for
|
||||
// context switches
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space
|
||||
.macro TS_ARCH_SAVE_REGS_ASM
|
||||
mov %rax, 0x00(%rdi)
|
||||
mov %rbx, 0x08(%rdi)
|
||||
mov %rcx, 0x10(%rdi)
|
||||
mov %rdx, 0x18(%rdi)
|
||||
mov %rsp, 0x20(%rdi)
|
||||
mov %rbp, 0x28(%rdi)
|
||||
mov %rsi, 0x30(%rdi)
|
||||
mov %rdi, 0x38(%rdi)
|
||||
mov %r8, 0x40(%rdi)
|
||||
mov %r9, 0x48(%rdi)
|
||||
mov %r10, 0x50(%rdi)
|
||||
mov %r11, 0x58(%rdi)
|
||||
mov %r12, 0x60(%rdi)
|
||||
mov %r13, 0x68(%rdi)
|
||||
mov %r14, 0x70(%rdi)
|
||||
mov %r15, 0x78(%rdi)
|
||||
.endm
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space
|
||||
.macro TS_ARCH_RESTORE_REGS_ASM
|
||||
mov 0x00(%rdi), %rax
|
||||
mov 0x08(%rdi), %rbx
|
||||
mov 0x10(%rdi), %rcx
|
||||
mov 0x18(%rdi), %rdx
|
||||
mov 0x20(%rdi), %rsp
|
||||
mov 0x28(%rdi), %rbp
|
||||
mov 0x30(%rdi), %rsi
|
||||
mov 0x40(%rdi), %r8
|
||||
mov 0x48(%rdi), %r9
|
||||
mov 0x50(%rdi), %r10
|
||||
mov 0x58(%rdi), %r11
|
||||
mov 0x60(%rdi), %r12
|
||||
mov 0x68(%rdi), %r13
|
||||
mov 0x70(%rdi), %r14
|
||||
mov 0x78(%rdi), %r15
|
||||
mov 0x38(%rdi), %rdi
|
||||
.endm
|
||||
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space of the current test/kernel
|
||||
// RSI = Pointer to the register save space of the test/kernel to restore
|
||||
ts_arch_resume_test_ASM:
|
||||
TS_ARCH_SAVE_REGS_ASM
|
||||
mov %rsi, %rdi
|
||||
TS_ARCH_RESTORE_REGS_ASM
|
||||
mov $0, %rax
|
||||
ret
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space of the current test
|
||||
// RSI = Pointer to the register save space of the kernel to restore
|
||||
ts_arch_resume_kernel_ASM:
|
||||
TS_ARCH_SAVE_REGS_ASM
|
||||
mov %rsi, %rdi
|
||||
TS_ARCH_RESTORE_REGS_ASM
|
||||
mov $0, %rax
|
||||
ret
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space of the current test
|
||||
// RSI = Pointer to the ts_poll function
|
||||
ts_arch_runIdleThread_ASM:
|
||||
|
||||
//Return -- Not yet implemented in X86
|
||||
ret
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space of the kernel
|
||||
// RSI = Pointer to the stack space of the test
|
||||
// RDX = Pointer to the runTest_* function
|
||||
// RCX = Iteration argument for runTest_*
|
||||
ts_arch_enter_init_cleanup_ASM:
|
||||
// Save all the registers
|
||||
TS_ARCH_SAVE_REGS_ASM
|
||||
|
||||
// Temporary save the kernel stack we'll return to
|
||||
mov %rsp, %rax
|
||||
|
||||
// Change the stack
|
||||
mov %rsi, %rsp
|
||||
|
||||
// Save the kernel register storage space pointer so we can restore registers on the return
|
||||
push %rdi
|
||||
|
||||
// Load the iteration argument
|
||||
mov %rcx, %rdi
|
||||
|
||||
// Call runTest_*
|
||||
mov %rcx, %rdi
|
||||
call *%rdx
|
||||
|
||||
// Pop the kernelRegs pointer
|
||||
pop %rdi
|
||||
|
||||
// Restore all the registers
|
||||
TS_ARCH_RESTORE_REGS_ASM
|
||||
|
||||
// Return 1 to indicate that this is a return from runTest_ instead of a resume kernel
|
||||
mov $1, %rax
|
||||
ret
|
||||
|
||||
// Inputs: RDI = Pointer to the register save space of current test
|
||||
// RSI = Pointer to the stack space of the next test
|
||||
// RDX = Pointer to the runTest_* function
|
||||
// RCX = Iteration argument for runTest_*
|
||||
ts_arch_startNextIteration_ASM:
|
||||
|
||||
//Not yet implemented
|
||||
ret
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| exception.c
|
||||
|
|
||||
| Fucntions for exception handling on 'x86' architecture.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
|
||||
|
||||
void arch_exc_globalInit()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
HW_EXC_HANDLER_FUNC* arch_exc_registerHandler(HW_EXC_VECTOR exception, HW_EXC_HANDLER_FUNC* handler)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
HW_EXC_VECTOR arch_exc_queryExceptionCause(void)
|
||||
{
|
||||
return (HW_EXC_VECTOR)0;
|
||||
}
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| interrupt.c
|
||||
|
|
||||
| Fucntions for interrupt handling on 'X86' architecture.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
|
||||
void arch_int_globalInit()
|
||||
{
|
||||
}
|
||||
|
||||
void arch_int_init()
|
||||
{
|
||||
}
|
||||
|
||||
HW_INT_HANDLER_FUNC* arch_int_registerHandler(HW_INT_VECTOR interrupt, HW_INT_HANDLER_FUNC* handler)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
UINT32 arch_int_enable(UINT32 mask)
|
||||
{
|
||||
return mask;
|
||||
}
|
||||
|
||||
UINT32 arch_int_disable(UINT32 mask)
|
||||
{
|
||||
return mask;
|
||||
}
|
||||
|
||||
void arch_int_set(UINT32 mask)
|
||||
{
|
||||
}
|
||||
|
||||
void arch_int_clear(UINT32 mask)
|
||||
{
|
||||
}
|
||||
|
||||
HW_RESULT arch_int_timerSetTimeout(HW_INT_VECTOR timer, UINT32 timeout)
|
||||
{
|
||||
return HW_E_NOTIMPL;
|
||||
}
|
||||
|
||||
HW_RESULT arch_int_timerSetCompare(HW_INT_VECTOR timer, UINT32 compare)
|
||||
{
|
||||
return HW_E_NOTIMPL;
|
||||
}
|
||||
|
||||
UINT32 arch_int_queryInterrupt(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
UINT32 arch_int_queryEnable(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| main.c
|
||||
|
|
||||
| Architecture specific entry point for Bifrost
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
//extern int platform_init();
|
||||
|
||||
int main(int argc, char* argv[])
|
||||
{
|
||||
//// Only the linux platform is supported for x86 right now, so call the platform specific init and nothing else
|
||||
//platform_init();
|
||||
//initGlobals();
|
||||
|
||||
UINT32 dwpid = hw_getCoreNum();
|
||||
|
||||
// Check if this core is active
|
||||
if(hw_activeCoreList[dwpid])
|
||||
{
|
||||
if(dwpid == bifrostCachedGlobals.tpid)
|
||||
{
|
||||
testDriver(dwpid);
|
||||
}
|
||||
else
|
||||
{
|
||||
testSlave(dwpid);
|
||||
}
|
||||
}
|
||||
|
||||
for(;;){
|
||||
asm volatile("hlt");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
/*-----------------------------------------------------
|
||||
|
|
||||
| preemption.c
|
||||
|
|
||||
| Contains functions used in preemptive tasking
|
||||
| configuration and setup.
|
||||
|
|
||||
|------------------------------------------------------
|
||||
|
|
||||
| Copyright (C) 2011 Microsoft Corporation
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
|
||||
HW_INT_VECTOR_MASK hw_criticalSectionBegin()
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void hw_criticalSectionEnd(HW_INT_VECTOR_MASK intMask)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
// Debug function. This is not public code currently.
|
||||
void hw_resetPreemptionTimer(UINT32 ticks)
|
||||
{
|
||||
|
||||
}
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
######################################################
|
||||
#
|
||||
# sources.imk
|
||||
#
|
||||
# Contains all C source information for the
|
||||
# Bifrost build for x86 architecture.
|
||||
#
|
||||
# Copyright (C) 2016 Microsoft Corporation
|
||||
# All Rights Reserved
|
||||
# Confidential and Proprietary
|
||||
#
|
||||
######################################################
|
||||
|
||||
|
||||
ARCHTYPE := x86
|
||||
|
||||
#
|
||||
# Kernel CFLAGS
|
||||
#
|
||||
X86_KERNEL_CFLAGS = $(DEFAULT_CFLAGS) $(WARNING_CFLAGS)
|
||||
|
||||
|
||||
#
|
||||
# Kernel binary selection--if CUSTOM_KERNEL_CFLAGS
|
||||
# is specified, build a testsuite-specific
|
||||
# version of the kernel under BIN_DIR--otherwise,
|
||||
# use the shared kernel.
|
||||
#
|
||||
X86_KERNEL_BINARY = $(if $(CUSTOM_KERNEL_CFLAGS),$(BIN_DIR)/obj/x86/kernel/bifrost_kernel.so,$(OBJ_ROOT)/x86/$(BFCOMP_MODE)/kernel/bifrost_kernel.so)
|
||||
|
||||
# These files will be compiled as Assembly instead of C++.
|
||||
# Apply the appropriate COMPILE_LANGUAGE override for them
|
||||
X86_ASM_SOURCES := $(BF_SRC_ROOT)/arch/x86/context.s
|
||||
|
||||
X86_O3OPT_SOURCES := $(SHARED_KERNEL_O3OPT_SOURCES) \
|
||||
$(DRIVER_O3OPT_SOURCES)
|
||||
|
||||
X86_SOURCES := $(SHARED_KERNEL_SOURCES) \
|
||||
$(DRIVER_SOURCES) \
|
||||
$(X86_ASM_SOURCES) \
|
||||
$(X86_O3OPT_SOURCES) \
|
||||
$(X86_SYS_SOURCES) \
|
||||
$(BF_SRC_ROOT)/arch/x86/atomic.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/context.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/exception.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/interrupt.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/main.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/preemption.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/suspend.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/terminate.c \
|
||||
$(BF_SRC_ROOT)/arch/x86/time.c
|
||||
|
||||
X86_HEADERS := $(SHARED_HEADERS) \
|
||||
$(BF_SRC_ROOT)/system/include/bifrost_system_api_x86.h \
|
||||
$(BF_SRC_ROOT)/system/include/bifrost_system_constants_x86.h
|
||||
|
||||
X86_IDIRS := $(BF_SRC_ROOT)/arch/x86/include
|
||||
|
||||
# Add library IDIRS
|
||||
ARCHTYPE := x86
|
||||
$(eval $(kernel_lib_template))
|
||||
|
||||
|
||||
define kernel_objs_template
|
||||
|
||||
FLAG := $$(call TOLOWER,$$(FLAG_UPPER))
|
||||
|
||||
#
|
||||
# x86 kernel objects and rules
|
||||
#
|
||||
|
||||
X86_KERNEL_OBJS := $$(X86_SOURCES:$(BF_SRC_ROOT)/%=$(OBJ_ROOT)/x86/$$(FLAG)/kernel/%.o)
|
||||
X86_O3OPT_OBJS := $$(X86_O3OPT_SOURCES:$(BF_SRC_ROOT)/%=$(OBJ_ROOT)/x86/$$(FLAG)/kernel/%.o)
|
||||
|
||||
$$(filter %.s.o %.S.o,$$(X86_KERNEL_OBJS)): COMPILE_LANGUAGE := assembler-with-cpp
|
||||
|
||||
# Specify -O3 optimization on a per-file basis
|
||||
$$(X86_O3OPT_OBJS): X86_KERNEL_CFLAGS += -O3
|
||||
|
||||
$$(X86_KERNEL_OBJS) $$(X86_PLAT_$(FLAG_UPPER)_OBJS): $(OBJ_ROOT)/x86/$$(FLAG)/kernel/%.o : $(BF_SRC_ROOT)/% $(X86_HEADERS)
|
||||
@echo Compiling $$< to $$@...
|
||||
@mkdir -p $$(@D)
|
||||
@$(COMPILE) -c -static -shared \
|
||||
-x $$(COMPILE_LANGUAGE) \
|
||||
$$(X86_KERNEL_CFLAGS) $(FLAG_UPPER:%=-D%) \
|
||||
-D__X86__ \
|
||||
$(BIFROST_IDIRS:%=-I%) \
|
||||
$(X86_IDIRS:%=-I%) \
|
||||
$(X86_SYS_IDIRS:%=-I%) \
|
||||
$$< -o $$@
|
||||
|
||||
#
|
||||
# Bifrost kernel binary for this architecture
|
||||
#
|
||||
$(OBJ_ROOT)/x86/$$(FLAG)/kernel/bifrost_kernel.so: $$(X86_KERNEL_OBJS)
|
||||
@echo Linking $$@...
|
||||
@mkdir -p $$(@D)
|
||||
ld -r $$^ -o $$@
|
||||
|
||||
|
||||
endef
|
||||
|
||||
$(foreach FLAG_UPPER,$(BFCOMP_FLAGS_UPPER),$(eval $(kernel_objs_template)))
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| suspend.c
|
||||
|
|
||||
| Fucntions for suspending the execution on a core for 'x86' architecture.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2014 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
#include "bifrost_private.h"
|
||||
|
||||
void arch_suspend()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| terminate.c
|
||||
|
|
||||
| Fucntions for terminate the execution on a core for 'x86' architecture.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2014 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
#include "bifrost_private.h"
|
||||
|
||||
void hw_terminate()
|
||||
{
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*-----------------------------------------------------
|
||||
|
|
||||
| time.c
|
||||
|
|
||||
| Contains functions for obtaining the current time
|
||||
| with the x86 architecture.
|
||||
|
|
||||
|------------------------------------------------------
|
||||
|
|
||||
| Copyright (C) 2011 Microsoft Corporation
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "bifrost_private.h"
|
||||
|
||||
HW_RESULT arch_int_startPreemptionTimer()
|
||||
{
|
||||
return S_OK;
|
||||
}
|
||||
|
||||
HW_RESULT arch_int_stopPreemptionTimer()
|
||||
{
|
||||
return S_OK;
|
||||
}
|
||||
|
||||
UINT64 hw_getCycleCount()
|
||||
{
|
||||
UINT64 currentTime = RDTSC();
|
||||
|
||||
//
|
||||
// The TSC register increments at a constant rate regardless
|
||||
// of power state so we can generally count on it for a realtime
|
||||
// reading.
|
||||
//
|
||||
return currentTime - bifrostCachedGlobals.hw_beginning_cycle_count;
|
||||
}
|
||||
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* Assembly functions to support interlocked exchange
|
||||
*/
|
||||
|
||||
.text
|
||||
|
||||
// a2 = int ptr
|
||||
// a3 = val
|
||||
.global arch_interlocked_compare_exchange
|
||||
//uint32_t hw_interlocked_compare_exchange(uint32_t* addr, uint32_t compare, uint32_t val)
|
||||
|
||||
.align 4
|
||||
arch_interlocked_compare_exchange:
|
||||
entry a1, 16
|
||||
wsr.scompare1 a3
|
||||
s32c1i a4, a2, 0
|
||||
mov a2, a4
|
||||
retw
|
||||
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
#include "bifrost_hs_intr.h"
|
||||
#include "bifrost_hs_mem.h"
|
||||
#include "bifrost_hs_boot.h"
|
||||
#include "bifrost_hs_context.h"
|
||||
#include "bifrost_types.h"
|
||||
#include "bifrost_system_constants_xtensa.h"
|
||||
#include "interrupt.h"
|
||||
#include "context.h"
|
||||
#include "atomic.h"
|
||||
#include "mem.h"
|
||||
|
||||
int32_t ke_hal_setup(hw_arch_bootinfo_t *bootinfo)
|
||||
{
|
||||
int32_t result = 0;
|
||||
if(bootinfo == NULL)
|
||||
return -1;
|
||||
|
||||
result = arch_interrupt_init(&bootinfo->int_info);
|
||||
|
||||
if(result != 0)
|
||||
return result;
|
||||
|
||||
result = arch_mem_init(bootinfo);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
void ke_set_timer_timeout(uint32_t ms)
|
||||
{
|
||||
uint32_t timeout = ms * (PROC_FREQUENCY_MHZ * 1000);
|
||||
arch_set_timer_timeout(timeout);
|
||||
return;
|
||||
}
|
||||
|
||||
void ke_trigger_intr(uint32_t core, uint32_t vec)
|
||||
{
|
||||
arch_trigger_interrupt(core, vec);
|
||||
}
|
||||
|
||||
// IRQL on Xtensa has identical mapping between kernel defined and arch specific mask
|
||||
|
||||
hw_irql_t ke_set_irql(hw_irql_t irql)
|
||||
{
|
||||
return arch_set_irql(irql);
|
||||
}
|
||||
|
||||
hw_irql_t ke_get_irql()
|
||||
{
|
||||
return arch_get_irql();
|
||||
}
|
||||
|
||||
void ke_context_switch(void *intr_context, void *old_context, void *new_context)
|
||||
{
|
||||
return arch_context_switch((UserFrame*)intr_context, (UserFrame*)old_context, (UserFrame*)new_context);
|
||||
}
|
||||
|
||||
void ke_create_context(void *context, void *pc, void *sp, hw_irql_t irql, void *arg)
|
||||
{
|
||||
arch_create_context((UserFrame*)context, pc, sp, (uint32_t)irql, arg);
|
||||
}
|
||||
|
||||
uint32_t ke_get_current_core()
|
||||
{
|
||||
return xthal_get_prid();
|
||||
}
|
||||
|
||||
void ke_flush_addr(void *addr, uint32_t num_of_cacheline)
|
||||
{
|
||||
xthal_dcache_region_writeback_inv(addr, num_of_cacheline * HW_CACHELINE_SIZE);
|
||||
}
|
||||
|
||||
hw_intr_handler_t ke_register_intr_handler(uint32_t vec, hw_intr_handler_t handler, void *context)
|
||||
{
|
||||
return arch_register_intr_handler(vec, handler, context);
|
||||
}
|
||||
|
||||
int32_t ke_interlocked_exchange(int32_t *addr, int32_t data)
|
||||
{
|
||||
int32_t orig = *addr;
|
||||
while(arch_interlocked_compare_exchange(addr, orig, data) != orig)
|
||||
{
|
||||
orig = *addr;
|
||||
}
|
||||
return orig;
|
||||
}
|
||||
|
||||
|
||||
int32_t ke_interlocked_compare_exchange(int32_t *addr, int32_t compare, int32_t val)
|
||||
{
|
||||
return arch_interlocked_compare_exchange(addr, compare, val);
|
||||
}
|
||||
|
||||
int32_t ke_interlocked_increment(int32_t *addr, int32_t val)
|
||||
{
|
||||
int32_t orig = *addr;
|
||||
while(arch_interlocked_compare_exchange(addr, orig, orig + val) != orig)
|
||||
{
|
||||
orig = *addr;
|
||||
}
|
||||
return orig;
|
||||
}
|
||||
|
||||
|
||||
void ke_register_exc_handler(hw_exc_type_t type, hw_exc_handler_t handler)
|
||||
{
|
||||
switch(type)
|
||||
{
|
||||
case invalid_op_exc:
|
||||
arch_register_exc_handler(HW_EXC_ILLEGAL, handler);
|
||||
case debug_exc:
|
||||
break;
|
||||
case div_by_zero_exc:
|
||||
arch_register_exc_handler(HW_EXC_DIVIDE_BY_ZERO, handler);
|
||||
case unrecoverable_exc:
|
||||
break;
|
||||
case unsupported_thr_fatal_exc:
|
||||
break;
|
||||
case unsupported_thr_nonfatal_exc:
|
||||
break;
|
||||
case page_fault_exc:
|
||||
arch_register_exc_handler(HW_EXC_INSTR_ADDR_ERROR, handler);
|
||||
arch_register_exc_handler(HW_EXC_INSTR_DATA_ERROR, handler);
|
||||
arch_register_exc_handler(HW_EXC_LOAD_STORE_ADDR_ERROR, handler);
|
||||
arch_register_exc_handler(HW_EXC_LOAD_STORE_DATA_ERROR, handler);
|
||||
break;
|
||||
case general_protection_exc:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| 1BL.S
|
||||
|
|
||||
| 1BL for 'xtensa' architecture.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2014 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
.equiv PCIE_RESET_RELEASE_ADDR, 0x04080090
|
||||
.equiv PCIE_RESET_RELEASE_DATA, 0x00000003
|
||||
.equiv INTC_P0_0_CLEAR_ADDR, 0x04000008
|
||||
.equiv INTC_P0_0_CLEAR_BIT, 0
|
||||
.equiv INTC_P0_0_CLEAR_BIT_MASK, 0x1
|
||||
.equiv INTC_P1_0_CLEAR_ADDR, 0x04000088
|
||||
.equiv INTC_P1_0_CLEAR_BIT, 1
|
||||
.equiv DRAM_RESET_TABLE_BASE, 0xA1000000
|
||||
#ifdef USE_ALT_VECTOR
|
||||
.equiv SRAM_RESET_VECTOR, 0x00100020
|
||||
#else
|
||||
.equiv SRAM_RESET_VECTOR, 0x00100000
|
||||
#endif
|
||||
.equiv SBOOT_RESET_VECTOR, 0x07108000
|
||||
|
||||
.equiv SCRPAD0_ADDR, 0x02000030
|
||||
.equiv SCRPAD0_DATA_BIT, 1
|
||||
|
||||
.begin no-absolute-literals
|
||||
.section .SharedResetVector.text, "ax"
|
||||
|
||||
.align 4
|
||||
.global _SharedResetVector
|
||||
_SharedResetVector:
|
||||
j .SharedResetHandler
|
||||
|
||||
.align 4
|
||||
.literal_position
|
||||
|
||||
.align 4
|
||||
.SharedResetHandler:
|
||||
rsr.prid a0
|
||||
bltui a0, 2, .ControlNode
|
||||
|
||||
.CoreN:
|
||||
movi a1, DRAM_RESET_TABLE_BASE
|
||||
addx4 a1, a0, a1
|
||||
l32i a1, a1, 0
|
||||
jx a1
|
||||
|
||||
.ControlNode:
|
||||
beqi a0, 0, .Core0 // dispatch for core0
|
||||
|
||||
.Core1:
|
||||
#ifndef L2BOOT
|
||||
movi a1, INTC_P1_0_CLEAR_ADDR
|
||||
.Poll:
|
||||
l32ai a2, a1, 0
|
||||
bbci a2, INTC_P1_0_CLEAR_BIT, .Poll
|
||||
s32i a2, a1, 0
|
||||
#endif
|
||||
j .CoreN
|
||||
|
||||
.Core0:
|
||||
#ifndef L2BOOT
|
||||
movi a0, PCIE_RESET_RELEASE_ADDR
|
||||
movi a1, PCIE_RESET_RELEASE_DATA
|
||||
l32i a2, a0, 0
|
||||
beq a1, a2, .PCIE_Initialized
|
||||
s32i a1, a0, 0
|
||||
.PCIE_Initialized:
|
||||
#ifdef PCIE_SYNC
|
||||
movi a1, INTC_P0_0_CLEAR_ADDR
|
||||
.Poll_2bl:
|
||||
l32ai a2, a1, 0
|
||||
bbci a2, INTC_P0_0_CLEAR_BIT, .Poll_2bl
|
||||
s32i a2, a1, 0
|
||||
#endif
|
||||
|
||||
#ifdef SBOOT
|
||||
movi a0, SBOOT_RESET_VECTOR
|
||||
#else
|
||||
movi a0, SRAM_RESET_VECTOR
|
||||
l32i a0, a0, 0
|
||||
#endif
|
||||
jx a0
|
||||
#else // L2BOOT
|
||||
movi a0, DRAM_RESET_TABLE_BASE
|
||||
l32i a0, a0, 0
|
||||
jx a0
|
||||
#endif
|
||||
|
||||
.size _SharedResetVector, . - _SharedResetVector
|
||||
.end no-absolute-literals
|
||||
|
||||
|
|
@ -1,368 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| 2bl.c
|
||||
|
|
||||
| main of boot loader which is called from reset handler.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "init_helper.h"
|
||||
#include "HuPPCIeATU.h"
|
||||
#include "HupreBootDefines.h"
|
||||
#include "hup_chip.h"
|
||||
#define BOOT_STACK_SIZE (0x400)
|
||||
extern int __stack;
|
||||
|
||||
BOOT_DIAG* gBootDiagPtr = (BOOT_DIAG*)BOOT_DIAG_BASE_ADDR;
|
||||
#ifndef PCIE_SYNC
|
||||
INIT_OPTION gInitOption __attribute__ ((section(".sram_init_opt.data")));
|
||||
INIT_OPTION* gInitOptionPtr = (INIT_OPTION*)&gInitOption;
|
||||
#else
|
||||
INIT_OPTION* gInitOptionPtr = (INIT_OPTION*)INIT_OPTION_BASE_ADDR;
|
||||
#endif
|
||||
|
||||
extern void dramc_init(int dpd);
|
||||
|
||||
void
|
||||
StatusUpdate(
|
||||
HUPRE_BOOT_STATUS Status
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Perform a status update the SoC can see to trace our progress.
|
||||
|
||||
Arguments:
|
||||
|
||||
Status - Status to write
|
||||
|
||||
Return value:
|
||||
|
||||
None.
|
||||
|
||||
--*/
|
||||
{
|
||||
reg_write32(HUP_CN_MISC_INTC_SCRATCH_REG0, Status);
|
||||
}
|
||||
|
||||
void
|
||||
DoDramInit()
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Setup DDR.
|
||||
|
||||
Arguments:
|
||||
|
||||
None.
|
||||
|
||||
Return value:
|
||||
|
||||
None.
|
||||
|
||||
--*/
|
||||
{
|
||||
dramc_init(0);
|
||||
}
|
||||
|
||||
void
|
||||
MapAtu()
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Temporary ATU setup.
|
||||
|
||||
ISSUE-2014/04/10-jloeser: Remove once HupDriver.sys ATU setup has been
|
||||
verified.
|
||||
|
||||
Arguments:
|
||||
|
||||
None.
|
||||
|
||||
Return value:
|
||||
|
||||
None.
|
||||
|
||||
--*/
|
||||
{
|
||||
UINT32 msiSocHigh;
|
||||
UINT32 msiSocLow;
|
||||
|
||||
volatile PCIE_ATU_REGISTERS* regs;
|
||||
|
||||
regs = (volatile PCIE_ATU_REGISTERS *)(HUP_ADDRESS_pcie + PCIE_ATU_STARTING_BYTE_OFFSET);
|
||||
//
|
||||
// prepare for writing outbound ATU entry 31
|
||||
//
|
||||
regs->VIEWPORT.Bits.REGION_DIR = PCIE_ATU_REGION_DIR_OUTBOUND; //0;
|
||||
|
||||
regs->VIEWPORT.Bits.REGION_INDEX = 31;
|
||||
|
||||
regs->LWR_BASE.Raw = XTENSA_PCIE_END - 4096;
|
||||
regs->UPPER_BASE = 0;
|
||||
regs->LIMIT_ADDR.Raw = XTENSA_PCIE_END - 1;
|
||||
|
||||
//
|
||||
// Obtain MSI address: Found at offsets 0x54 (low), 0x58 (high)
|
||||
// from PCI config space.
|
||||
//
|
||||
msiSocLow = *(PUINT32)(HUP_ADDRESS_pcie + 0x54);
|
||||
msiSocHigh = *(PUINT32)(HUP_ADDRESS_pcie + 0x58);
|
||||
|
||||
regs->LWR_TARGET_ADDR.Raw = msiSocLow & ~0xFFFUL;
|
||||
regs->UPPER_TARGET_ADDR = msiSocHigh;
|
||||
|
||||
regs->REGION_CTRL1.Raw = 0;
|
||||
regs->REGION_CTRL3.Raw = 0;
|
||||
regs->REGION_CTRL2.Raw = 0;
|
||||
regs->REGION_CTRL2.OutboundBits.REGION_EN = 1;
|
||||
}
|
||||
|
||||
void
|
||||
DoGetMsiDetails(
|
||||
PUINT32* MsiAddress,
|
||||
PUINT32 MsiData0
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Obtain MSI address and adata.
|
||||
|
||||
The last 4KB of the PCI range have been setup by the SoC to contain the
|
||||
the MSI page.
|
||||
|
||||
The 12-bit offset into the PCI range and the data base word are found
|
||||
found in the PCIe config space.
|
||||
|
||||
Arguments:
|
||||
|
||||
MsiAddress - Upon return, will contain the address to write to to trigger
|
||||
an MSI.
|
||||
|
||||
MsiData0 - Upon return, will contain the data to write to trigger MSI 0.
|
||||
|
||||
Return value:
|
||||
|
||||
None.
|
||||
|
||||
--*/
|
||||
{
|
||||
UINT32 msiSocLow;
|
||||
|
||||
//
|
||||
// ISSUE-2014/04/10-jloeser: Remove once HupDriver.sys ATU setup has been
|
||||
// verified.
|
||||
//
|
||||
//MapAtu();
|
||||
|
||||
//
|
||||
// Obtain MSI address: Found at offsets 0x54 (low) from PCI config space.
|
||||
//
|
||||
msiSocLow = *(PUINT32)(HUP_ADDRESS_pcie + 0x54);
|
||||
|
||||
*MsiAddress = (PUINT32)(XTENSA_PCIE_END - 4096 + (msiSocLow & 0xFFCUL));
|
||||
|
||||
//
|
||||
// Obtain MSI data: Found in lower 16 bits at offset 0x5C of PCI config
|
||||
// space.
|
||||
//
|
||||
*MsiData0 = *(PUINT32)(HUP_ADDRESS_pcie + 0x5C) & 0xFFFF;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
DoSendMsi(
|
||||
PUINT32 MsiAddress,
|
||||
UINT32 MsiData
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Signal DDR readiness to SoC by sending it an MSI.
|
||||
|
||||
Arguments:
|
||||
|
||||
MsiAddress - Address to write to to send an MSI.
|
||||
|
||||
MsiData - Data to write.
|
||||
|
||||
Return value:
|
||||
|
||||
None.
|
||||
|
||||
--*/
|
||||
{
|
||||
__asm__ __volatile__ ( "memw \n" );
|
||||
*MsiAddress = MsiData;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void
|
||||
DoWaitFor3BL()
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Wait for 3BL readyness.
|
||||
|
||||
Arguments:
|
||||
|
||||
None.
|
||||
|
||||
Return value:
|
||||
|
||||
None.
|
||||
|
||||
--*/
|
||||
{
|
||||
UINT32 bits;
|
||||
|
||||
do
|
||||
{
|
||||
bits = *(volatile UINT32*)(HUP_CN_MISC_INTC_P0_0_DATA);
|
||||
} while ((bits & 0x2) == 0);
|
||||
|
||||
//
|
||||
// Ack our interrupt at the interrupt controller.
|
||||
//
|
||||
*(UINT32*)(HUP_CN_MISC_INTC_P0_0_DATA) = bits;
|
||||
}
|
||||
|
||||
#ifdef BASRAM_ONLY
|
||||
|
||||
// Can't declare ANY variables in the function
|
||||
// in which we switch the stack. Otherwise,
|
||||
// they'll write above the top of our stack.
|
||||
// So main will just switch the stack and then
|
||||
// execute its other tasks in a second function
|
||||
int main_body();
|
||||
int main()
|
||||
{
|
||||
// Set up stacks first of all
|
||||
asm volatile(
|
||||
"mov a1, %[stack];"
|
||||
:
|
||||
: [stack] "r" ((int)&__stack - BOOT_STACK_SIZE * get_prid())
|
||||
: "a1"
|
||||
);
|
||||
|
||||
main_body();
|
||||
|
||||
// Bogus return, we should never get here
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main_body()
|
||||
{
|
||||
if(get_prid() == 0)
|
||||
{
|
||||
#ifdef PCIE_SYNC
|
||||
*(r32*)PCIE_RESET_RELEASE_ADDR = PCIE_RESET_RELEASE_DATA;
|
||||
while(*(r32*)HUP_CN_MISC_INTC_P0_0_DATA == 0);
|
||||
*(r32*)HUP_CN_MISC_INTC_P0_0_DATA = 0;
|
||||
#endif
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_STARTED);
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING1_ADDRESS = 0x303FFFF;
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING2_ADDRESS = 0x03FFFFFF;
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING5_ADDRESS = 0xFFFFFFFF;
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING6_ADDRESS = 0xFFFFFFFF;
|
||||
if(gInitOptionPtr->dramc_init_opt.std.DRAMC_INIT_FOR_BASRAM_MODE ||
|
||||
get_platform_type() == PLAT_VEL ||
|
||||
get_platform_type() == PLAT_PAL)
|
||||
{
|
||||
gBootDiagPtr->dramc.init_time.start = (unsigned long long )get_ccount() * 2;
|
||||
DoDramInit();
|
||||
gBootDiagPtr->dramc.init_time.end = (unsigned long long )get_ccount() * 2;
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_DDR_UP);
|
||||
}
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_READY_FOR_3BL);
|
||||
set_dramc_ready();
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_DONE);
|
||||
}
|
||||
else if(get_prid() == 1)
|
||||
{
|
||||
wait_for_dramc_ready();
|
||||
}
|
||||
|
||||
asm volatile(
|
||||
"movi a0, 0x20122000 \n"
|
||||
"jx a0 \n"
|
||||
);
|
||||
|
||||
// Bogus return, we should never get here
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else //!BASRAM_ONLY
|
||||
|
||||
// No stack switching on this path
|
||||
// since only one core executes it
|
||||
int main()
|
||||
{
|
||||
PUINT32 msiAddress;
|
||||
UINT32 msiData0;
|
||||
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_STARTED);
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING1_ADDRESS = 0x303FFFF;
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING2_ADDRESS = 0x03FFFFFF;
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING5_ADDRESS = 0xFFFFFFFF;
|
||||
*(r32*)HUP_CHIP_POR_CLOCKGATING6_ADDRESS = 0xFFFFFFFF;
|
||||
if(gInitOptionPtr->dramc_init_opt.std.NO_DRAMC_INIT == 0)
|
||||
{
|
||||
gBootDiagPtr->dramc.init_time.start = (unsigned long long )get_ccount() * 2;
|
||||
DoDramInit();
|
||||
gBootDiagPtr->dramc.init_time.end = (unsigned long long )get_ccount() * 2;
|
||||
}
|
||||
#ifndef VALIDATION_MODE
|
||||
set_dramc_ready();
|
||||
#else
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_DDR_UP);
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_READY_FOR_3BL);
|
||||
DoGetMsiDetails(&msiAddress, &msiData0);
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_MSI_MAPPED);
|
||||
DoSendMsi(msiAddress, msiData0);
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_MSI_SENT);
|
||||
DoWaitFor3BL();
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_SEEN_3BL);
|
||||
StatusUpdate(HUPRE_BOOT_STATUS_2BL_DONE);
|
||||
#endif //VALIDATION_MODE
|
||||
|
||||
// Invalidate cached stack
|
||||
asm volatile(
|
||||
"mov a2, %[addr]\n"
|
||||
"loopnez %[size], .sram_stack_inv_end\n"
|
||||
"dhi a2, 0\n"
|
||||
"addi a2, a2, 64\n"
|
||||
".sram_stack_inv_end:\n"
|
||||
:
|
||||
: [addr] "r" ((int)&__stack - BOOT_STACK_SIZE), [size] "r" (BOOT_STACK_SIZE / XCHAL_DCACHE_LINESIZE)
|
||||
: "a2"
|
||||
);
|
||||
|
||||
// Transfer control via jump table
|
||||
asm volatile(
|
||||
"movi a0, 0xA1000000 \n"
|
||||
"l32i a0, a0, 0 \n"
|
||||
"jx a0 \n"
|
||||
);
|
||||
|
||||
// Bogus return, we should never get here
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif //BASRAM_ONLY
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* Alternate reset vector
|
||||
*/
|
||||
.begin literal_prefix .AltResetVector
|
||||
.section .AltResetVector.text, "ax"
|
||||
|
||||
/* Minimal vector, just jump to the handler dfefined below */
|
||||
.align 4
|
||||
.global _AltResetVector
|
||||
_AltResetVector:
|
||||
j _AltResetHandler
|
||||
|
||||
.size _AltResetVector, . - _AltResetVector
|
||||
|
||||
|
||||
/* Alternate reset vector handler, just jump to the normal boot vector */
|
||||
.align 4
|
||||
.literal_position // tells the assembler/linker to place literals here
|
||||
|
||||
.align 4
|
||||
.global _AltResetHandler
|
||||
_AltResetHandler:
|
||||
j.l 0x7100000, a0
|
||||
.end literal_prefix
|
||||
|
||||
|
|
@ -1,269 +0,0 @@
|
|||
//---------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) Microsoft Corporation. All rights reserved.
|
||||
//
|
||||
// Abstract:
|
||||
// Contains hardware data structure definitions of the internal
|
||||
// address translation unit (iATU) of the PCIe endpoint on the HuP.
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#pragma once
|
||||
|
||||
static const UINT32 HUP_ADDRESS_pcie = 0x04400000;
|
||||
static const UINT32 XTENSA_PCIE_BASE = 0x3E000000;
|
||||
static const UINT32 XTENSA_PCIE_SIZE = 0x02000000;
|
||||
static const UINT32 XTENSA_PCIE_END = 0x40000000;
|
||||
|
||||
// These constants are configured in silicon and cannot be read by
|
||||
// software.
|
||||
//
|
||||
static const UINT32 PCIE_ATU_CX_INTERNAL_ATU_ENABLE = 1; // Indicates that the ATU is enabled
|
||||
static const UINT32 PCIE_ATU_CX_ATU_NUM_OUTBOUND_REGIONS = 32; // Maximum number of outbound translation regions that can be defined
|
||||
static const UINT32 PCIE_ATU_CX_ATU_NUM_INBOUND_REGIONS = 32; // Maximum number of inbound translation regions that can be defined
|
||||
static const UINT32 PCIE_ATU_CX_ATU_MIN_REGION_SIZE = (UINT32)(4 * 1024); // Minimum size and alignment of a single translation region
|
||||
|
||||
// Starting byte and DWORD offsets of ATU registers in PCIe config space
|
||||
static const UINT32 PCIE_ATU_STARTING_BYTE_OFFSET = 0x900;
|
||||
static const UINT32 PCIE_ATU_STARTING_DWORD_OFFSET = 0x900 >> 2;
|
||||
|
||||
|
||||
// Byte and DWORD offsets of the last ATU register in PCIe config space.
|
||||
static const UINT32 PCIE_ATU_LAST_REGISTER_BYTE_OFFSET = 0x920;
|
||||
static const UINT32 PCIE_ATU_LAST_REGISTER_DWORD_OFFSET = 0x920 >> 2;
|
||||
|
||||
//static const UINT32 PCIE_ATU_REGION_DIR_OUTBOUND = 0;
|
||||
//static const UINT32 PCIE_ATU_REGION_DIR_INBOUND = 1;
|
||||
#define PCIE_ATU_REGION_DIR_OUTBOUND 0;
|
||||
#define PCIE_ATU_REGION_DIR_INBOUND 1;
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////
|
||||
// ATU Register Definitions.
|
||||
// Register byte offsets are in comments.
|
||||
// Where the spec defines inbound and outbound registers at the same
|
||||
// offset, if they are identical then only one version is defined here.
|
||||
// If they are not identical then the register contains a union of 2
|
||||
// bitfield structs (one for each direction).
|
||||
//
|
||||
// The viewport register selects a region and direction for subsequent
|
||||
// register read/write operations.
|
||||
//
|
||||
|
||||
//////////////////////////////////////
|
||||
// Example 1:
|
||||
// ASIC-side code to set outbound region 2 to map the first 4K
|
||||
// of the HuP PCIe 1GB data window to a specific SoC address
|
||||
/*
|
||||
|
||||
PPCIE_ATU_REGISTERS pRegisters = (PPCIE_ATU_REGISTERS)(0x4400000 + PCIE_ATU_STARTING_BYTE_OFFSET); // 0x4400000 is start of PCIe config space in HuP memory map
|
||||
|
||||
pRegisters->VIEWPORT.Bits.REGION_DIR = PCIE_ATU_REGION_DIR_OUTBOUND;
|
||||
pRegisters->VIEWPORT.Bits.REGION_INDEX = 2;
|
||||
|
||||
|
||||
pRegisters->LWR_BASE.Raw = 0x40000000; // 0x400000000 is start of 1GB PCIe data window in HuP memory map. This must be 4K-aligned.
|
||||
pRegisters->UPPER_BASE = 0;
|
||||
pRegisters->LIMIT_ADDR.Raw = 0x40000FFF; // create a 4K mapping. This is the lower 32-bits of the address of the last byte in the mapping. (Upper bits are defined by UPPER_BASE).
|
||||
pRegisters->LWR_TARGET_ADDR.Raw = SocAddress.LowPart;
|
||||
pRegisters->UPPER_TARGET_ADDR = SocAddress.HighPart;
|
||||
|
||||
pRegisters->REGION_CTRL1.Raw = 0;
|
||||
pRegisters->REGION_CTRL3.Raw = 0;
|
||||
pRegisters->REGION_CTRL2.Raw = 0;
|
||||
pRegisters->REGION_CTRL2.OutboundBits.REGION_EN = 1; // Indicates that the region mapping should be used. Always set this register last after all other registers for the region have been programmed.
|
||||
|
||||
|
||||
////////////////////////////
|
||||
// Example 2:
|
||||
// SoC-side code to set inbound region 3 to map the INTC register set
|
||||
// on BAR 0.
|
||||
|
||||
PPCIE_ATU_REGISTERS pRegisters = (PPCIE_ATU_REGISTERS)(pBAR1 + PCIE_ATU_STARTING_BYTE_OFFSET); // Assumes that pBAR1 was set to the system virtual address of the start of BAR 1 from a prior call to MmMapIoSpace and that BAR 1 maps to the PCIe core register set.
|
||||
|
||||
pRegisters->VIEWPORT.Bits.REGION_DIR = PCIE_ATU_REGION_DIR_INBOUND;
|
||||
pRegisters->VIEWPORT.Bits.REGION_INDEX = 3;
|
||||
|
||||
pRegisters->LWR_BASE.Raw = pBAR0Physical; // Assumes that pBAR0Physical was set to the SoC's 4K-aligned starting physical address for BAR 0 assigned by Windows and received during IRP_MN_START_DEVICE or PrepareHardware
|
||||
pRegisters->UPPER_BASE = 0; // Assumes 32-bit Windows. If running on 64-bit set UPPER_BASE to upper DWORD of pBAR0Physical
|
||||
pRegisters->LIMIT_ADDR.Raw = pBAR0Physical + 0xFFF; // Create a 4K mapping. This is the lower 32-bits of the address of the last byte in the mapping. (Upper bits are defined by UPPER_BASE).
|
||||
pRegisters->LWR_TARGET_ADDR.Raw = 0x4000000; // Start of INTC registers in HuP memory map. Must be 4K-aligned.
|
||||
pRegisters->UPPER_TARGET_ADDR = 0; // HuP uses 32-bit addressing so high word is zero
|
||||
|
||||
pRegisters->REGION_CTRL1.Raw = 0;
|
||||
pRegisters->REGION_CTRL2.Raw = 0;
|
||||
pRegisters->REGION_CTRL3.Raw = 0;
|
||||
pRegisters->REGION_CTRL2.InboundBits.BAR_NUM = 0; // Shown for completeness. Setting Raw to zero earlier already set this bit to zero. For other BARs set this field to the BAR number.
|
||||
pRegisters->REGION_CTRL2.InboundBits.REGION_EN = 1;
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
typedef struct PCIeATUViewPortBits
|
||||
{
|
||||
UINT32 REGION_INDEX:5;
|
||||
UINT32 VP_RSVD:26;
|
||||
UINT32 REGION_DIR:1;
|
||||
} PCIE_ATU_VIEWPORT_BITS;
|
||||
|
||||
typedef union PCIeATUViewport
|
||||
{
|
||||
PCIE_ATU_VIEWPORT_BITS Bits;
|
||||
UINT32 Raw;
|
||||
|
||||
} PCIE_ATU_VIEWPORT;
|
||||
|
||||
|
||||
|
||||
// Per-direction, per-channel registers
|
||||
//
|
||||
typedef struct PCIeATURegionCtrl1Bits
|
||||
{
|
||||
UINT32 TYPE:5;
|
||||
UINT32 TC:3;
|
||||
UINT32 TD:1;
|
||||
UINT32 ATTR:2;
|
||||
UINT32 IDO:1;
|
||||
UINT32 TH:1;
|
||||
UINT32 RSVD_P_13:3;
|
||||
UINT32 AT:2;
|
||||
UINT32 PH:2;
|
||||
UINT32 CTRL_1_FUNC_NUM:5;
|
||||
UINT32 RSVDP_25:7;
|
||||
} PCIE_ATU_REGION_CTRL1_BITS;
|
||||
|
||||
typedef union PCIeATURegionCtrl1
|
||||
{
|
||||
PCIE_ATU_REGION_CTRL1_BITS Bits;
|
||||
UINT32 Raw;
|
||||
} PCIE_ATU_REGION_CTRL1;
|
||||
|
||||
|
||||
|
||||
typedef struct PCIeATURegionCtrl2OutboundBits
|
||||
{
|
||||
UINT32 MSG_CODE:8;
|
||||
UINT32 RSVDP_8:11;
|
||||
UINT32 FUNC_BYPASS:1;
|
||||
UINT32 RSVDP_20:7;
|
||||
UINT32 DMA_BYPASS:1;
|
||||
UINT32 CFG_SHIFT_MODE:1;
|
||||
UINT32 INVERT_MODE:1;
|
||||
UINT32 RSVDP_30:1;
|
||||
UINT32 REGION_EN:1;
|
||||
} PCIE_ATU_REGION_CTRL2_OUTBOUND_BITS;
|
||||
|
||||
typedef struct PCIeATURegionCtrl2InboundBits
|
||||
{
|
||||
UINT32 MSG_CODE:8;
|
||||
UINT32 BAR_NUM:3;
|
||||
UINT32 RSVDP_11:3;
|
||||
UINT32 TC_MATCH_EN:1;
|
||||
UINT32 TD_MATCH_EN:1;
|
||||
UINT32 ATTR_MATCH_EN:1;
|
||||
UINT32 TH_MATCH_EN:1;
|
||||
UINT32 AT_MATCH_EN:1;
|
||||
UINT32 FUNC_MATCH_EN:1;
|
||||
UINT32 VF_MATCH_EN:1;
|
||||
UINT32 MSG_CODE_MATCH_EN:1;
|
||||
UINT32 PH_MATCH_EN:1;
|
||||
UINT32 RSVDP_23:1;
|
||||
UINT32 RESPONSE_CODE:2;
|
||||
UINT32 RSVDP_26:1;
|
||||
UINT32 FUZZY_TYPE_MATCH_CODE:1;
|
||||
UINT32 CFG_SHIFT_MODE:1;
|
||||
UINT32 INVERT_MODE:1;
|
||||
UINT32 MATCH_MODE:1;
|
||||
UINT32 REGION_EN:1;
|
||||
} PCIE_ATU_REGION_CTRL2_INBOUND_BITS;
|
||||
|
||||
|
||||
typedef union PCIeATURegionCtrl2
|
||||
{
|
||||
PCIE_ATU_REGION_CTRL2_OUTBOUND_BITS OutboundBits;
|
||||
PCIE_ATU_REGION_CTRL2_INBOUND_BITS InboundBits;
|
||||
UINT32 Raw;
|
||||
} PCIE_ATU_REGION_CTRL2;
|
||||
|
||||
|
||||
typedef struct PCIeATULwrBaseBits
|
||||
{
|
||||
UINT32 LWR_BASE_HW:12;
|
||||
UINT32 LWR_BASE_RW:20;
|
||||
} PCIE_ATU_LWR_BASE_BITS;
|
||||
|
||||
|
||||
typedef union PCIeATULwrBase
|
||||
{
|
||||
PCIE_ATU_LWR_BASE_BITS Bits;
|
||||
UINT32 Raw;
|
||||
} PCIE_ATU_LWR_BASE;
|
||||
|
||||
|
||||
typedef struct PCIeATULimitAddrBits
|
||||
{
|
||||
UINT32 LIMIT_ADDR_HW:12;
|
||||
UINT32 LIMIT_ADDR_RW:20;
|
||||
} PCIE_ATU_LIMIT_ADDR_BITS;
|
||||
|
||||
typedef union PCIeATULimitAddr
|
||||
{
|
||||
PCIE_ATU_LIMIT_ADDR_BITS Bits;
|
||||
UINT32 Raw;
|
||||
} PCIE_ATU_LIMIT_ADDR;
|
||||
|
||||
typedef struct PCIeATULwrTargetAddrBits
|
||||
{
|
||||
UINT32 LWR_TARGET_ADDR_HW:12;
|
||||
UINT32 LWR_TARGET_ADDR_RW:20;
|
||||
} PCIE_ATU_LWR_TARGET_ADDR_BITS;
|
||||
|
||||
typedef union PCIeATULwrTargetAddr
|
||||
{
|
||||
PCIE_ATU_LWR_TARGET_ADDR_BITS Bits;
|
||||
UINT32 Raw;
|
||||
} PCIE_ATU_LWR_TARGET_ADDR;
|
||||
|
||||
|
||||
typedef struct PCIeATURegionCtrl3Bits
|
||||
{
|
||||
UINT32 VF_NUMBER:1;
|
||||
UINT32 RSVDP_1:30;
|
||||
UINT32 VF_ACTIVE:1;
|
||||
} PCIE_ATU_REGION_CTRL3_BITS;
|
||||
|
||||
|
||||
typedef union PCIeATURegionCtrl3
|
||||
{
|
||||
PCIE_ATU_REGION_CTRL3_BITS Bits;
|
||||
UINT32 Raw;
|
||||
} PCIE_ATU_REGION_CTRL3;
|
||||
|
||||
|
||||
|
||||
// Full register set definition
|
||||
//
|
||||
typedef struct PCIeATURegisters
|
||||
{
|
||||
PCIE_ATU_VIEWPORT VIEWPORT; // 0x900
|
||||
PCIE_ATU_REGION_CTRL1 REGION_CTRL1; // 0x904
|
||||
PCIE_ATU_REGION_CTRL2 REGION_CTRL2; // 0x908
|
||||
PCIE_ATU_LWR_BASE LWR_BASE; // 0x90C
|
||||
UINT32 UPPER_BASE; // 0x910
|
||||
PCIE_ATU_LIMIT_ADDR LIMIT_ADDR; // 0x914
|
||||
PCIE_ATU_LWR_TARGET_ADDR LWR_TARGET_ADDR; // 0x918
|
||||
UINT32 UPPER_TARGET_ADDR; // 0x91C
|
||||
PCIE_ATU_REGION_CTRL3 REGION_CTRL3; // 0x920
|
||||
|
||||
} PCIE_ATU_REGISTERS, *PPCIE_ATU_REGISTERS;
|
||||
|
||||
//C_ASSERT(sizeof(PCIE_ATU_VIEWPORT) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_REGION_CTRL1) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_REGION_CTRL2) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_LWR_BASE) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_LIMIT_ADDR) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_LWR_TARGET_ADDR) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_REGION_CTRL3) == sizeof(UINT32));
|
||||
//C_ASSERT(sizeof(PCIE_ATU_REGISTERS) == (9 * sizeof(UINT32)));
|
||||
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
/*++
|
||||
|
||||
Copyright (c) 2013 Microsoft Corporation. All Rights Reserved.
|
||||
|
||||
Module Name:
|
||||
|
||||
HupreBootDefines.h
|
||||
|
||||
Abstract:
|
||||
|
||||
HupRE boot status value definitions.
|
||||
|
||||
Author:
|
||||
|
||||
Jork Loeser (jloeser) 28-Oct-2013
|
||||
|
||||
--*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//
|
||||
// Status codes propagated from ASIC to SoC.
|
||||
//
|
||||
// While the upper 16 bits carry semantic meaning, the lower 16 bits do not
|
||||
// and can change anytime.
|
||||
//
|
||||
// Upper 16 bits:
|
||||
//
|
||||
// 0x0000 - reset state
|
||||
// 0x0001 - 2BL can be downloaded
|
||||
// 0x0002 - 3BL can be downloaded
|
||||
// 0x0003 - 3BL has been started and is ready to proceed with handshake.
|
||||
// 0x8000 - (or'ed) Error. The remaining bits might contain a more details.
|
||||
//
|
||||
typedef enum _HUPRE_BOOT_STATUS
|
||||
{
|
||||
HUPRE_BOOT_STATUS_RESET = 0, // Set by HW
|
||||
HUPRE_BOOT_STATUS_1BL_CORE_UP,
|
||||
HUPRE_BOOT_STATUS_1BL_READY_FOR_2BL = 0x00010000,
|
||||
HUPRE_BOOT_STATUS_1BL_PCI_UP,
|
||||
HUPRE_BOOT_STATUS_1BL_CACHE_CLEANED,
|
||||
HUPRE_BOOT_STATUS_1BL_SEEN_2BL,
|
||||
HUPRE_BOOT_STATUS_1BL_DONE,
|
||||
HUPRE_BOOT_STATUS_2BL_STARTED,
|
||||
HUPRE_BOOT_STATUS_2BL_CACHE_UP,
|
||||
HUPRE_BOOT_STATUS_2BL_DDR_UP,
|
||||
HUPRE_BOOT_STATUS_2BL_READY_FOR_3BL = 0x00020000,
|
||||
HUPRE_BOOT_STATUS_2BL_MSI_MAPPED,
|
||||
HUPRE_BOOT_STATUS_2BL_MSI_SENT,
|
||||
HUPRE_BOOT_STATUS_2BL_SEEN_3BL,
|
||||
HUPRE_BOOT_STATUS_2BL_FIREWALLS_SET,
|
||||
HUPRE_BOOT_STATUS_2BL_DONE,
|
||||
HUPRE_BOOT_STATUS_3BL_STARTED = 0x00030000,
|
||||
HUPRE_BOOT_STATUS_3BL_TOPOLOGY_DONE,
|
||||
HUPRE_BOOT_STATUS_3BL_INTC_LINES_ENABLED,
|
||||
HUPRE_BOOT_STATUS_3BL_MSGPOOL_DONE,
|
||||
HUPRE_BOOT_STATUS_3BL_INQUEUES_DONE,
|
||||
HUPRE_BOOT_STATUS_3BL_PCIE_CONFIG_DONE = 0x00040000,
|
||||
HUPRE_BOOT_STATUS_3BL_PCIE_HANDSHAKE_DONE,
|
||||
HUPRE_BOOT_STATUS_ERROR = 0x80000000,
|
||||
} HUPRE_BOOT_STATUS;
|
||||
|
||||
//
|
||||
// INTC specifics to use for status communication from SoC to ASIC
|
||||
//
|
||||
enum
|
||||
{
|
||||
//
|
||||
// Interrupt line to use. Same for core0/1.
|
||||
//
|
||||
HUPRE_BOOT_INTC_LINE = 0,
|
||||
|
||||
//
|
||||
// Bits to use for signal readyness of various boot images.
|
||||
//
|
||||
HUPRE_BOOT_INTC_BIT_2BL = 0,
|
||||
HUPRE_BOOT_INTC_BIT_3BL = 1,
|
||||
};
|
||||
|
||||
|
|
@ -1,254 +0,0 @@
|
|||
//-----------------------------------------------------------------------------
|
||||
// File: ddc_params.h
|
||||
// Author : Matthew Pumar<matpumar@microsoft.com>
|
||||
// Generated on: 2016-06-27 12:44:57.886442
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description : AUTOGENERATED HEADER by ddc_timing.py DO NOT MODIFY
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// Copyright (c) 2015 by Microsoft.
|
||||
// This model is the confidential and proprietary property of Microsoft and the
|
||||
// possession or use of this file requires a written license from Microsoft.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
#ifndef _DDC_PARAMS_H_
|
||||
#define _DDC_PARAMS_H_
|
||||
|
||||
#define DDC_MIN 0
|
||||
#define DDC_TYP 1
|
||||
#define DDC_MAX 2
|
||||
#define DDC_REG 3
|
||||
#define DDC_PROG 4
|
||||
#define DDC_MICRON 5
|
||||
#define DDC_RAND 6
|
||||
|
||||
typedef struct{
|
||||
uint32_t dqsck[5];
|
||||
uint32_t ppd[5];
|
||||
uint32_t rrd[5];
|
||||
uint32_t zqcs[5];
|
||||
uint32_t rank[5];
|
||||
uint32_t rfcab[5];
|
||||
uint32_t refi[5];
|
||||
uint32_t zqcl[5];
|
||||
uint32_t rtp[5];
|
||||
uint32_t dqsq[5];
|
||||
uint32_t dqss[5];
|
||||
uint32_t rfcpb[5];
|
||||
uint32_t rpab[5];
|
||||
uint32_t rcpb[5];
|
||||
uint32_t xpd[5];
|
||||
uint32_t rpst[5];
|
||||
uint32_t rcd[5];
|
||||
uint32_t xsr[5];
|
||||
uint32_t zqreset[5];
|
||||
uint32_t cke[5];
|
||||
uint32_t wtr[5];
|
||||
uint32_t wpre[5];
|
||||
uint32_t bl[5];
|
||||
uint32_t wl[5];
|
||||
uint32_t faw[5];
|
||||
uint32_t zqinit[5];
|
||||
uint32_t rl[5];
|
||||
uint32_t wr[5];
|
||||
uint32_t rcab[5];
|
||||
uint32_t rlat[5];
|
||||
uint32_t rppb[5];
|
||||
uint32_t sr[5];
|
||||
uint32_t mrri[5];
|
||||
uint32_t mrw[5];
|
||||
uint32_t mrr[5];
|
||||
uint32_t mrd[5];
|
||||
uint32_t ccd[5];
|
||||
uint32_t ras[5];
|
||||
} lp3_ddc_params;
|
||||
|
||||
typedef struct{
|
||||
uint32_t dqsck[6];
|
||||
uint32_t ppd[6];
|
||||
uint32_t rrd[6];
|
||||
uint32_t dqs2dq[6];
|
||||
uint32_t rank[6];
|
||||
uint32_t rfcab[6];
|
||||
uint32_t refi[6];
|
||||
uint32_t rtw[6];
|
||||
uint32_t rtp[6];
|
||||
uint32_t dqss[6];
|
||||
uint32_t rfcpb[6];
|
||||
uint32_t rpab[6];
|
||||
uint32_t zqlatch[6];
|
||||
uint32_t rcpb[6];
|
||||
uint32_t xpd[6];
|
||||
uint32_t ckelpd[6];
|
||||
uint32_t rpst[6];
|
||||
uint32_t rcd[6];
|
||||
uint32_t xsr[6];
|
||||
uint32_t ccdmw[6];
|
||||
uint32_t escke[6];
|
||||
uint32_t zqreset[6];
|
||||
uint32_t cke[6];
|
||||
uint32_t wtr[6];
|
||||
uint32_t rtrrd[6];
|
||||
uint32_t wpre[6];
|
||||
uint32_t bl[6];
|
||||
uint32_t mrwckel[6];
|
||||
uint32_t wl[6];
|
||||
uint32_t faw[6];
|
||||
uint32_t cmdcke[6];
|
||||
uint32_t rl[6];
|
||||
uint32_t wr[6];
|
||||
uint32_t ckesr[6];
|
||||
uint32_t zqinit[6];
|
||||
uint32_t rcab[6];
|
||||
uint32_t rlat[6];
|
||||
uint32_t rppb[6];
|
||||
uint32_t wrwtr[6];
|
||||
uint32_t sr[6];
|
||||
uint32_t mrri[6];
|
||||
uint32_t mrw[6];
|
||||
uint32_t odtlon[6];
|
||||
uint32_t odton[6];
|
||||
uint32_t mrr[6];
|
||||
uint32_t mrd[6];
|
||||
uint32_t ccd[6];
|
||||
uint32_t ras[6];
|
||||
} lp4_ddc_params;
|
||||
|
||||
typedef enum ddc_c2py_mapping{
|
||||
LP3_DQSCK = 21,
|
||||
LP3_PPD = 2,
|
||||
LP3_RRD = 8,
|
||||
LP3_ZQCS = 38,
|
||||
LP3_RANK = 34,
|
||||
LP3_RFCAB = 14,
|
||||
LP3_REFI = 35,
|
||||
LP3_ZQCL = 37,
|
||||
LP3_RTP = 11,
|
||||
LP3_DQSQ = 22,
|
||||
LP3_DQSS = 23,
|
||||
LP3_RFCPB = 15,
|
||||
LP3_RPAB = 5,
|
||||
LP3_RCPB = 4,
|
||||
LP3_XPD = 19,
|
||||
LP3_RPST = 28,
|
||||
LP3_RCD = 7,
|
||||
LP3_XSR = 20,
|
||||
LP3_ZQRESET = 39,
|
||||
LP3_CKE = 17,
|
||||
LP3_WTR = 16,
|
||||
LP3_WPRE = 27,
|
||||
LP3_BL = 33,
|
||||
LP3_WL = 24,
|
||||
LP3_FAW = 10,
|
||||
LP3_ZQINIT = 36,
|
||||
LP3_RL = 25,
|
||||
LP3_WR = 13,
|
||||
LP3_RCAB = 3,
|
||||
LP3_RLAT = 26,
|
||||
LP3_RPPB = 6,
|
||||
LP3_SR = 18,
|
||||
LP3_MRRI = 32,
|
||||
LP3_MRW = 29,
|
||||
LP3_MRR = 31,
|
||||
LP3_MRD = 30,
|
||||
LP3_CCD = 12,
|
||||
LP3_RAS = 9,
|
||||
LP4_DQSCK = 61,
|
||||
LP4_PPD = 48,
|
||||
LP4_RRD = 43,
|
||||
LP4_DQS2DQ = 63,
|
||||
LP4_RANK = 82,
|
||||
LP4_RFCAB = 52,
|
||||
LP4_REFI = 78,
|
||||
LP4_RTW = 84,
|
||||
LP4_RTP = 50,
|
||||
LP4_DQSS = 62,
|
||||
LP4_RFCPB = 53,
|
||||
LP4_RPAB = 46,
|
||||
LP4_ZQLATCH = 80,
|
||||
LP4_RCPB = 42,
|
||||
LP4_XPD = 59,
|
||||
LP4_CKELPD = 75,
|
||||
LP4_RPST = 68,
|
||||
LP4_RCD = 44,
|
||||
LP4_XSR = 60,
|
||||
LP4_CCDMW = 55,
|
||||
LP4_ESCKE = 77,
|
||||
LP4_ZQRESET = 81,
|
||||
LP4_CKE = 57,
|
||||
LP4_WTR = 56,
|
||||
LP4_RTRRD = 85,
|
||||
LP4_WPRE = 67,
|
||||
LP4_BL = 83,
|
||||
LP4_MRWCKEL = 73,
|
||||
LP4_WL = 64,
|
||||
LP4_FAW = 49,
|
||||
LP4_CMDCKE = 76,
|
||||
LP4_RL = 65,
|
||||
LP4_WR = 51,
|
||||
LP4_CKESR = 74,
|
||||
LP4_ZQINIT = 79,
|
||||
LP4_RCAB = 41,
|
||||
LP4_RLAT = 66,
|
||||
LP4_RPPB = 47,
|
||||
LP4_WRWTR = 86,
|
||||
LP4_SR = 58,
|
||||
LP4_MRRI = 72,
|
||||
LP4_MRW = 69,
|
||||
LP4_ODTLON = 87,
|
||||
LP4_ODTON = 88,
|
||||
LP4_MRR = 71,
|
||||
LP4_MRD = 70,
|
||||
LP4_CCD = 54,
|
||||
LP4_RAS = 45,
|
||||
LP4_DQSCK_NS = 110,
|
||||
LP4_PPD_NS = 97,
|
||||
LP4_RRD_NS = 92,
|
||||
LP4_DQS2DQ_NS = 112,
|
||||
LP4_RANK_NS = 131,
|
||||
LP4_RFCAB_NS = 101,
|
||||
LP4_REFI_NS = 127,
|
||||
LP4_RTW_NS = 133,
|
||||
LP4_RTP_NS = 99,
|
||||
LP4_DQSS_NS = 111,
|
||||
LP4_RFCPB_NS = 102,
|
||||
LP4_RPAB_NS = 95,
|
||||
LP4_ZQLATCH_NS = 129,
|
||||
LP4_RCPB_NS = 91,
|
||||
LP4_XPD_NS = 108,
|
||||
LP4_CKELPD_NS = 124,
|
||||
LP4_RPST_NS = 117,
|
||||
LP4_RCD_NS = 93,
|
||||
LP4_XSR_NS = 109,
|
||||
LP4_CCDMW_NS = 104,
|
||||
LP4_ESCKE_NS = 126,
|
||||
LP4_ZQRESET_NS = 130,
|
||||
LP4_CKE_NS = 106,
|
||||
LP4_WTR_NS = 105,
|
||||
LP4_RTRRD_NS = 134,
|
||||
LP4_WPRE_NS = 116,
|
||||
LP4_BL_NS = 132,
|
||||
LP4_MRWCKEL_NS = 122,
|
||||
LP4_WL_NS = 113,
|
||||
LP4_FAW_NS = 98,
|
||||
LP4_CMDCKE_NS = 125,
|
||||
LP4_RL_NS = 114,
|
||||
LP4_WR_NS = 100,
|
||||
LP4_CKESR_NS = 123,
|
||||
LP4_ZQINIT_NS = 128,
|
||||
LP4_RCAB_NS = 90,
|
||||
LP4_RLAT_NS = 115,
|
||||
LP4_RPPB_NS = 96,
|
||||
LP4_WRWTR_NS = 135,
|
||||
LP4_SR_NS = 107,
|
||||
LP4_MRRI_NS = 121,
|
||||
LP4_MRW_NS = 118,
|
||||
LP4_ODTLON_NS = 136,
|
||||
LP4_ODTON_NS = 137,
|
||||
LP4_MRR_NS = 120,
|
||||
LP4_MRD_NS = 119,
|
||||
LP4_CCD_NS = 103,
|
||||
LP4_RAS_NS = 94
|
||||
} ddc_c2py_map;
|
||||
|
||||
#endif
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| init_helper.h
|
||||
|
|
||||
| helper functions definition.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INIT_HELPER_H__
|
||||
#define __INIT_HELPER_H__
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "init_helper_common.h"
|
||||
|
||||
#define PCIE_RESET_RELEASE_ADDR (0x04080090)
|
||||
#define PCIE_RESET_RELEASE_DATA (0x00000003)
|
||||
#define HUP_CN_MISC_INTC_P0_0_DATA (0x04000000)
|
||||
#define HUP_CN_MISC_INTC_P0_0_CLEAR (0x04000008)
|
||||
#define HUP_CN_MISC_INTC_P1_0_SET (0x04000084)
|
||||
#define HUP_CN_MISC_INTC_P1_0_CLEAR (0x04000088)
|
||||
#define HUP_CN_MISC_INTC_SCRATCH_REG0 (0x04005000)
|
||||
#define HUP_CN_MISC_INTC_SCRATCH_REG1 (0x04005010)
|
||||
#define HUP_CN_MISC_POR_BITS4CONTORLCORE (0x04080800)
|
||||
|
||||
#define DRAMC_READY (0x00000002)
|
||||
|
||||
//
|
||||
// C-portable version of extern "C"
|
||||
//
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN_C extern "C"
|
||||
#else
|
||||
#define EXTERN_C extern
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifndef MC_INIT_BFTEST
|
||||
// Bifrost compatibility typedefs and memory access functions
|
||||
typedef uint8_t UINT8, *PUINT8;
|
||||
typedef uint32_t UINT32, *PUINT32;
|
||||
|
||||
static inline UINT32 hw_read32(volatile UINT32* addr)
|
||||
{
|
||||
return *addr;
|
||||
}
|
||||
|
||||
static inline void hw_write32(volatile UINT32* addr, UINT32 data)
|
||||
{
|
||||
*addr = data;
|
||||
}
|
||||
|
||||
#endif //MC_INIT_BFTEST
|
||||
|
||||
typedef volatile unsigned int r32;
|
||||
typedef volatile unsigned long long r64;
|
||||
typedef volatile unsigned short r16;
|
||||
typedef volatile unsigned char r8;
|
||||
typedef unsigned long long u64;
|
||||
typedef unsigned int u32;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned char u8;
|
||||
typedef int s32;
|
||||
typedef short s16;
|
||||
typedef char s8;
|
||||
|
||||
typedef enum{
|
||||
PLAT_CHIP = 0,
|
||||
PLAT_MVP = 1,
|
||||
PLAT_PAL = 2,
|
||||
PLAT_RPP = 3,
|
||||
PLAT_ISS = 4,
|
||||
PLAT_SIM = 5,
|
||||
PLAT_VEL = 6,
|
||||
PLAT_ZEBU = 7,
|
||||
}PLATFORM_TYPE;
|
||||
|
||||
typedef enum{
|
||||
OPT_MASK_NO_DRAMC_RESET = 0x00000001,
|
||||
OPT_MASK_NO_DRAMC_INIT = 0x00000002,
|
||||
OPT_MASK_DRAMC_INIT_FOR_BASRAM_MODE = 0x00000004,
|
||||
OPT_MASK_SIM_SILICON_MODE = 0x00000008,
|
||||
OPT_MASK_DDR_MODE = 0x00000030,
|
||||
OPT_MASK_FREQUENCY = 0x00000F00,
|
||||
OPT_MASK_UPCTL = 0x0000F000,
|
||||
OPT_MASK_SCHEDULER = 0x000F0000,
|
||||
OPT_MASK_PHY = 0x3FF00000,
|
||||
OPT_MASK_PHY_MR3 = 0x00C00000,
|
||||
OPT_MASK_PHY_ZQ0PR = 0x03000000,
|
||||
OPT_MASK_PHY_ZQ1PR = 0x0C000000,
|
||||
OPT_MASK_PHY_PIR = 0x10000000,
|
||||
OPT_MASK_PHY_DTCR = 0x20000000,
|
||||
}DRAMC_INIT_OPTION_MASK;
|
||||
|
||||
typedef enum{
|
||||
OPT_MASK_LSB_NO_DRAMC_RESET = 0,
|
||||
OPT_MASK_LSB_NO_DRAMC_INIT = 1,
|
||||
OPT_MASK_LSB_DRAMC_INIT_FOR_BASRAM_MODE = 2,
|
||||
OPT_MASK_LSB_SIM_SILICON_MODE = 3,
|
||||
OPT_MASK_LSB_DDR_MODE = 4,
|
||||
OPT_MASK_LSB_FREQUENCY = 8,
|
||||
OPT_MASK_LSB_UPCTL = 12,
|
||||
OPT_MASK_LSB_SCHEDULER = 16,
|
||||
OPT_MASK_LSB_PHY = 20,
|
||||
OPT_MASK_LSB_PHY_MR3 = 22,
|
||||
OPT_MASK_LSB_PHY_ZQ0PR = 24,
|
||||
OPT_MASK_LSB_PHY_ZQ1PR = 26,
|
||||
OPT_MASK_LSB_PHY_PIR = 28,
|
||||
OPT_MASK_LSB_PHY_DTCR = 29,
|
||||
}DRAMC_INIT_OPTION_MASK_LSB;
|
||||
|
||||
typedef enum{
|
||||
LPDDR_DEFAULT = 0,
|
||||
LPDDR_2 = 2,
|
||||
LPDDR_3 = 3,
|
||||
}DRAMC_INIT_OPTION_DDR_MODE;
|
||||
|
||||
typedef enum{
|
||||
CHANNEL_BIT9_DEFAULT = 1,
|
||||
CHANNEL_BIT10 = 2,
|
||||
CHANNEL_BIT11 = 4,
|
||||
CHANNEL_BIT26 = 8,
|
||||
}POR_INIT_DRAMC_INTERLEAVE_MODE;
|
||||
|
||||
typedef enum{
|
||||
LPDDR_SIZE_DEFAULT = 0,
|
||||
LPDDR_SIZE_4Gb = 4,
|
||||
LPDDR_SIZE_8Gb = 8,
|
||||
}DRAMC_INIT_OPTION_DDR_SIZE;
|
||||
|
||||
typedef enum{
|
||||
LPDDR_RANKS_DEFAULT = 0,
|
||||
LPDDR_RANKS_SINGLE = 1,
|
||||
LPDDR_RANKS_DOUBLE = 2,
|
||||
}DRAMC_INIT_OPTION_DDR_RANKS;
|
||||
|
||||
typedef enum{
|
||||
FREQ_DEFAULT = 1600,
|
||||
FREQ_400MHZ = 400,
|
||||
FREQ_800MHZ = 800,
|
||||
FREQ_1066MHZ = 1066,
|
||||
FREQ_1333MHZ = 1333,
|
||||
}DRAMC_INIT_OPTION_FREQUENCY;
|
||||
|
||||
typedef enum{
|
||||
UPCTL_MASK_TREFI = 0x00000001,
|
||||
}DRAMC_INIT_OPTION_UPCTL_MASK;
|
||||
|
||||
|
||||
typedef enum{
|
||||
DRAMC_INIT_BEGIN = 0x00050000,
|
||||
DRAMC_INIT_POR = 0x00051000,
|
||||
DRAMC_INIT_SCHEDULER = 0x00052000,
|
||||
DRAMC_INIT_FREQUENCY = 0x00053000,
|
||||
DRAMC_INIT_PHY_STARTED = 0x00054000,
|
||||
DRAMC_INIT_PHY_BEFORE_TRAINING = 0x00054001,
|
||||
DRAMC_INIT_PHY_AFTER_TRAINING = 0x00054002,
|
||||
DRAMC_INIT_DFI = 0x00055000,
|
||||
DRAMC_INIT_POWER_UP = 0x00056000,
|
||||
DRAMC_INIT_TIMING_REGS = 0x00057000,
|
||||
DRAMC_INIT_DFI_TIMING_REGS = 0x00058000,
|
||||
DRAMC_INIT_MEMORY_STARTED = 0x00059000,
|
||||
DRAMC_INIT_MEMORY_MRW_RESET = 0x00059001,
|
||||
DRAMC_INIT_MEMORY_MRW_ZQ = 0x00059002,
|
||||
DRAMC_INIT_MEMORY_MRW_MR2 = 0x00059003,
|
||||
DRAMC_INIT_MEMORY_MRW_MR1 = 0x00059004,
|
||||
DRAMC_INIT_MEMORY_MRW_MR3 = 0x00059005,
|
||||
DRAMC_INIT_MEMORY_MRW_REF = 0x00059006,
|
||||
DRAMC_INIT_DFICTRLUPD = 0x0005A000,
|
||||
DRAMC_INIT_MOVE_STATE_CONFIG = 0x0005B000,
|
||||
DRAMC_INIT_OVERRIDE_SEQ_STARTED = 0x0005C000,
|
||||
DRAMC_INIT_OVERRIDE_SEQ_CONFIG = 0x0005C001,
|
||||
DRAMC_INIT_OVERRIDE_SEQ_MCMD = 0x0005C002,
|
||||
DRAMC_INIT_MOVE_STATE_ACCESS = 0x0005D000,
|
||||
}DRAMC_INIT_STATUS;
|
||||
|
||||
#define reg_write32(addr, val) ((*(volatile unsigned int*)(addr)) = val)
|
||||
#define reg_read32(addr, val) (val = (*(volatile unsigned int*)addr))
|
||||
|
||||
#define get_prid() xthal_get_prid()
|
||||
#define get_ccount() xthal_get_ccount()
|
||||
|
||||
static inline void delay_cycles(unsigned int cycles)
|
||||
{
|
||||
unsigned int start = get_ccount();
|
||||
while((unsigned int)(get_ccount() - start) < cycles);
|
||||
}
|
||||
|
||||
#define delay_ns(ns) delay_cycles(ns / 2)
|
||||
#define delay_us(us) delay_cycles(us * 1000 / 2)
|
||||
#define delay_ms(ms) delay_cycles(ms * 1000000 / 2)
|
||||
|
||||
static inline PLATFORM_TYPE get_platform_type()
|
||||
{
|
||||
#ifdef SIM_PLAT
|
||||
return PLAT_SIM;
|
||||
#else
|
||||
unsigned int reg_data = 0;
|
||||
reg_data = *(volatile unsigned int*)(HUP_CN_MISC_POR_BITS4CONTORLCORE);
|
||||
return (PLATFORM_TYPE)((reg_data & 0xFF000000) >> 24);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline unsigned int get_dramc_init_option(DRAMC_INIT_OPTION_MASK option_mask)
|
||||
{
|
||||
unsigned int reg_data = *(volatile unsigned int*)(HUP_CN_MISC_INTC_SCRATCH_REG1);
|
||||
unsigned int ret = 0;
|
||||
PLATFORM_TYPE plat = get_platform_type();
|
||||
switch(option_mask)
|
||||
{
|
||||
case OPT_MASK_DRAMC_INIT_FOR_BASRAM_MODE:
|
||||
ret = (reg_data & OPT_MASK_DRAMC_INIT_FOR_BASRAM_MODE) >> OPT_MASK_LSB_DRAMC_INIT_FOR_BASRAM_MODE;
|
||||
break;
|
||||
|
||||
case OPT_MASK_NO_DRAMC_INIT:
|
||||
ret = (reg_data & OPT_MASK_DRAMC_INIT_FOR_BASRAM_MODE) >> OPT_MASK_LSB_DRAMC_INIT_FOR_BASRAM_MODE;
|
||||
break;
|
||||
|
||||
case OPT_MASK_NO_DRAMC_RESET:
|
||||
ret = (reg_data & OPT_MASK_NO_DRAMC_RESET) >> OPT_MASK_LSB_NO_DRAMC_RESET;
|
||||
break;
|
||||
|
||||
case OPT_MASK_SIM_SILICON_MODE:
|
||||
ret = (reg_data & OPT_MASK_SIM_SILICON_MODE) >> OPT_MASK_LSB_SIM_SILICON_MODE;
|
||||
break;
|
||||
|
||||
case OPT_MASK_DDR_MODE:
|
||||
if((plat == PLAT_PAL) || (plat == PLAT_RPP))
|
||||
{
|
||||
ret = LPDDR_3;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = (reg_data & OPT_MASK_DDR_MODE) >> OPT_MASK_LSB_DDR_MODE;
|
||||
}
|
||||
break;
|
||||
|
||||
case OPT_MASK_FREQUENCY:
|
||||
if((plat == PLAT_PAL) || (plat == PLAT_RPP))
|
||||
{
|
||||
ret = FREQ_800MHZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = (reg_data & OPT_MASK_FREQUENCY) >> OPT_MASK_LSB_FREQUENCY;
|
||||
}
|
||||
break;
|
||||
|
||||
case OPT_MASK_UPCTL:
|
||||
ret = (reg_data & OPT_MASK_UPCTL) >> OPT_MASK_LSB_UPCTL;
|
||||
break;
|
||||
|
||||
case OPT_MASK_SCHEDULER:
|
||||
ret = (reg_data & OPT_MASK_SCHEDULER) >> OPT_MASK_LSB_SCHEDULER;
|
||||
break;
|
||||
|
||||
case OPT_MASK_PHY:
|
||||
ret = (reg_data & OPT_MASK_PHY) >> OPT_MASK_LSB_PHY;
|
||||
break;
|
||||
|
||||
case OPT_MASK_PHY_MR3:
|
||||
ret = (reg_data & OPT_MASK_PHY_MR3) >> OPT_MASK_LSB_PHY_MR3;
|
||||
break;
|
||||
|
||||
case OPT_MASK_PHY_ZQ0PR:
|
||||
ret = (reg_data & OPT_MASK_PHY_ZQ0PR) >> OPT_MASK_LSB_PHY_ZQ0PR;
|
||||
break;
|
||||
|
||||
case OPT_MASK_PHY_ZQ1PR:
|
||||
ret = (reg_data & OPT_MASK_PHY_ZQ1PR) >> OPT_MASK_LSB_PHY_ZQ1PR;
|
||||
break;
|
||||
|
||||
case OPT_MASK_PHY_PIR:
|
||||
ret = (reg_data & OPT_MASK_PHY_PIR) >> OPT_MASK_LSB_PHY_PIR;
|
||||
break;
|
||||
|
||||
case OPT_MASK_PHY_DTCR:
|
||||
ret = (reg_data & OPT_MASK_PHY_DTCR) >> OPT_MASK_LSB_PHY_DTCR;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void set_dramc_ready()
|
||||
{
|
||||
delay_us(10);
|
||||
*(unsigned int*)(HUP_CN_MISC_INTC_P1_0_SET) = 0x2;
|
||||
}
|
||||
|
||||
static inline void wait_for_dramc_ready()
|
||||
{
|
||||
unsigned int reg_data = 0;
|
||||
do
|
||||
{
|
||||
reg_data = *(volatile unsigned int*)(HUP_CN_MISC_INTC_P1_0_CLEAR);
|
||||
}while((reg_data & 0x2) == 0);
|
||||
|
||||
*(unsigned int*)(HUP_CN_MISC_INTC_P1_0_CLEAR) = 0x2;
|
||||
}
|
||||
static void inline post_status(unsigned int status )
|
||||
{
|
||||
*(unsigned int *)(HUP_CN_MISC_INTC_SCRATCH_REG0) = status;
|
||||
}
|
||||
|
||||
#endif // __INIT_HELPER_H__
|
||||
|
||||
|
|
@ -1,177 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| init_helper_common.h
|
||||
|
|
||||
| Definitions and structs that are used
|
||||
| by both Bifrost and 2BL
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2013 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INIT_HELPER_COMMON_H__
|
||||
#define __INIT_HELPER_COMMON_H__
|
||||
|
||||
#define INIT_OPTION_BASE_ADDR (0x00100200)
|
||||
#define BOOT_DIAG_BASE_ADDR (0x00100400)
|
||||
#define CACHED_BOOT_DIAG_BASE_ADDR (0x20100400)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned long long start;
|
||||
unsigned long long end;
|
||||
}BOOT_DIAG_DRAMC_INIT_TIME;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int pir;
|
||||
unsigned int dtcr;
|
||||
unsigned int mr3;
|
||||
unsigned int zq0pr;
|
||||
unsigned int zq1pr;
|
||||
unsigned int aclcdlr;
|
||||
unsigned int dtdr[2];
|
||||
unsigned int dtedr[2];
|
||||
unsigned int dx0lcdlr[2];
|
||||
unsigned int dx1lcdlr[2];
|
||||
unsigned int dx2lcdlr[2];
|
||||
unsigned int dx3lcdlr[2];
|
||||
unsigned int dx0bdlr[6];
|
||||
unsigned int dx1bdlr[6];
|
||||
unsigned int dx2bdlr[6];
|
||||
unsigned int dx3bdlr[6];
|
||||
unsigned int dx4bdlr[6];
|
||||
unsigned int dx5bdlr[6];
|
||||
unsigned int dx6bdlr[6];
|
||||
unsigned int dx7bdlr[6];
|
||||
unsigned int dx8bdlr[6];
|
||||
unsigned int dx9bdlr[6];
|
||||
}BOOT_DIAG_DRAMC_TRAINING_STAT;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int aclcdlr;
|
||||
unsigned int dx0lcdlr1;
|
||||
unsigned int dx1lcdlr1;
|
||||
unsigned int dx2lcdlr1;
|
||||
unsigned int dx3lcdlr1;
|
||||
}BOOT_DIAG_DRAMC_SHMOO_OVERRIDE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BOOT_DIAG_DRAMC_INIT_TIME init_time;
|
||||
BOOT_DIAG_DRAMC_TRAINING_STAT training_stat;
|
||||
BOOT_DIAG_DRAMC_SHMOO_OVERRIDE shmoo_override;
|
||||
}BOOT_DIAG_DRAMC;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BOOT_DIAG_DRAMC dramc;
|
||||
}BOOT_DIAG;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int NO_DRAMC_RESET :1;
|
||||
unsigned int NO_DRAMC_INIT :1;
|
||||
unsigned int DRAMC_INIT_FOR_BASRAM_MODE :1;
|
||||
unsigned int FULL_DRAMC_INIT :1;
|
||||
unsigned int DDR_MODE :2;
|
||||
unsigned int DDR_SIZE :4;
|
||||
unsigned int DDR_RANKS :2;
|
||||
unsigned int FREQUENCY_OPT :11;
|
||||
unsigned int UPCTL_OPT :1;
|
||||
unsigned int DDR_CONF :2;
|
||||
unsigned int PHY_OPT :2;
|
||||
unsigned int DRAMC_INTERLEAVE_MODE :4;
|
||||
}DRAMC_INIT_OPT_STD;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int mr3 :2;
|
||||
unsigned int zq0pr :2;
|
||||
unsigned int zq1pr :2;
|
||||
unsigned int rsvd :26;
|
||||
}DRAMC_INIT_OPT_SHMOO_DS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int dx0lcdlr1 :8;
|
||||
unsigned int dx1lcdlr1 :8;
|
||||
unsigned int dx2lcdlr1 :8;
|
||||
unsigned int dx3lcdlr1 :8;
|
||||
}DRAMC_INIT_OPT_SHMOO_WDQD;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int dx0lcdlr1 :8;
|
||||
unsigned int dx1lcdlr1 :8;
|
||||
unsigned int dx2lcdlr1 :8;
|
||||
unsigned int dx3lcdlr1 :8;
|
||||
}DRAMC_INIT_OPT_SHMOO_RDQSD;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int dx0lcdlr1 :8;
|
||||
unsigned int dx1lcdlr1 :8;
|
||||
unsigned int dx2lcdlr1 :8;
|
||||
unsigned int dx3lcdlr1 :8;
|
||||
}DRAMC_INIT_OPT_SHMOO_RDQSND;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int acd :8;
|
||||
unsigned int rsvd :24;
|
||||
}DRAMC_INIT_OPT_SHMOO_AC;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int ds :1;
|
||||
unsigned int wdqd :1;
|
||||
unsigned int rdqsd :1;
|
||||
unsigned int rdqsnd :1;
|
||||
unsigned int ac :1;
|
||||
unsigned int rsvd :27;
|
||||
}DRAMC_INIT_OPT_SHMOO_ENABLE_MASK;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DRAMC_INIT_OPT_SHMOO_ENABLE_MASK enable;
|
||||
DRAMC_INIT_OPT_SHMOO_DS ds;
|
||||
DRAMC_INIT_OPT_SHMOO_WDQD wdqd;
|
||||
DRAMC_INIT_OPT_SHMOO_RDQSD rdqsd;
|
||||
DRAMC_INIT_OPT_SHMOO_RDQSND rdqsnd;
|
||||
DRAMC_INIT_OPT_SHMOO_AC ac;
|
||||
}DRAMC_INIT_OPT_SHMOO;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DRAMC_INIT_OPT_STD std;
|
||||
DRAMC_INIT_OPT_SHMOO shmoo;
|
||||
}DRAMC_INIT_OPT;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int skip_dram_heap_init;
|
||||
unsigned int suite_rand_seed;
|
||||
unsigned int verbosity;
|
||||
unsigned int runtime;
|
||||
unsigned int jtm_interval;
|
||||
unsigned int jtm_slope;
|
||||
unsigned int jtm_offset;
|
||||
unsigned int bock_test;
|
||||
}BF_INIT_OPT;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DRAMC_INIT_OPT dramc_init_opt;
|
||||
BF_INIT_OPT bf_init_opt;
|
||||
}INIT_OPTION;
|
||||
|
||||
#endif // __INIT_HELPER_COMMON_H__
|
||||
|
||||
|
|
@ -1,222 +0,0 @@
|
|||
lp4_ddc_params lp4_400mhz_param_db = {
|
||||
.dqsck={1,2,2,0,2,2},
|
||||
.ppd={4,4,4,0,4,4},
|
||||
.rrd={2,4,10,0,4,4},
|
||||
.dqs2dq={1,1,1,0,1,1},
|
||||
.rank={1,10,8,0,10,10},
|
||||
.rfcab={110,112,118,0,112,112},
|
||||
.refi={1561,1563,1569,0,1563,1562},
|
||||
.rtw={21,23,29,0,23,23},
|
||||
.rtp={8,8,8,0,8,8},
|
||||
.dqss={0,2,8,0,2,1},
|
||||
.rfcpb={54,56,62,0,56,56},
|
||||
.rpab={7,9,15,0,9,9},
|
||||
.zqlatch={10,12,18,0,12,12},
|
||||
.rcpb={21,25,37,0,25,24},
|
||||
.xpd={1,3,9,0,5,5},
|
||||
.ckelpd={8,10,16,0,10,10},
|
||||
.rpst={0,1,7,0,1,1},
|
||||
.rcd={6,8,14,0,8,8},
|
||||
.xsr={73,75,81,0,75,75},
|
||||
.ccdmw={30,32,38,0,32,32},
|
||||
.escke={2,2,2,0,2,3},
|
||||
.zqreset={18,20,26,0,20,20},
|
||||
.cke={1,3,9,0,3,4},
|
||||
.wtr={6,8,14,0,8,8},
|
||||
.rtrrd={35,37,43,0,37,37},
|
||||
.wpre={2,2,2,0,2,1.8},
|
||||
.bl={0,0,0,0,0,0},
|
||||
.mrwckel={8,10,16,0,10,10},
|
||||
.wl={6,6,6,0,6,6},
|
||||
.faw={14,16,22,0,16,40},
|
||||
.cmdcke={1,3,9,0,3,3},
|
||||
.rl={12,12,12,0,12,12},
|
||||
.wr={10,10,10,0,10,10},
|
||||
.ckesr={8,10,16,0,10,10},
|
||||
.zqinit={398,400,406,0,400,400},
|
||||
.rcab={24,26,32,0,26,26},
|
||||
.rlat={4,6,12,0,6,6},
|
||||
.rppb={6,8,14,0,8,8},
|
||||
.wrwtr={17,19,25,0,19,19},
|
||||
.sr={4,6,12,0,6,6},
|
||||
.mrri={8,10,16,0,10,0},
|
||||
.mrw={10,10,14,0,10,10},
|
||||
.odtlon={4,4,4,0,4,4},
|
||||
.odton={2,2,2,0,2,2},
|
||||
.mrr={2,8,10,0,8,8},
|
||||
.mrd={8,10,16,0,10,10},
|
||||
.ccd={8,8,16,0,8,8},
|
||||
.ras={15,17,23,0,17,17}
|
||||
};
|
||||
|
||||
lp4_ddc_params lp4_800mhz_param_db = {
|
||||
.dqsck={1,3,3,0,3,3},
|
||||
.ppd={4,4,4,0,4,4},
|
||||
.rrd={4,8,20,0,8,8},
|
||||
.dqs2dq={1,1,1,0,1,2},
|
||||
.rank={1,10,15,0,10,10},
|
||||
.rfcab={220,224,236,0,224,224},
|
||||
.refi={3121,3125,3137,0,3125,3124},
|
||||
.rtw={22,26,38,0,26,26},
|
||||
.rtp={8,8,8,0,8,8},
|
||||
.dqss={1,2,2,0,2,2},
|
||||
.rfcpb={108,112,124,0,112,112},
|
||||
.rpab={13,17,29,0,17,17},
|
||||
.zqlatch={20,24,36,0,24,24},
|
||||
.rcpb={40,97,72,0,97,97},
|
||||
.xpd={6,6,12,0,6,6},
|
||||
.ckelpd={6,10,22,0,10,10},
|
||||
.rpst={1,1,13,0,1,1},
|
||||
.rcd={11,15,27,0,15,15},
|
||||
.xsr={226,230,242,0,230,230},
|
||||
.ccdmw={28,32,44,0,32,32},
|
||||
.escke={2,2,2,0,2,3},
|
||||
.zqreset={36,40,52,0,40,40},
|
||||
.cke={2,6,12,0,6,6},
|
||||
.wtr={4,8,20,0,8,8},
|
||||
.rtrrd={38,42,54,0,42,42},
|
||||
.wpre={2,2,2,0,2,1.8},
|
||||
.bl={0,0,0,0,0,0},
|
||||
.mrwckel={8,12,24,0,12,12},
|
||||
.wl={8,8,8,0,8,8},
|
||||
.faw={28,32,44,0,32,40},
|
||||
.cmdcke={0,3,7,0,3,3},
|
||||
.rl={16,16,16,0,16,16},
|
||||
.wr={16,16,16,0,16,16},
|
||||
.ckesr={8,12,24,0,12,12},
|
||||
.zqinit={796,800,812,0,800,800},
|
||||
.rcab={43,51,75,0,51,51},
|
||||
.rlat={2,6,18,0,6,6},
|
||||
.rppb={11,15,27,0,15,15},
|
||||
.wrwtr={18,22,34,0,22,22},
|
||||
.sr={8,12,24,0,12,12},
|
||||
.mrri={14,18,30,0,18,18},
|
||||
.mrw={4,8,16,0,8,10},
|
||||
.odtlon={0,0,0,0,0,0},
|
||||
.odton={1,1,1,0,1,2},
|
||||
.mrr={3,14,28,0,14,7},
|
||||
.mrd={8,12,16,0,12,12},
|
||||
.ccd={8,8,16,0,8,8},
|
||||
.ras={30,34,46,0,34,34}
|
||||
};
|
||||
|
||||
lp4_ddc_params lp4_1066mhz_param_db = {
|
||||
.dqsck={2,4,4,0,4,4},
|
||||
.ppd={4,4,4,0,4,4},
|
||||
.rrd={6,11,27,0,11,11},
|
||||
.dqs2dq={1,1,1,0,1,2},
|
||||
.rank={2,10,20,0,10,10},
|
||||
.rfcab={294,299,315,0,299,299},
|
||||
.refi={4159,4165,4181,0,4165,4163},
|
||||
.rtw={22,27,43,0,27,27},
|
||||
.rtp={8,8,8,0,8,8},
|
||||
.dqss={1,2,3,0,2,2},
|
||||
.rfcpb={144,150,166,0,150,150},
|
||||
.rpab={18,23,39,0,23,23},
|
||||
.zqlatch={27,32,48,0,32,32},
|
||||
.rcpb={54,97,96,0,97,97},
|
||||
.xpd={8,8,16,0,8,8},
|
||||
.ckelpd={5,10,26,0,10,10},
|
||||
.rpst={1,1,17,0,1,1},
|
||||
.rcd={14,20,36,0,20,20},
|
||||
.xsr={302,307,323,0,307,307},
|
||||
.ccdmw={27,32,48,0,32,32},
|
||||
.escke={2,2,2,0,2,3},
|
||||
.zqreset={48,54,70,0,54,54},
|
||||
.cke={3,8,16,0,8,8},
|
||||
.wtr={6,11,27,0,11,11},
|
||||
.rtrrd={39,45,61,0,45,45},
|
||||
.wpre={2,2,2,0,2,2},
|
||||
.bl={0,0,0,0,0,0},
|
||||
.mrwckel={10,15,31,0,15,15},
|
||||
.wl={10,10,10,0,10,10},
|
||||
.faw={38,43,59,0,43,43},
|
||||
.cmdcke={0,3,10,0,3,3},
|
||||
.rl={22,22,22,0,22,22},
|
||||
.wr={20,20,20,0,20,20},
|
||||
.ckesr={11,16,32,0,16,16},
|
||||
.zqinit={1061,1067,1083,0,1067,1067},
|
||||
.rcab={57,68,100,0,68,68},
|
||||
.rlat={1,6,22,0,6,6},
|
||||
.rppb={14,20,36,0,20,20},
|
||||
.wrwtr={18,24,40,0,24,24},
|
||||
.sr={11,16,32,0,16,16},
|
||||
.mrri={17,23,39,0,23,23},
|
||||
.mrw={6,11,21,0,11,11},
|
||||
.odtlon={4,4,4,0,4,4},
|
||||
.odton={1,1,1,0,1,2},
|
||||
.mrr={4,14,28,0,14,9},
|
||||
.mrd={10,15,21,0,15,15},
|
||||
.ccd={8,8,16,0,8,8},
|
||||
.ras={40,45,61,0,45,45}
|
||||
};
|
||||
|
||||
lp4_ddc_params lp4_1333mhz_param_db = {
|
||||
.dqsck={2,5,5,0,5,5},
|
||||
.ppd={4,4,4,0,4,4},
|
||||
.rrd={7,14,34,0,14,14},
|
||||
.dqs2dq={2,2,2,0,2,1},
|
||||
.rank={2,10,25,0,10,10},
|
||||
.rfcab={367,374,394,0,374,374},
|
||||
.refi={5202,5208,5228,0,5208,5206},
|
||||
.rtw={22,29,49,0,29,29},
|
||||
.rtp={10,10,10,0,10,10},
|
||||
.dqss={0,2,22,0,2,2},
|
||||
.rfcpb={180,187,207,0,187,187},
|
||||
.rpab={22,28,48,0,28,28},
|
||||
.zqlatch={34,40,60,0,40,40},
|
||||
.rcpb={68,80,120,0,80,80},
|
||||
.xpd={4,10,30,0,10,10},
|
||||
.ckelpd={4,10,30,0,10,10},
|
||||
.rpst={0,1,21,0,1,1},
|
||||
.rcd={18,24,44,0,24,24},
|
||||
.xsr={244,250,270,0,250,250},
|
||||
.ccdmw={26,32,52,0,32,32},
|
||||
.escke={2,2,2,0,2,3},
|
||||
.zqreset={60,67,87,0,67,67},
|
||||
.cke={4,10,30,0,10,10},
|
||||
.wtr={7,14,34,0,14,14},
|
||||
.rtrrd={41,48,68,0,48,48},
|
||||
.wpre={2,2,2,0,2,3},
|
||||
.bl={0,0,0,0,0,0},
|
||||
.mrwckel={12,19,39,0,19,19},
|
||||
.wl={12,12,12,0,12,12},
|
||||
.faw={47,54,74,0,54,54},
|
||||
.cmdcke={0,3,23,0,3,3},
|
||||
.rl={28,28,28,0,28,28},
|
||||
.wr={24,24,24,0,24,24},
|
||||
.ckesr={14,20,40,0,20,20},
|
||||
.zqinit={1327,1334,1354,0,1334,1334},
|
||||
.rcab={78,84,104,0,84,84},
|
||||
.rlat={0,6,26,0,6,6},
|
||||
.rppb={18,24,44,0,24,24},
|
||||
.wrwtr={19,26,46,0,26,26},
|
||||
.sr={14,20,40,0,20,20},
|
||||
.mrri={26,32,52,0,32,0},
|
||||
.mrw={14,14,40,0,14,14},
|
||||
.odtlon={4,4,4,0,4,4},
|
||||
.odton={2,2,2,0,2,2},
|
||||
.mrr={4,12,30,0,12,12},
|
||||
.mrd={12,19,39,0,19,19},
|
||||
.ccd={8,8,16,0,8,8},
|
||||
.ras={50,56,76,0,56,56}
|
||||
};
|
||||
|
||||
void update_ddc_params_frequency(int frequency){
|
||||
|
||||
if(frequency == 400){
|
||||
lp4_param_db = lp4_400mhz_param_db;
|
||||
}
|
||||
|
||||
if(frequency == 800){
|
||||
lp4_param_db = lp4_800mhz_param_db;
|
||||
}
|
||||
|
||||
if(frequency == 1066){
|
||||
lp4_param_db = lp4_1066mhz_param_db;
|
||||
}
|
||||
|
||||
if(frequency == 1333){
|
||||
lp4_param_db = lp4_1333mhz_param_db;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
#ifndef __KAHALU_GLOBAL_DEFINES_HEADER_INC
|
||||
#define __KAHALU_GLOBAL_DEFINES_HEADER_INC
|
||||
|
||||
#ifdef MCU_IP_VERIF
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <svdpi.h>
|
||||
#include <stddef.h>
|
||||
#include <unistd.h>
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
//Global variables
|
||||
typedef enum {
|
||||
REGACC_RD = 0,
|
||||
REGACC_WR = 1
|
||||
} REGACC_TYPE;
|
||||
|
||||
#endif //__KAHALU_GLOBAL_DEFINES_HEADER_INC
|
||||
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
#ifndef __KAHALU_SIM_INIT_HEADER_INC
|
||||
#define __KAHALU_SIM_INIT_HEADER_INC
|
||||
|
||||
|
||||
#include <kahalu_utils.h>
|
||||
|
||||
|
||||
//DPI imports
|
||||
//extern void bfm_read32(uint32_t* addr, uint32_t* data);
|
||||
//extern void bfm_write32(uint32_t* addr, uint32_t data);
|
||||
//extern void simulation_tb_wait(uint32_t cycles, char * clock);
|
||||
//extern void simulation_wait_ns(uint32_t ns);
|
||||
|
||||
// MTC extern functions from mtc_train.c
|
||||
extern void program_non_default_regs_for_mtc_write_training_init();
|
||||
|
||||
// DPI export
|
||||
//extern int simulation_init_seq (const int dram_mode, const int active_ranks, const int dram_cfg, const int autoref_int, const int training_test_num, const int dfi_training_en, const int ddc_param_mode, const int wr_dbi, const int rd_dbi, const int use_real_init_seq, const int dram_frequency, int delay_model, const int enable_pmb, const int phy_init_train, const int dump_phy_regs);
|
||||
extern int release_global_hold_seq(const int mc, const int cycles, char* clk);
|
||||
|
||||
|
||||
|
||||
//DDC timing routines
|
||||
void update_ddc_fields(const int mc, const int dram_frequency);
|
||||
void update_all_ddc_param(const int mc, int val, const int dram_frequency);
|
||||
#ifdef MCU_IP_VERIF
|
||||
void update_ddc_params_from_yml();
|
||||
#endif //MCU_IP_VERIF
|
||||
void update_ddc_params_frequency(int frequency);
|
||||
|
||||
//Init routines
|
||||
void write_mr_reg(const int mc, uint32_t mr_addr, uint32_t rank, uint32_t data);
|
||||
void pmb_enable_function(const int mc);
|
||||
void configure_dram(const int mc, int config_num);
|
||||
void mc_setup(const int mc, const int mode, const int active_ranks, const int dram_cfg);
|
||||
void init_dram(const int mc, const int mode, const int active_ranks, const int dram_cfg);
|
||||
void wait_for_dfi_init(const int mc);
|
||||
uint32_t read_mr_reg(const int mc, uint32_t mr_addr, uint32_t rank);
|
||||
void send_mr_commands(const int mc, const int dram_mode, const int active_ranks, const int wr_dbi_dis, const int rd_dbi_dis, const int ddc_mode, const int frequency);
|
||||
int mcu_reset_init_seq
|
||||
(
|
||||
const int mc,
|
||||
const int dram_mode,
|
||||
const int active_ranks,
|
||||
const int dram_cfg,
|
||||
const int autoref_int,
|
||||
const int ddc_param_mode,
|
||||
const int wr_dbi_dis,
|
||||
const int rd_dbi_dis,
|
||||
const int dram_frequency,
|
||||
const int enable_pmb,
|
||||
const int skip_part_phy_init
|
||||
);
|
||||
|
||||
void perf_regs_init(const int mc);
|
||||
#ifdef MCU_IP_VERIF
|
||||
extern int simulation_init_seq
|
||||
#else
|
||||
EXTERN_C int simulation_init_seq
|
||||
#endif //MCU_IP_VERIF
|
||||
(
|
||||
const int mc,
|
||||
const int dram_mode,
|
||||
const int active_ranks,
|
||||
const int dram_cfg,
|
||||
const int autoref_int,
|
||||
const int training_test_num,
|
||||
const int phy_training_mode,
|
||||
const int ddc_param_mode,
|
||||
const int wr_dbi_dis,
|
||||
const int rd_dbi_dis,
|
||||
const int use_real_init_seq,
|
||||
const int dram_frequency,
|
||||
const int delay_model,
|
||||
const int enable_pmb,
|
||||
const int phy_init_train,
|
||||
const int dump_phy_regs,
|
||||
const int seed,
|
||||
const int skip_mcu_init,
|
||||
const int pmg_setup_en,
|
||||
const int training_en,
|
||||
const int skip_part_phy_init,
|
||||
const int mov_window_size,
|
||||
const int mtc_adjust_step,
|
||||
const int mtc_use_read_methodB,
|
||||
const int set_bdlr_val
|
||||
);
|
||||
|
||||
|
||||
void do_yml_reg_writes(char *fname);
|
||||
void set_autorefresh(const int mc, int interval, int dram_mode, const int dram_frequency);
|
||||
void program_ddc_phy_params(const int mc, const int rd_dbi_dis, const int dram_frequency);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,168 +0,0 @@
|
|||
#ifndef __KAHALU_UTILS_HEADER_INC
|
||||
#define __KAHALU_UTILS_HEADER_INC
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#include <unistd.h>
|
||||
#include <errno.h>
|
||||
|
||||
#ifdef MCU_IP_VERIF
|
||||
#include <svdpi.h>
|
||||
#include <bist.h>
|
||||
#include "conf_defs.h"
|
||||
#define hw_status(...) printf (__VA_ARGS__)
|
||||
#else
|
||||
#ifdef REAL_MCPHY
|
||||
#define CONF_HAS___PHY_RTL
|
||||
#endif //REAL_MCPHY
|
||||
#include "init_helper.h"
|
||||
#ifndef MC_INIT_BFTEST
|
||||
#define hw_status(...)
|
||||
#else
|
||||
#include "bifrost.h"
|
||||
#endif
|
||||
#include "hup_chip.h"
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
|
||||
#include <ddc_params.h>
|
||||
#include <mcu_regs.h>
|
||||
#include <kahalu_global_defines.h>
|
||||
|
||||
|
||||
//Reg Model
|
||||
static PTR_Mcu_regs chip_regs = (PTR_Mcu_regs)(MCU_REGS_MCP_REGS_ADDRESS);
|
||||
extern uint32_t* g_last_regacc_addr;
|
||||
extern REGACC_TYPE g_last_regacc_type;
|
||||
extern int dram_type;
|
||||
extern lp4_ddc_params lp4_param_db;
|
||||
extern lp3_ddc_params lp3_param_db;
|
||||
|
||||
extern void simulation_tb_wait(uint32_t cycles, const char * clock);
|
||||
#ifdef MCU_IP_VERIF
|
||||
//DPI imports
|
||||
extern void bfm_read32(uint32_t* addr, uint32_t* data);
|
||||
extern void bfm_write32(uint32_t* addr, uint32_t data);
|
||||
extern void update_ddc_params_from_yml();
|
||||
#define hw_sleep(ns) simulation_wait_ns(ns);
|
||||
extern void simulation_wait_ns(uint32_t t_ns);
|
||||
extern void print_sim_time();
|
||||
extern char* get_sim_time();
|
||||
extern int sv_get_wire_delay_reg_wr(uint32_t rank, uint32_t slice);
|
||||
extern int sv_get_wire_delay_reg_rd(uint32_t rank, uint32_t slice);
|
||||
#else
|
||||
|
||||
#ifndef MC_INIT_BFTEST
|
||||
#define hw_sleep(ns) delay_ns(ns)
|
||||
#endif
|
||||
#endif //MCU_IP_VERIF
|
||||
// DPI export
|
||||
//extern int simulation_init_seq (const int dram_mode, const int active_ranks, const int dram_cfg, const int autoref_int, const int training_test_num, const int dfi_training_en, const int ddc_param_mode, const int wr_dbi, const int rd_dbi, const int use_real_init_seq, const int dram_frequency, int delay_model, const int enable_pmb, const int phy_init_train, const int dump_phy_regs);
|
||||
//extern void release_global_hold_seq(const int cycles, char* clk);
|
||||
|
||||
|
||||
static inline void hw_phy_regacc_post_wait(uint32_t is_read)
|
||||
{
|
||||
//The SNPS LPDDR4 PHY requires spacing between register accesses.
|
||||
//Assuming if there was an access to a non-LPDDR4-PHY register
|
||||
//that would take more time than the required spacing,
|
||||
//this delay is added only when there are consecutive accesses
|
||||
//to LPDDR4-PHY registers, from the single thread that manages
|
||||
//the LPDDR4-PHY; it is also assumed that only one thread will
|
||||
//be managing the LPDDR4-PHY at the SoC level.
|
||||
//TODO: FIXME: The tb_wait routines should be replaced with appropriate
|
||||
//wait routines for SoC level
|
||||
if ( is_read )
|
||||
{
|
||||
//Command Spacing from Read to a following Read/Write: 2 pclk cycles.
|
||||
simulation_tb_wait(2, "apb");
|
||||
}
|
||||
else
|
||||
{
|
||||
//Command spacing from Write to a following Write/Read:
|
||||
// 1 pclk + (`DWC_AFIFO_SYNC_STAGES+ 4) ctl_clk cycles
|
||||
// DWC_AFIFO_SYNC_STAGES = 4; to be safe making it 10 ctl_clk cycles
|
||||
simulation_tb_wait(10, "mem");
|
||||
simulation_tb_wait(1, "apb");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static inline uint32_t hw_phy_read32(uint32_t* addr)
|
||||
{
|
||||
uint32_t ret;
|
||||
//hw_phy_regacc_wait(addr);
|
||||
#ifdef MCU_IP_VERIF
|
||||
bfm_read32(addr, &ret);
|
||||
#else
|
||||
ret = hw_read32((uint32_t*)addr);
|
||||
#endif //MCU_IP_VERIF
|
||||
hw_phy_regacc_post_wait(1);
|
||||
return ret;}
|
||||
|
||||
static inline void hw_phy_write32(uint32_t* addr, uint32_t data)
|
||||
{
|
||||
//hw_phy_regacc_wait(addr);
|
||||
#ifdef MCU_IP_VERIF
|
||||
bfm_write32(addr, data);
|
||||
#else
|
||||
hw_write32((uint32_t*)addr, data);
|
||||
#endif //MCU_IP_VERIF
|
||||
hw_phy_regacc_post_wait(0);
|
||||
}
|
||||
|
||||
|
||||
#ifdef MCU_IP_VERIF
|
||||
static inline uint32_t hw_read32(uint32_t* addr)
|
||||
{
|
||||
uint32_t ret;
|
||||
//hw_phy_regacc_wait(addr);
|
||||
bfm_read32(addr, &ret);
|
||||
return ret;}
|
||||
|
||||
static inline void hw_write32(uint32_t* addr, uint32_t data)
|
||||
{
|
||||
//hw_phy_regacc_wait(addr);
|
||||
bfm_write32(addr, data);
|
||||
}
|
||||
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
static inline void print_with_time(const char *line)
|
||||
{
|
||||
#ifdef MCU_IP_VERIF
|
||||
print_sim_time();
|
||||
#endif //MCU_IP_VERIF
|
||||
hw_status("%s", line);
|
||||
}
|
||||
|
||||
static inline uint32_t get_mcu_baseaddr(const int mc)
|
||||
{
|
||||
|
||||
uint32_t base_addr = 0;
|
||||
|
||||
#ifndef MCU_IP_VERIF
|
||||
base_addr = HUP_CHIP_MCU0_ADDRESS + (HUP_CHIP_MCU1_ADDRESS-HUP_CHIP_MCU0_ADDRESS)*mc;
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
return base_addr;
|
||||
}
|
||||
|
||||
//Helper functions
|
||||
//extern int dram_type;
|
||||
//extern lp4_ddc_params lp4_param_db;
|
||||
//extern lp3_ddc_params lp3_param_db;
|
||||
uint32_t getRandInterval(uint32_t begin, uint32_t end);
|
||||
#ifdef MCU_IP_VERIF
|
||||
void get_current_dir();
|
||||
void print_addr(volatile uint32_t* address);
|
||||
void do_yml_reg_writes(char *fname);
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
void set_reg(const int mc, uintptr_t addr, uint32_t field_mask, uint32_t data);
|
||||
void set_reg_val(const int mc, uintptr_t addr, uint32_t field_mask, uint32_t data);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
#ifndef MTC_INIT_H
|
||||
#define MTC_INIT_H
|
||||
|
||||
#include "conf_defs.h"
|
||||
#include <math.h>
|
||||
#include <assert.h>
|
||||
|
||||
#define WDLY_MASK 0x1ff
|
||||
#define NUM_SLICES 2
|
||||
#define MAX_SLICES 4
|
||||
#define NUM_RANKS 2
|
||||
#define NUM_READ_DELAYS 3
|
||||
#define MOV_WINDOW_MAX 63
|
||||
|
||||
#define DQSL 3
|
||||
#define TPRD 0x3f
|
||||
|
||||
#define DQS_CYCLE_TIME 625
|
||||
#define DQS_HALF_CYCLE_TIME DQS_CYCLE_TIME/2
|
||||
|
||||
// ----- Top level init functions -----
|
||||
void program_non_default_regs_for_mtc_read_and_write_training_init();
|
||||
void program_non_default_regs_for_mtc_write_training_init();
|
||||
void program_mtc_training_window_size(int val);
|
||||
void program_mtc_training_adj_step(int val);
|
||||
void read_methodA_init();
|
||||
|
||||
int get_WDQPRD(int dqs_no,int rankid);
|
||||
|
||||
// ----- Register Access functions ------
|
||||
void set_rank_id(int rankid);
|
||||
void set_dxngcr3_read_training_disable_drift_compensation(int dqs_no,int rankid);
|
||||
int get_phy_delay_write_reg(int dqs_no,int rankid);
|
||||
int get_mtc_delay_write_reg(int dqs_no,int rankid);
|
||||
int get_pub_gcr3_gateacctlclk();
|
||||
void set_pub_gcr3_gateacctlclk(int value);
|
||||
void set_dxngcr3_wdlvt(int dqs_no,int rankid,int value);
|
||||
void set_pubgcr3_pure(int value);
|
||||
void set_crb_active_ranks(int value);
|
||||
int get_phy_dxngtr0_dgsl(int dqs_no,int rankid);
|
||||
int get_phy_dxngtr0(int dqs_no,int rankid);
|
||||
int get_phy_dxngtr0_wdqsl(int dqs_no,int rankid);
|
||||
int get_dxnmdlr0_iprd(int dqs_no,int rankid);
|
||||
void set_mtc_dxngsr0 (int dqs_no,int rankid,int value);
|
||||
int get_mtc_dxngsr6(int dqs_no,int rankid);
|
||||
void set_mtc_dxngtr0 (int dqs_no,int rankid,int value);
|
||||
int get_mtc_dxngtr0_dgsl(int dqs_no,int rankid);
|
||||
int get_phy_dxngsr0_gdqsprd(int dqs_no,int rankid);
|
||||
int get_phy_dxngsr0(int dqs_no,int rankid);
|
||||
|
||||
// Helper functions
|
||||
unsigned int rand_interval(unsigned int min, unsigned int max);
|
||||
|
||||
// --- External Global variables ----
|
||||
int global_delay_model;
|
||||
int global_dram_mode, global_dram_frequency;
|
||||
int global_wdqdprd[NUM_SLICES];
|
||||
// Positive number for global_wire_delay_reg_wr means Write DQ is
|
||||
// delayed; thus the movement will be to the left;
|
||||
// Negative number for global_wire_delay_reg_wr means Write DQS is
|
||||
// delayed; thus the movement will be to the right.
|
||||
int global_wire_delay_reg_wr[NUM_RANKS][NUM_SLICES];
|
||||
|
||||
// Positive number for global_wire_delay_reg_rd means Read DQS is
|
||||
// delayed; thus the movement will be to the left;
|
||||
// Negative number for global_wire_delay_reg_rd means Read DQ is
|
||||
// delayed; thus the movement will be to the right.
|
||||
int global_wire_delay_reg_rd[NUM_RANKS][NUM_SLICES];
|
||||
|
||||
int global_drift_enabled_for_phy_based_training;
|
||||
|
||||
int global_wdqsl[NUM_RANKS][NUM_SLICES];
|
||||
int global_golden_wdqsl[NUM_RANKS][NUM_SLICES];
|
||||
int global_golden_wr_delay_val[NUM_RANKS][NUM_SLICES];
|
||||
int global_golden_rd_lr2_val[NUM_RANKS][NUM_SLICES];
|
||||
int global_golden_rd_lr3_val[NUM_RANKS][NUM_SLICES]; //Same is used for lr4 also
|
||||
int program_single_rank;
|
||||
int dxngtr0_dgsl[NUM_RANKS][NUM_SLICES];
|
||||
int dxngsr0_gdqsprd[NUM_RANKS][NUM_SLICES];
|
||||
int adjust_gate_delay[NUM_RANKS][NUM_SLICES];
|
||||
int global_final_adj_values[NUM_RANKS][NUM_SLICES];
|
||||
int global_final_gate_adj_values[NUM_RANKS][NUM_SLICES];
|
||||
int random_write_data ;
|
||||
int dont_program_training_regs_for_write ;
|
||||
int dont_program_training_regs_for_read ;
|
||||
int trn_frq;
|
||||
|
||||
// read configuration parameters
|
||||
int gate_adj_disable;
|
||||
int phy_based_delay_adj;
|
||||
int wdlvt_enable;
|
||||
|
||||
// Global default MTC test control variables
|
||||
int global_sample_cnt;
|
||||
int global_zqcal_break;
|
||||
|
||||
#endif
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
#ifndef __MTC_TRAIN_HEADER_INC_
|
||||
#define __MTC_TRAIN_HEADER_INC_
|
||||
|
||||
#include "conf_defs.h"
|
||||
#include <kahalu_sim_init.h>
|
||||
|
||||
// prototypes
|
||||
void mtc_phy_update_training_test();
|
||||
void mtc_training_tests(int mtc_test_num,int dram_mode,int autoref_int,int delay_model,int dram_frequency, int active_ranks);
|
||||
void create_write_training_delay_testcase(int mov_window);
|
||||
extern void set_autorefresh(const int mc, int interval,int dram_mode, const int dram_frequency);
|
||||
|
||||
#define PHY_REGS_PIR_OFFSET 0x1
|
||||
#define PHY_REGS_PGSR0_OFFSET 0x12
|
||||
#define STATUS_IDONE_COMPARE 0x1
|
||||
#define POLLING_LIMIT 100
|
||||
|
||||
#ifdef CONF_HAS___PHY_RTL
|
||||
#define GOLDEN_RD_DELAY_VAL_1600 0x1f
|
||||
#define GOLDEN_WR_DELAY_VAL_1600 0x5
|
||||
#define GOLDEN_WDQSL_VAL_1600 0x3
|
||||
#define GOLDEN_RDGSL_VAL_1600 0x1
|
||||
#define GOLDEN_RD_DELAY_VAL_1333 0x26
|
||||
#define GOLDEN_WR_DELAY_VAL_1333 0x3d
|
||||
#define GOLDEN_RD_DELAY_VAL_400 0x7d
|
||||
#define GOLDEN_WR_DELAY_VAL_400 0xdf
|
||||
#define MVM_DELTA 20
|
||||
#define MVM_DELTA_RD 20
|
||||
#else
|
||||
#define GOLDEN_RD_DELAY_VAL_1600 0
|
||||
#define GOLDEN_WR_DELAY_VAL_1600 1
|
||||
#define GOLDEN_RD_DELAY_VAL_1333 0
|
||||
#define GOLDEN_WR_DELAY_VAL_1333 1
|
||||
#define GOLDEN_RD_DELAY_VAL_400 0
|
||||
#define GOLDEN_WR_DELAY_VAL_400 1
|
||||
#define MVM_DELTA 5
|
||||
#define MVM_DELTA_RD 5
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
//
|
||||
// Autogenerated by h2inc flow. This file MUST be kept in sync with hup_chip.h!
|
||||
//
|
||||
.equiv HUP_CHIP_GPIO15_GPIOAFSEL_ADDRESS, 0x444b420
|
||||
.equiv HUP_GPIO_GPIOAFSEL_AFSEL_FIELD_MASK, 0xff
|
||||
.equiv HUP_CHIP_POR_GPIO_IE_GP127_GP96_ADDRESS, 0x40805ac
|
||||
.equiv HUP_CHIP_POR_GPIO_REG_OVERRIDE_ADDRESS, 0x40805e8
|
||||
.equiv HUP_POR_GPIO_REG_OVERRIDE_ENABLE_FIELD_MASK, 0x1
|
||||
.equiv HUP_CHIP_POR_SPI_DIV16_ADDRESS, 0x408050c
|
||||
.equiv HUP_POR_SPI_DIV16_SEL_FIELD_MASK, 0x1f
|
||||
.equiv HUP_CHIP_SPI5_CTRLR0_ADDRESS, 0x4465000
|
||||
.equiv HUP_CHIP_SPI5_CTRLR1_ADDRESS, 0x4465004
|
||||
.equiv HUP_CHIP_SPI5_SSIENR_ADDRESS, 0x4465008
|
||||
.equiv HUP_CHIP_SPI5_SER_ADDRESS, 0x4465010
|
||||
.equiv HUP_CHIP_SPI5_BAUDR_ADDRESS, 0x4465014
|
||||
.equiv HUP_CHIP_SPI5_DR0_ADDRESS, 0x4465060
|
||||
.equiv HUP_CHIP_SPI5_SR_ADDRESS, 0x4465028
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
|
||||
#include "kahalu_sim_init.h"
|
||||
#include "snps_lp4_phy_lib.h"
|
||||
|
||||
#ifdef CONF_HAS___PHY_RTL
|
||||
void phy_init_synps_lp4
|
||||
(
|
||||
const int mc,
|
||||
const int active_ranks,
|
||||
const int ddc_mode,
|
||||
const int wr_dbi_dis,
|
||||
const int rd_dbi_dis,
|
||||
const int dram_frequency,
|
||||
const int phy_init_train,
|
||||
const int dump_phy_regs,
|
||||
const int set_bdlr_val
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
|
||||
#include "kahalu_sim_init.h"
|
||||
#include "snps_lp4_phy_lib.h"
|
||||
|
||||
#ifdef CONF_HAS___PHY_RTL
|
||||
void phy_regs_initial_settings(const int mc, const int dram_frequency, const int ddc_mode, const int active_ranks, const int wr_dbi_dis, const int rd_dbi_dis);
|
||||
|
||||
void perform_cbt();
|
||||
|
||||
void wait_for_pgsr0_idone();
|
||||
|
||||
void set_pub_regs(const int mc, const int dram_mode, const int dram_frequency, const int ddc_mode, const int active_ranks, const int wr_dbi_dis, const int rd_dbi_dis);
|
||||
|
||||
int phy_real_init_synps_lp4
|
||||
(
|
||||
const int mc,
|
||||
const int ddc_mode,
|
||||
const int active_ranks,
|
||||
const int dram_frequency,
|
||||
const int wr_dbi_dis,
|
||||
const int rd_dbi_dis,
|
||||
const int skip_part_phy_init
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
|
||||
#include "kahalu_sim_init.h"
|
||||
|
||||
#ifdef CONF_HAS___PHY_RTL
|
||||
|
||||
void phy_init_synps_lp4_reg_write(const int mc, const int dram_frequency);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,276 +0,0 @@
|
|||
/*-------------------------------------------------------
|
||||
|
|
||||
| spi.inc
|
||||
|
|
||||
| routines for SPI operation.
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
|
|
||||
| Copyright ( C ) 2015 Microsoft Corp.
|
||||
| All Rights Reserved
|
||||
| Confidential and Proprietary
|
||||
|
|
||||
|--------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "sboot.inc"
|
||||
|
||||
// From hup_chip.h
|
||||
// gpio_regs[15].gpioafsel.afsel
|
||||
// Set GPIO 123-127 to hardware control
|
||||
.equiv HUP_GPIO_15_GPIOAFSEL_DATA, 0xF8
|
||||
|
||||
// From hup_chip.h
|
||||
// por_regs.GPIO_IE_GP127_GP96 GPIO_IE_GP127_GP96
|
||||
// Enable receiver on GPIO125
|
||||
.equiv HUP_POR_GPIO_IE3_DATA, 0x20000000
|
||||
.equiv HUP_POR_GPIO_IE3_MASK, 0x20000000
|
||||
|
||||
// From hup_chip.h
|
||||
// por_regs.GPIO_reg_override
|
||||
// Enable register overrides
|
||||
.equiv HUP_POR_GPIO_REG_OVERRIDE_DATA, 0x1
|
||||
|
||||
// From hup_chip.h
|
||||
// por_regs.spi_div16
|
||||
// set divider to 1/N
|
||||
.equiv HUP_POR_SPI_DIV_DATA, 0xF
|
||||
|
||||
// SCPH: 0x1 (clock toggles at start of first data bit)
|
||||
// SCPOL: 0x1 (inactive state is high)
|
||||
// TMOD: 0x3 (EEPROM read)
|
||||
// DFS_32: 0x7 (8 bit frame size)
|
||||
.equiv SPI_REGS_CTRLR0_DATA, 0x000703C0
|
||||
// Always use slave line 0
|
||||
.equiv SPI_REGS_SER_DATA_LO, 0x00000000
|
||||
.equiv SPI_REGS_SER_DATA_HI, 0x00000001
|
||||
.equiv SPI_REGS_BAUD_DATA, 0x00000002
|
||||
|
||||
// From Synopsys databook: https://iebhwdev/sites/Silicon/Makena/Shared%20Documents/Vendor/Synopsys/Databooks/LowSpeedIO/dw_apb_ssi_db_4p00a.pdf
|
||||
.equiv SPI_STS_BSY_BIT, 0
|
||||
// Transmit FIFO Not Full
|
||||
.equiv SPI_STS_TNF_BIT, 1
|
||||
// Transmit FIFO Empty
|
||||
.equiv SPI_STS_TFE_BIT, 2
|
||||
// Receive FIFO Not Empty
|
||||
.equiv SPI_STS_RNE_BIT, 3
|
||||
// Receive FIFO Full
|
||||
.equiv SPI_STS_RFF_BIT, 4
|
||||
|
||||
.equiv SPI_FLASH_READ_CMD, 0x03
|
||||
.equiv SPI_FLASH_READ_HDR_CMD, (0x000000 << 8) | SPI_FLASH_READ_CMD
|
||||
.equiv SPI_FLASH_HEADER_SIZE, 12
|
||||
|
||||
.equiv SPI_FRAME_MASK, 0x000000FF
|
||||
|
||||
// Shift loop counter. Starts at 32 and decrements
|
||||
// because Tensilica left shifting instruction shifts
|
||||
// by 32 - <reg value>
|
||||
.equiv READ_SHIFT_LOOP_START, 32
|
||||
.equiv READ_SHIFT_LOOP_END, 0
|
||||
.equiv READ_SHIFT_LOOP_INCR, -8
|
||||
|
||||
|
||||
// Stall until the SPI is idle.
|
||||
// Arguments:
|
||||
// pSr: Value will be clobbered. Used to point to the status register
|
||||
// pDr: Value will be clobbered. Used to point to the data register
|
||||
// SrData: Value will be clobbered. Used to store value read from status register
|
||||
// DrData: Value will be clobbered. Used to store value read from data register
|
||||
.macro SPI_IDLE pSr, pDr, SrData, DrData
|
||||
LOCAL .WaitWhileBusy
|
||||
LOCAL .RxFifoEmpty
|
||||
|
||||
movi \pSr, HUP_CHIP_SPI5_SR_ADDRESS
|
||||
movi \pDr, HUP_CHIP_SPI5_DR0_ADDRESS
|
||||
.WaitWhileBusy:
|
||||
// Read status register
|
||||
l32i \SrData, \pSr, 0
|
||||
// Branch down if Receive FIFO Not Empty flag not set
|
||||
bbci \SrData, SPI_STS_RNE_BIT, .RxFifoEmpty
|
||||
// Otherwise read from the data register
|
||||
l32i \DrData, \pDr, 0
|
||||
.RxFifoEmpty:
|
||||
// Branch back if Transmit FIFO Empty flag not set
|
||||
bbci \SrData, SPI_STS_TFE_BIT, .WaitWhileBusy
|
||||
// Branch back if Busy flag is set
|
||||
bbsi \SrData, SPI_STS_BSY_BIT, .WaitWhileBusy
|
||||
.endm
|
||||
|
||||
|
||||
// Read/modify/write a register
|
||||
// Arguments:
|
||||
// Temp: Value will be clobbered. Used to store temporary values
|
||||
// ReadValue: Value will be clobbered. Used to store the value read from the register
|
||||
// AddrReg: Value will be clobbered. Used to store the address value
|
||||
// MaskReg: Value will be clobbered. Used to store the mask value
|
||||
// Addr: address of the register
|
||||
// Data: data to write
|
||||
// Mask: data to write
|
||||
.macro REG_RMW_BITS Temp, ReadValue, AddrReg, MaskReg, Addr, Data, Mask
|
||||
movi \MaskReg, \Mask
|
||||
movi \AddrReg, \Addr
|
||||
// Read register value
|
||||
l32i \ReadValue, \AddrReg, 0
|
||||
// Invert mask and use it to zero
|
||||
// out the relevant bits in the reg value
|
||||
movi \Temp, -1
|
||||
xor \Temp, \Temp, \MaskReg
|
||||
and \ReadValue, \Temp, \ReadValue
|
||||
// Mask the data and OR it with the
|
||||
// remaining reg value
|
||||
movi \Temp, \Data
|
||||
and \Temp, \Temp, \MaskReg
|
||||
or \ReadValue, \Temp, \ReadValue
|
||||
// Write the register
|
||||
s32i \ReadValue, \AddrReg, 0
|
||||
.endm
|
||||
|
||||
|
||||
// Read 32 bits from the SPI data register
|
||||
// Arguments:
|
||||
// Ret: The register in which to store the return value
|
||||
// pSr: Value will be clobbered. Used to point to the status register
|
||||
// pDr: Value will be clobbered. Used to point to the data register
|
||||
// RegData: Value will be clobbered. Used to store value read from registers
|
||||
// Ctr: Value will be clobbered. Used as a counter for the read loop
|
||||
.macro SPI_RECV32 Ret, pSr, pDr, RegData, Ctr
|
||||
LOCAL .CheckRxAvail
|
||||
|
||||
movi \pSr, HUP_CHIP_SPI5_SR_ADDRESS
|
||||
movi \pDr, HUP_CHIP_SPI5_DR0_ADDRESS
|
||||
|
||||
// Zero out the return register
|
||||
movi \Ret, 0
|
||||
// Shift loop counter.
|
||||
movi \Ctr, READ_SHIFT_LOOP_START
|
||||
.CheckRxAvail:
|
||||
// Read status register
|
||||
l32i \RegData, \pSr, 0
|
||||
// Branch back if Receive FIFO Not Empty flag not set (meaning Receive FIFO is empty)
|
||||
bbci \RegData, SPI_STS_RNE_BIT, .CheckRxAvail
|
||||
// Read from Receive FIFO
|
||||
l32i \RegData, \pDr, 0
|
||||
// Shift left as necessary and OR
|
||||
// into the return register
|
||||
wsr.sar \Ctr
|
||||
sll \RegData, \RegData
|
||||
or \Ret, \RegData, \Ret
|
||||
|
||||
addi \Ctr, \Ctr, READ_SHIFT_LOOP_INCR
|
||||
// If not done, branch back and read another byte
|
||||
bnei \Ctr, READ_SHIFT_LOOP_END, .CheckRxAvail
|
||||
.endm
|
||||
|
||||
|
||||
// Read 8 bits from the SPI data register
|
||||
// Arguments:
|
||||
// Ret: The register in which to store the return value
|
||||
// pSr: Value will be clobbered. Used to point to the status register
|
||||
// pDr: Value will be clobbered. Used to point to the data register
|
||||
// RegData: Value will be clobbered. Used to store value read from registers
|
||||
// Ctr: Unused. Added to maintain same footprint as SPI_RECV32
|
||||
.macro SPI_RECV8 Ret, pSr, pDr, RegData, Ctr
|
||||
LOCAL .CheckRxAvail
|
||||
|
||||
movi \pSr, HUP_CHIP_SPI5_SR_ADDRESS
|
||||
movi \pDr, HUP_CHIP_SPI5_DR0_ADDRESS
|
||||
|
||||
.CheckRxAvail:
|
||||
// Read status register
|
||||
l32i \RegData, \pSr, 0
|
||||
// Branch back if Receive FIFO Not Empty flag not set (meaning Receive FIFO is empty)
|
||||
bbci \RegData, SPI_STS_RNE_BIT, .CheckRxAvail
|
||||
// Read from Receive FIFO
|
||||
l32i \Ret, \pDr, 0
|
||||
|
||||
.endm
|
||||
|
||||
// Initiate a Flash transfer by writing a
|
||||
// command over SPI.
|
||||
// Arguments:
|
||||
// Cmd: The register containing the command to write
|
||||
// Cnt: The number of bytes to be transferred
|
||||
// RegAddr: Value will be clobbered. Used to store addresses of various registers
|
||||
// RegData: Value will be clobbered. Used to store data which is written to or read from registers
|
||||
// TempCmd: Value will be clobbered. Stores intermediate values of the command as it is serialized
|
||||
// Ctr: Value will be clobbered. Used as a counter for the write loop
|
||||
.macro SPI_TRANSFER Cmd, Cnt, RegAddr, RegData, TempCmd, Ctr
|
||||
LOCAL .WaitTxAvail
|
||||
LOCAL .EndTx
|
||||
|
||||
// Barrier before disable
|
||||
memw
|
||||
|
||||
// Disable while configuring CTRLR1
|
||||
movi \RegAddr, HUP_CHIP_SPI5_SSIENR_ADDRESS
|
||||
//movi \RegAddr, SPI_REGS_SSIENR_ADDR
|
||||
movi \RegData, 0
|
||||
s32i \RegData, \RegAddr, 0
|
||||
|
||||
// Barrier after disable
|
||||
memw
|
||||
|
||||
// Set up CTRLR1 with the number of bytes to be written
|
||||
movi \RegAddr, HUP_CHIP_SPI5_CTRLR1_ADDRESS
|
||||
addi \RegData, \Cnt, -1
|
||||
s32i \RegData, \RegAddr, 0
|
||||
|
||||
// Disable slave select until
|
||||
// we've finished writing the command
|
||||
// into the TXFIFO
|
||||
movi \RegAddr, HUP_CHIP_SPI5_SER_ADDRESS
|
||||
movi \RegData, SPI_REGS_SER_DATA_LO
|
||||
s32i \RegData, \RegAddr, 0
|
||||
|
||||
// Barrier before enable
|
||||
memw
|
||||
|
||||
// Re-enable
|
||||
movi \RegAddr, HUP_CHIP_SPI5_SSIENR_ADDRESS
|
||||
movi \RegData, 1
|
||||
s32i \RegData, \RegAddr, 0
|
||||
|
||||
// Barrier after enable
|
||||
memw
|
||||
|
||||
// Store off the command value to a temp register
|
||||
mov \TempCmd, \Cmd
|
||||
movi \Ctr, 0
|
||||
.WaitTxAvail:
|
||||
// Read status register into RegData
|
||||
//movi \RegAddr, SPI_REGS_SSPSR_ADDR
|
||||
movi \RegAddr, HUP_CHIP_SPI5_SR_ADDRESS
|
||||
l32i \RegData, \RegAddr, 0
|
||||
// If Transmit FIFO Not Full flag is not set (meaning FIFO is full), branch back
|
||||
bbci \RegData, SPI_STS_TNF_BIT, .WaitTxAvail
|
||||
// Mask data for first byte
|
||||
movi \RegData, SPI_FRAME_MASK
|
||||
and \RegData, \RegData, \TempCmd
|
||||
// Write to data register
|
||||
//movi \RegAddr, SPI_REGS_SSPDR_ADDR
|
||||
movi \RegAddr, HUP_CHIP_SPI5_DR0_ADDRESS
|
||||
s32i \RegData, \RegAddr, 0
|
||||
// Barrier to ensure bytes arrive
|
||||
// at the SPI in order
|
||||
memw
|
||||
// Shift data for next byte
|
||||
srli \TempCmd, \TempCmd, 8
|
||||
|
||||
// As long as there is data left to send, branch back and transmit next byte
|
||||
addi \Ctr, \Ctr, 8
|
||||
blti \Ctr, 32, .WaitTxAvail
|
||||
|
||||
// Barrier before reenabling slave select
|
||||
memw
|
||||
|
||||
// Reenable slave select to actually begin the transfer
|
||||
movi \RegAddr, HUP_CHIP_SPI5_SER_ADDRESS
|
||||
movi \RegData, SPI_REGS_SER_DATA_HI
|
||||
s32i \RegData, \RegAddr, 0
|
||||
|
||||
// Barrier after reenabling slave select
|
||||
memw
|
||||
|
||||
.endm
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,22 +0,0 @@
|
|||
#ifndef __KAHALU_GLOBALS_HEADER_INC
|
||||
#define __KAHALU_GLOBALS_HEADER_INC
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stddef.h>
|
||||
#include <unistd.h>
|
||||
#ifdef MCU_IP_VERIF
|
||||
#include <svdpi.h>
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
#include <kahalu_global_defines.h>
|
||||
|
||||
//Global variables
|
||||
|
||||
static REGACC_TYPE g_last_regacc_type;
|
||||
|
||||
static uint32_t* g_last_regacc_addr;
|
||||
|
||||
|
||||
#endif //__KAHALU_GLOBALS_HEADER_INC
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,169 +0,0 @@
|
|||
#include <kahalu_utils.h>
|
||||
|
||||
|
||||
void simulation_tb_wait(uint32_t cycles, const char * clock) {
|
||||
|
||||
hw_sleep(cycles * 10); //Slowest clock for now.
|
||||
|
||||
}
|
||||
|
||||
uint32_t getRandInterval(uint32_t begin, uint32_t end) {
|
||||
uint32_t range = 1 + end - begin;
|
||||
uint32_t limit = RAND_MAX - (RAND_MAX % range);
|
||||
|
||||
uint32_t randVal;
|
||||
do {
|
||||
randVal = rand();
|
||||
} while (randVal >= limit);
|
||||
|
||||
return (randVal % range) + begin;
|
||||
}
|
||||
|
||||
void print_addr(volatile uint32_t* address){
|
||||
int print_val = 0;
|
||||
print_val = (intptr_t)address;
|
||||
hw_status("printval from function : %08x\n", print_val);
|
||||
}
|
||||
|
||||
void set_reg(const int mc, uintptr_t addr, uint32_t field_mask, uint32_t data){
|
||||
|
||||
uint32_t i, prog_val;
|
||||
uint32_t mc_base_addr = get_mcu_baseaddr(mc);
|
||||
|
||||
hw_status("Received addr = %08x, field_mask = %-8x, data = %08x\n", (addr + mc_base_addr), field_mask, data);
|
||||
|
||||
if(field_mask != 0){
|
||||
//calculate how much we need to shift the data
|
||||
for(i=0; (((field_mask>>i)&1)==0); i++);
|
||||
}else{
|
||||
hw_status("Write mask is 0, returning without programming\n");
|
||||
return;
|
||||
}
|
||||
|
||||
hw_status("Read Address = %08x\n", (addr + mc_base_addr));
|
||||
|
||||
//get the data in the register
|
||||
prog_val = hw_read32((uint32_t *)(addr + mc_base_addr));
|
||||
|
||||
//clear the field we want to program
|
||||
prog_val = prog_val & (~field_mask);
|
||||
|
||||
//put data in the field
|
||||
prog_val |= ((data<<i)&field_mask);
|
||||
|
||||
hw_status("Writing Address = %08x With Value = %08x\n", (addr + mc_base_addr), prog_val);
|
||||
|
||||
//program the value
|
||||
hw_write32((uint32_t *)(addr + mc_base_addr), prog_val);
|
||||
}
|
||||
|
||||
void set_reg_val(const int mc, uintptr_t addr, uint32_t field_mask, uint32_t data){
|
||||
|
||||
uint32_t i, prog_val;
|
||||
uint32_t mc_base_addr = get_mcu_baseaddr(mc);
|
||||
|
||||
hw_status("Set Reg Val Received addr = %08x, field_mask = %-8x, data = %08x\n", (addr + mc_base_addr), field_mask, data);
|
||||
|
||||
if(field_mask != 0){
|
||||
//calculate how much we need to shift the data
|
||||
//for(i=0; (((field_mask>>i)&1)==0); i++);
|
||||
}else{
|
||||
hw_status("Write mask is 0, returning without programming\n");
|
||||
return;
|
||||
}
|
||||
|
||||
hw_status("Read Address = %08x\n", (addr + mc_base_addr));
|
||||
|
||||
//get the data in the register
|
||||
prog_val = hw_read32((uint32_t *)(addr + mc_base_addr));
|
||||
hw_status("read back data = %08x",prog_val);
|
||||
//clear the field we want to program
|
||||
prog_val = prog_val & (~field_mask);
|
||||
hw_status("cleared read data = %08x",prog_val);
|
||||
|
||||
//put data in the field
|
||||
prog_val |= (data & field_mask);
|
||||
|
||||
hw_status("Writing Address = %08x With Value = %08x\n", (addr + mc_base_addr), prog_val);
|
||||
|
||||
//program the value
|
||||
hw_write32((uint32_t *)(addr + mc_base_addr), prog_val);
|
||||
}
|
||||
|
||||
void do_yml_reg_writes(char *fname){
|
||||
uint32_t line_val, line_num, prog_addr, prog_data, prog_mask;
|
||||
char line[80];
|
||||
FILE *fr;
|
||||
|
||||
/*"rt" means open the file for reading text */
|
||||
/* open the file for reading */
|
||||
fr = fopen (fname, "rt");
|
||||
|
||||
if(fr==NULL){
|
||||
hw_status("Cound not find %s Skipping do_yml_reg_writes()\n", fname);
|
||||
return;
|
||||
}else{
|
||||
hw_status("Found %s, proceeding with do_yml_reg_writes()\n", fname);
|
||||
}
|
||||
|
||||
line_num = 0;
|
||||
|
||||
while(fgets(line, 80, fr) != NULL)
|
||||
{
|
||||
line_val = (uint32_t)strtol(line, NULL, 2);
|
||||
hw_status ("Read line from file: %08x ", line_val);
|
||||
|
||||
if(line_num == 0){
|
||||
//do nothing
|
||||
hw_status("num regs\n");
|
||||
}else if((line_num%3)==1){
|
||||
prog_addr = line_val;
|
||||
hw_status("addr\n");
|
||||
}else if((line_num%3)==2){
|
||||
prog_mask = line_val;
|
||||
hw_status("mask\n");
|
||||
}else if((line_num%3)==0){
|
||||
prog_data = line_val;
|
||||
hw_status("data\n");
|
||||
set_reg(0, prog_addr, prog_mask, prog_data);
|
||||
}
|
||||
line_num++;
|
||||
}
|
||||
|
||||
fclose(fr); /* close the file prior to exiting the routine */
|
||||
}
|
||||
|
||||
#ifdef MCU_IP_VERIF
|
||||
void get_current_dir(){
|
||||
char cwd[1024];
|
||||
if (getcwd(cwd, sizeof(cwd)) != NULL)
|
||||
fprintf(stdout, "Current working dir: %s\n", cwd);
|
||||
else
|
||||
perror("getcwd() error");
|
||||
}
|
||||
#endif //MCU_IP_VERIF
|
||||
|
||||
|
||||
/*
|
||||
UINT32 get_reg(volatile UINT32* addr, UINT32 field_mask){
|
||||
|
||||
UINT32 ret_val = (hw_read32(addr) & field_mask);
|
||||
|
||||
if(field_mask == 0){
|
||||
return 0;
|
||||
} else{
|
||||
while((field_mask & 0x1)==0){
|
||||
field_mask >>= 1;
|
||||
ret_val >>= 1;
|
||||
}
|
||||
}
|
||||
return ret_val;
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,537 +0,0 @@
|
|||
|
||||
#include "kahalu_sim_init.h"
|
||||
#include "snps_lp4_phy_lib.h"
|
||||
|
||||
#ifdef CONF_HAS___PHY_RTL
|
||||
void phy_init_synps_lp4(const int mc, const int active_ranks, const int ddc_mode, const int wr_dbi_dis, const int rd_dbi_dis, const int dram_frequency, const int phy_init_train, const int dump_phy_regs, const int set_bdlr_val) {
|
||||
uint32_t rd_data = 0;
|
||||
uint32_t wr_data = 0;
|
||||
uint32_t rd_addr = 0;
|
||||
uint32_t rl_val = 0;
|
||||
uint32_t rtp_val = 0;
|
||||
uint32_t tmp_set_bdlr_val;
|
||||
|
||||
uint32_t mc_base_addr = get_mcu_baseaddr(mc);
|
||||
|
||||
hw_status("KAHALU_SIM_INIT: SNPS PHY INIT frequency = %0d, ddc_mode = %0d, wr_dbi_dis= %0d, rd_dbi_dis = %0d\n", dram_frequency, ddc_mode, wr_dbi_dis, rd_dbi_dis);
|
||||
|
||||
program_ddc_phy_params(mc, rd_dbi_dis, dram_frequency);
|
||||
|
||||
hw_status("KAHALU_SIM_INIT: DEASSERTING RESET to PHY\n");
|
||||
hw_write32((uint32_t*)(MCU_REGS_PHYCTRL_REGS_SNP_CTL_RST_N_ADDRESS + mc_base_addr), 0x01);
|
||||
|
||||
//Enable PUB mode
|
||||
hw_status("KAHALU_SIM_INIT: ENABLING PUB\n");
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR1_ADDRESS + mc_base_addr), 0x02024640);
|
||||
|
||||
//for MTC coverage
|
||||
if (set_bdlr_val != 0)
|
||||
{
|
||||
wr_data = PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_RANKWID_SET(0) | PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_RANKRID_SET(0);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_ADDRESS, wr_data);
|
||||
tmp_set_bdlr_val = set_bdlr_val & 0xff;
|
||||
wr_data = (tmp_set_bdlr_val << 24) | (tmp_set_bdlr_val << 16) | (tmp_set_bdlr_val << 8) | tmp_set_bdlr_val;
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0BDLR3_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0BDLR4_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0BDLR5_ADDRESS, tmp_set_bdlr_val);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1BDLR3_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1BDLR4_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1BDLR5_ADDRESS, tmp_set_bdlr_val);
|
||||
wr_data = PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_RANKWID_SET(1) | PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_RANKRID_SET(1);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_ADDRESS, wr_data);
|
||||
wr_data = (tmp_set_bdlr_val << 24) | (tmp_set_bdlr_val << 16) | (tmp_set_bdlr_val << 8) | tmp_set_bdlr_val;
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0BDLR3_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0BDLR4_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0BDLR5_ADDRESS, tmp_set_bdlr_val);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1BDLR3_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1BDLR4_ADDRESS, wr_data);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1BDLR5_ADDRESS, tmp_set_bdlr_val);
|
||||
wr_data = PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_RANKWID_SET(0) | PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_RANKRID_SET(0);
|
||||
hw_phy_write32((uint32_t*) MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_RANKIDR_ADDRESS, wr_data);
|
||||
}
|
||||
|
||||
//Reconfigure DQ/DM Mapping for DXnDQMAP;
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0DQMAP0_ADDRESS + mc_base_addr), 0x00035678);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX0DQMAP1_ADDRESS + mc_base_addr), 0x00004012);
|
||||
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1DQMAP0_ADDRESS + mc_base_addr), 0x00035678);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX1DQMAP1_ADDRESS + mc_base_addr), 0x00004012);
|
||||
|
||||
//Programming DRAM Configuration (setting memory type to LP4)
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DCR_ADDRESS + mc_base_addr), 0x0000040d);
|
||||
|
||||
//Driving retention enable ports of PHY top
|
||||
hw_write32((uint32_t*)(MCU_REGS_PHYCTRL_REGS_SNP_RET_EN_N_ADDRESS + mc_base_addr), 0x1);
|
||||
hw_write32((uint32_t*)(MCU_REGS_PHYCTRL_REGS_SNP_RET_EN_I_ADDRESS + mc_base_addr), 0x2);
|
||||
hw_write32((uint32_t*)(MCU_REGS_PHYCTRL_REGS_SNP_EXT_EN_I_ADDRESS + mc_base_addr), 0x01);
|
||||
|
||||
//PHY Timing registers
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PTR1_ADDRESS + mc_base_addr), 0x2e8112c0);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PTR3_ADDRESS + mc_base_addr), 0x00000014);
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PTR4_ADDRESS + mc_base_addr));
|
||||
rd_data = rd_data & (uint32_t)(~PHY_REGS_DWC_DDRPHY_PUB_PTR4_TDINIT1_FIELD_MASK);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PTR4_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_PTR4_TDINIT1_SET(lp4_param_db.xpd[ddc_mode]+2)) );
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PTR5_ADDRESS + mc_base_addr), 0x00000014);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PTR6_ADDRESS + mc_base_addr), 0x03300640);
|
||||
|
||||
//FREQ VARIATION -- Frequency of clk_mem = 0.5 * DRAM clock frequency
|
||||
//PLL Control Register 0 for 400MHz
|
||||
if (dram_frequency == 400) {
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_FRQSEL_SET(0x6)) );
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_FRQSEL_SET(0x6)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_FRQSEL_SET(0x6)));
|
||||
} else if (dram_frequency == 800) {
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_FRQSEL_SET(0x2)) );
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_FRQSEL_SET(0x2)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_FRQSEL_SET(0x2)));
|
||||
} else if (dram_frequency == 1066) {
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_PLLCR0_FRQSEL_SET(0x1)) );
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL0PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL1PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL2PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL3PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL4PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL5PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL6PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL7PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SL8PLLCR0_FRQSEL_SET(0x1)));
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_ADDRESS + mc_base_addr));
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_ADDRESS + mc_base_addr), (uint32_t)(rd_data|PHY_REGS_DWC_DDRPHY_PUB_DX8SLBPLLCR0_FRQSEL_SET(0x1)));
|
||||
}
|
||||
|
||||
//DRAM timing parameter
|
||||
// DTPR0:
|
||||
// [4:0] = RTP (MR2 [2:0])
|
||||
// [14:8] = RP (maps to RPab typical cycles = 34)
|
||||
// [22:16] = RAS
|
||||
// [28:24] = RRD
|
||||
|
||||
wr_data = 0;
|
||||
|
||||
if(ddc_mode == DDC_MICRON){
|
||||
hw_status("KAHALU_SIM_INIT: DDC_MODE is DDC_MICRON\n");
|
||||
rl_val = lp4_param_db.rl[DDC_TYP];
|
||||
rtp_val = lp4_param_db.rtp[DDC_TYP];
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rl = %d\n",lp4_param_db.rl[DDC_TYP]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rtp = %d\n",lp4_param_db.rtp[DDC_TYP]);
|
||||
} else{
|
||||
hw_status("KAHALU_SIM_INIT: DDC_MODE is not DDC_MICRON\n");
|
||||
rl_val = lp4_param_db.rl[DDC_REG];
|
||||
//rl_val = 28;
|
||||
rtp_val = lp4_param_db.rtp[DDC_REG];
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rl = %d\n",lp4_param_db.rl[DDC_TYP]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rtp = %d\n",lp4_param_db.rtp[DDC_TYP]);
|
||||
}
|
||||
|
||||
if((rl_val == 6) && (rtp_val == 8)){
|
||||
wr_data = 0;
|
||||
}else if (((rl_val == 10)||(rl_val == 12)) && (rtp_val == 8)){
|
||||
wr_data = 1;
|
||||
}else if((rl_val == 14) && (rtp_val == 8)){
|
||||
wr_data = 2;
|
||||
}else if((rl_val == 20) && (rtp_val == 8)){
|
||||
wr_data = 3;
|
||||
}else if(((rl_val == 24)||(rl_val == 28)) && (rtp_val == 10)){
|
||||
wr_data = 4;
|
||||
}else if(((rl_val == 28)||(rl_val == 32)) && (rtp_val == 12)){ //*
|
||||
wr_data = 5;
|
||||
}else if(((rl_val == 32) ||(rl_val == 36)) && (rtp_val == 14)){
|
||||
wr_data = 6;
|
||||
}else if(((rl_val == 36)||(rl_val == 40)) && (rtp_val == 16)){
|
||||
wr_data = 7;
|
||||
}else{
|
||||
wr_data = 0;
|
||||
}
|
||||
|
||||
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rpab=%d\n",lp4_param_db.rpab[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.ras=%d\n" ,lp4_param_db.ras[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rrd=%d\n",lp4_param_db.rrd[ddc_mode]);
|
||||
|
||||
|
||||
//hw_status("ddc_mode=%d\n",ddc_mode);
|
||||
//hw_status("RPAB: {%d,%d,%d,%d,%d,%d}",lp4_param_db.rpab[0],lp4_param_db.rpab[1],lp4_param_db.rpab[2],lp4_param_db.rpab[3],lp4_param_db.rpab[4],lp4_param_db.rpab[5]);
|
||||
|
||||
hw_status("DTPR0.rpab=%d\n",lp4_param_db.rpab[ddc_mode]);
|
||||
hw_status("DTPR0.ras=%d\n" ,lp4_param_db.ras[ddc_mode]);
|
||||
hw_status("DTPR0.rrd=%d\n",lp4_param_db.rrd[ddc_mode]);
|
||||
wr_data = ((wr_data << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR0_TRTP_LSB) |
|
||||
(lp4_param_db.rpab[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR0_TRP_LSB) |
|
||||
(lp4_param_db.ras[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR0_TRAS_LSB) |
|
||||
(lp4_param_db.rrd[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR0_TRRD_LSB) );
|
||||
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR0_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
// DTPR1:
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TWLMRD_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TFAW_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TMOD_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TMRD_LSB
|
||||
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.faw=%d\n",lp4_param_db.faw[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.mrd=%d\n" ,lp4_param_db.mrd[ddc_mode]);
|
||||
hw_status("DTPR1.faw=%d\n",lp4_param_db.faw[ddc_mode]);
|
||||
hw_status("DTPR1.mrd=%d\n",lp4_param_db.mrd[ddc_mode]);
|
||||
wr_data = ((16 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TWLMRD_LSB) |
|
||||
(lp4_param_db.faw[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TFAW_LSB) |
|
||||
(7 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TMOD_LSB) | //MOD is DDR3/DDR4 param. Don't care for LPDDR.
|
||||
(lp4_param_db.mrd[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR1_TMRD_LSB) );
|
||||
|
||||
//Use database timing value to program timing registers
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR1_ADDRESS, 0x1740071A);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR1_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
// DTRP2:
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TRTW_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TRTODT_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TCMDCKE_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TCKE_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TXS_LSB
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.cmdcke=%d\n",lp4_param_db.cmdcke[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.cke=%d\n" ,lp4_param_db.cke[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.xsr=%d\n" ,lp4_param_db.xsr[ddc_mode]);
|
||||
hw_status("DTPR2.cmdcke=%d\n",lp4_param_db.cmdcke[ddc_mode]);
|
||||
hw_status("DTPR2.cke=%d\n" ,lp4_param_db.cke[ddc_mode]);
|
||||
hw_status("DTPR2.xsr=%d\n" ,lp4_param_db.xsr[ddc_mode]);
|
||||
wr_data = ((0 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TRTW_LSB) | //Stardard bus turn around delay; No additional delay
|
||||
(0 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TRTODT_LSB) | //MOD is DDR3/DDR4 param. Don't care for LPDDR.
|
||||
(lp4_param_db.cmdcke[ddc_mode]<< (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TCMDCKE_LSB) |
|
||||
(lp4_param_db.cke[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TCKE_LSB) |
|
||||
(7 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TVRCG_LSB) |
|
||||
(lp4_param_db.xsr[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR2_TXS_LSB) );
|
||||
|
||||
//Use database timing value to program timing registers
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR2_ADDRESS, 0x000c01d9);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR2_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
// DTRP3:
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TOFDX_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TCCD_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TDLLK_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TDQSCKMAX_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TDQSCK_LSB
|
||||
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.dqsck=%d\n",lp4_param_db.dqsck[ddc_mode]);
|
||||
hw_status("DTPR3.dqsckmax=%d\n",lp4_param_db.dqsck[ddc_mode]);
|
||||
hw_status("DTPR3.dqsck=%d\n",lp4_param_db.dqsck[ddc_mode]);
|
||||
wr_data = ((0 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TOFDX_LSB) | //ODT turn-off dealy extention = 0
|
||||
(0 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TCCD_LSB) | //CCD=BL/2
|
||||
(384 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TDLLK_LSB) | //Don't care. DLL locking time. Use default in PUB.
|
||||
(lp4_param_db.dqsck[ddc_mode]<< (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TDQSCKMAX_LSB) |
|
||||
(lp4_param_db.dqsck[ddc_mode]<< (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR3_TDQSCK_LSB) );
|
||||
|
||||
//1600MHz setting
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR3_ADDRESS, 0x02000606);
|
||||
//1333MHz setting
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR3_ADDRESS, 0x02000505);
|
||||
//Use database timing value to program timing registers
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR3_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
// DTRP4:
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TAOND_TAOFD_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TRFC_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TWLO_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TXP_LSB
|
||||
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rfcab=%d\n",lp4_param_db.rfcab[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.xpd=%d\n",lp4_param_db.xpd[ddc_mode]);
|
||||
hw_status("DTPR4.rfcab=%d\n",lp4_param_db.rfcab[ddc_mode]);
|
||||
hw_status("DTPR4.xpd=%d\n",lp4_param_db.xpd[ddc_mode]);
|
||||
wr_data = ((0 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TAOND_TAOFD_LSB) | //DDR2 only. Don't care. Set to 0.
|
||||
(lp4_param_db.rfcab[ddc_mode]<< (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TRFC_LSB) |
|
||||
(43 << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TWLO_LSB) | //Not used by DDC; Use default
|
||||
(lp4_param_db.xpd[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR4_TXP_LSB) );
|
||||
|
||||
//Use database timing value to program timing registers
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR4_ADDRESS, 0x01202814);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR4_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
// DTRP5:
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR5_TRC_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR5_TRCD_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR5_TWTR_LSB
|
||||
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rcpb=%d\n",lp4_param_db.rcpb[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.rcd=%d\n",lp4_param_db.rcd[ddc_mode]);
|
||||
//please don't delete. Needed for SoC porting - hw_status("lp4_param_db.wtr=%d\n",lp4_param_db.wtr[ddc_mode]);
|
||||
hw_status("DTPR5.rcpb=%d\n",lp4_param_db.rcpb[ddc_mode]);
|
||||
hw_status("DTPR5.rcd=%d\n",lp4_param_db.rcd[ddc_mode]);
|
||||
hw_status("DTPR5.wtr=%d\n",lp4_param_db.wtr[ddc_mode]);
|
||||
wr_data = ((lp4_param_db.rcpb[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR5_TRC_LSB) |
|
||||
(lp4_param_db.rcd[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR5_TRCD_LSB) |
|
||||
(lp4_param_db.wtr[ddc_mode] << (uint32_t)PHY_REGS_DWC_DDRPHY_PUB_DTPR5_TWTR_LSB) );
|
||||
|
||||
//Use database timing value to program timing registers
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR5_ADDRESS, 0x60654410);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR5_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
// DTRP6:
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR6_PUBWLEN_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR6_PUBRLEN_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR6_PUBWL_LSB
|
||||
//PHY_REGS_DWC_DDRPHY_PUB_DTPR6_PUBRL_LSB
|
||||
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTPR6_ADDRESS + mc_base_addr), 0x00000000); //RL/WL disabled in PUB. Will be calculated from MR settings.
|
||||
|
||||
|
||||
//ZQCR Configuration register for ZQ cal
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_ZQCR_ADDRESS + mc_base_addr), 0x008a2c58);
|
||||
|
||||
|
||||
// PIR. Initiates PLL initialization, Impedence caliberation, Delay line caliberation.
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PIR_ADDRESS + mc_base_addr), 0x00000073);
|
||||
|
||||
//FREQ VARIATION
|
||||
//PGCR2 PHY general configuration register
|
||||
if (dram_frequency == 400) {
|
||||
//mem_clk_freq = 200MHz
|
||||
//mem_clk_period = 5ns
|
||||
//Adding 10% margin = 5.5ns
|
||||
//tREFPRD = (9*3900/mem_clk_period)-600 = 5781 = 0x1695
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR2_ADDRESS + mc_base_addr), 0x10f01695);
|
||||
} else if (dram_frequency == 800) {
|
||||
//mem_clk_freq = 400MHz
|
||||
//mem_clk_period = 2.5ns
|
||||
//Adding 10% margin = 2.75ns
|
||||
//tREFPRD = (9*3900/mem_clk_period)-600 = 12164 = 0x2f84
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR2_ADDRESS + mc_base_addr), 0x10f02f84);
|
||||
} else if (dram_frequency == 1066) {
|
||||
//mem_clk_freq = 533MHz
|
||||
//mem_clk_period = 1.876ns
|
||||
//Adding 10% margin = 2.06ns
|
||||
//tREFPRD = (9*3900/mem_clk_period)-600 = 12164 = 0x4037
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR2_ADDRESS + mc_base_addr), 0x10f04037);
|
||||
} else if (dram_frequency == 1333) {
|
||||
//mem_clk_freq = 666.6666MHz
|
||||
//mem_clk_period = 1.5ns
|
||||
//Adding 10% margin = 1.65ns
|
||||
//tREFPRD = (9*3900/mem_clk_period)-600 = 20672 = 0x50c0
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR2_ADDRESS + mc_base_addr), 0x10f050c0);
|
||||
} else {
|
||||
//mem_clk_freq = 800MHz
|
||||
//mem_clk_period = 1.25ns
|
||||
//Adding 10% margin = 1.375ns
|
||||
//tREFPRD = (9*3900/mem_clk_period)-600 = 24927 = 0x615f
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR2_ADDRESS + mc_base_addr), 0x10f0615f);
|
||||
}
|
||||
|
||||
|
||||
//Waiting for PLL initialization, Impedence caliberation, Delay line caliberation to be complete
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGSR0_ADDRESS + mc_base_addr));
|
||||
|
||||
rd_data = 0;
|
||||
do{
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGSR0_ADDRESS + mc_base_addr));
|
||||
}while((rd_data & 0x00000001) != 0x00000001);
|
||||
|
||||
hw_status("KAHALU_SIM_INIT: PLL INITIALIZATION COMPLETE\n");
|
||||
|
||||
|
||||
|
||||
//MR0
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR0_ADDRESS + mc_base_addr), 0x00000000);
|
||||
|
||||
//FREQ VARIATION
|
||||
//MR1
|
||||
if (dram_frequency == 400) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR1_ADDRESS + mc_base_addr), 0x00000016);
|
||||
} else if (dram_frequency == 800) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR1_ADDRESS + mc_base_addr), 0x00000026); //nWR=16, wr-preable =2 nclk, BL=2'b10
|
||||
} else if (dram_frequency == 1066) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR1_ADDRESS + mc_base_addr), 0x00000036); //nWR=20, wr-preable =2 nclk, BL=2'b10
|
||||
} else if (dram_frequency == 1333) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR1_ADDRESS + mc_base_addr), 0x00000046); //nWR=24, wr-preable =2 nclk, BL=2'b10
|
||||
} else {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR1_ADDRESS + mc_base_addr), 0x00000056); //nWR=30, wr-preable =2 nclk, BL=2'b10
|
||||
}
|
||||
|
||||
//MR3
|
||||
|
||||
//write MR3 to enable rd and wr dbi except when dbi is disabled by test
|
||||
if( (wr_dbi_dis ==1) && (rd_dbi_dis == 1) )
|
||||
wr_data = 0x31; //00110001 wr_dbi + rd_dbi cleared
|
||||
else if(wr_dbi_dis)
|
||||
wr_data = 0x71; //01110001 wr_dbi cleared
|
||||
else if(rd_dbi_dis)
|
||||
wr_data = 0xb1; //10110001 rd_dbi cleared
|
||||
else
|
||||
wr_data = 0xf1; //enable both
|
||||
|
||||
//hw_phy_write32((uint32_t)MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR3_ADDRESS, 0x000000f1);
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR3_ADDRESS + mc_base_addr), wr_data);
|
||||
|
||||
//FREQ VARIATION
|
||||
//MR2
|
||||
if (dram_frequency == 400) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR2_ADDRESS + mc_base_addr), 0x000000009);
|
||||
} else if (dram_frequency == 800) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR2_ADDRESS + mc_base_addr), 0x000000012);
|
||||
} else if (dram_frequency == 1066) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR2_ADDRESS + mc_base_addr), 0x00000001b);
|
||||
} else if (dram_frequency == 1333) {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR2_ADDRESS + mc_base_addr), 0x000000024);
|
||||
} else {
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR2_ADDRESS + mc_base_addr), 0x00000002D);
|
||||
}
|
||||
//MR4
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR4_ADDRESS + mc_base_addr), 0x00000003);
|
||||
|
||||
//MR12
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR12_ADDRESS + mc_base_addr), 0x0000004D);
|
||||
|
||||
//MR11
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_MR11_ADDRESS + mc_base_addr), 0x00000000);
|
||||
|
||||
|
||||
// DX8SL0DXCTL2 Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0DXCTL2_ADDRESS + mc_base_addr), 0x00281800);
|
||||
|
||||
// DX8SL1DXCTL2 Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1DXCTL2_ADDRESS + mc_base_addr), 0x00281800);
|
||||
|
||||
// DX8SL2DXCTL2 Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2DXCTL2_ADDRESS + mc_base_addr), 0x00281800);
|
||||
|
||||
// DX8SL3DXCTL2 Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2DXCTL2_ADDRESS + mc_base_addr), 0x00281800);
|
||||
|
||||
// DX8SL0DQSCTL Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL0DQSCTL_ADDRESS + mc_base_addr), 0x012640c4);
|
||||
|
||||
// DX8SL1DQSCTL Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL1DQSCTL_ADDRESS + mc_base_addr), 0x012640c4);
|
||||
|
||||
// DX8SL2DQSCTL Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL2DQSCTL_ADDRESS + mc_base_addr), 0x012640c4);
|
||||
|
||||
// DX8SL3DQSCTL Data slice control register. Value got from Synopsys
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX8SL3DQSCTL_ADDRESS + mc_base_addr), 0x012640c4);
|
||||
|
||||
// DSGCR PHY update request disabled
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DSGCR_ADDRESS + mc_base_addr), 0x02a04180);
|
||||
|
||||
// DTCR0 Training configuration register.
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTCR0_ADDRESS + mc_base_addr), 0x900051c7);
|
||||
|
||||
if (active_ranks == 1) {
|
||||
//DTCR1 Training configuration register.
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTCR1_ADDRESS + mc_base_addr), 0x00010236);
|
||||
} else {
|
||||
//DTCR1 Training configuration register.
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DTCR1_ADDRESS + mc_base_addr), 0x00030236);
|
||||
}
|
||||
|
||||
|
||||
// Starting DRAM initializarion
|
||||
hw_status("KAHALU_SIM_INIT: DRAM INITIALIZATION STARTED\n");
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PIR_ADDRESS + mc_base_addr), 0x00000181);
|
||||
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGSR0_ADDRESS + mc_base_addr));
|
||||
|
||||
rd_data = 0;
|
||||
do{
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGSR0_ADDRESS + mc_base_addr));
|
||||
}while((rd_data & 0x00000001) != 0x00000001);
|
||||
|
||||
hw_status("KAHALU_SIM_INIT: DRAM INITIALIZATION COMPLETE\n");
|
||||
|
||||
if (dump_phy_regs) {
|
||||
hw_status("DUMPING ALL REGISTERS BEFORE TRAINING\n");
|
||||
|
||||
rd_addr = MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_RIDR_ADDRESS;
|
||||
do
|
||||
{
|
||||
hw_read32((uint32_t*)(rd_addr+mc_base_addr));
|
||||
rd_addr += 4;
|
||||
} while (rd_addr != MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX4SLBIOCR_ADDRESS);
|
||||
}
|
||||
|
||||
if (!phy_init_train)
|
||||
{
|
||||
hw_status("KAHALU_SIM_INIT: PROGRAMMING REGISTERS WITH TRAINED VALUES for FREQUENCY %0d\n",dram_frequency);
|
||||
phy_init_synps_lp4_reg_write(mc, dram_frequency);
|
||||
}
|
||||
else
|
||||
{
|
||||
hw_status("TRAININGS START\n");
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PIR_ADDRESS + mc_base_addr), 0x0012FE01);
|
||||
rd_data = 0;
|
||||
do
|
||||
{
|
||||
rd_data = hw_phy_read32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGSR0_ADDRESS + mc_base_addr));
|
||||
} while ((rd_data & 0x00000001) != 0x00000001);
|
||||
|
||||
hw_status("TRAININGS COMPLETE\n");
|
||||
if (rd_data & 0x7ffc0000)
|
||||
{
|
||||
hw_status("ERROR: PHY_INIT_TRAIN failed; PGSR0 = 0x%0x\n", rd_data);
|
||||
}
|
||||
}
|
||||
|
||||
if (dump_phy_regs) {
|
||||
hw_status("DUMPING ALL REGISTERS AFTER TRAINING\n");
|
||||
|
||||
rd_addr = MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_RIDR_ADDRESS;
|
||||
do
|
||||
{
|
||||
hw_read32((uint32_t*)(rd_addr+mc_base_addr));
|
||||
rd_addr += 4;
|
||||
} while (rd_addr != MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_DX4SLBIOCR_ADDRESS);
|
||||
}
|
||||
|
||||
hw_status("KAHALU_SIM_INIT: DISABLING PUB\n");
|
||||
hw_phy_write32((uint32_t*)(MCU_REGS_PHY_REGS_DWC_DDRPHY_PUB_PGCR1_ADDRESS + mc_base_addr), 0x02004600);
|
||||
hw_status("KAHALU_SIM_INIT: PHY INITIALIZATION COMPLETE\n");
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue