So kernel 64 can set up itself now. (Requires 1GB page size. But just for temporary setup, in the kernel we will still stick to 4KB page.)
This commit is contained in:
HyperAssembler
parent
57b0f4a8f1
commit
56375a5253
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@ -19,7 +19,11 @@ ata2: enabled=0
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ata3: enabled=0
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pci: enabled=1, chipset=i440fx
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vga: extension=vbe, update_freq=5
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cpu: count=1, ips=4000000, model=corei7_sandy_bridge_2600k, reset_on_triple_fault=1, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0
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cpu: count=1, ips=4000000, model=bx_generic, reset_on_triple_fault=1, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0
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cpuid: level=6, stepping=3, model=3, family=6, vendor_string="GenuineIntel", brand_string=" Intel(R) Pentium(R) 4 CPU "
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cpuid: mmx=1, apic=xapic, simd=sse2, sse4a=0, misaligned_sse=0, sep=1, movbe=0, adx=0
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cpuid: aes=0, sha=0, xsave=0, xsaveopt=0, x86_64=1, 1g_pages=1, pcid=0, fsgsbase=1
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cpuid: smep=0, smap=0, mwait=1, vmx=1
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print_timestamps: enabled=0
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port_e9_hack: enabled=0
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private_colormap: enabled=0
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@ -5,8 +5,8 @@ display_library: win32, options="gui_debug"
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memory: host=256, guest=256
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romimage: file="bochs/BIOS-bochs-latest"
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vgaromimage: file="bochs/VGABIOS-lgpl-latest"
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boot: cdrom
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magic_break: enabled=1
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floppy_bootsig_check: disabled=0
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# no floppya
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# no floppyb
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@ -20,12 +20,15 @@ ata2: enabled=0
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ata3: enabled=0
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pci: enabled=1, chipset=i440fx
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vga: extension=vbe, update_freq=5
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cpu: count=1, ips=4000000, model=corei7_sandy_bridge_2600k, reset_on_triple_fault=1, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0
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cpu: count=1, ips=4000000, model=bx_generic, reset_on_triple_fault=1, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0
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cpuid: level=6, stepping=3, model=3, family=6, vendor_string="GenuineIntel", brand_string=" Intel(R) Pentium(R) 4 CPU "
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cpuid: mmx=1, apic=xapic, simd=sse2, sse4a=0, misaligned_sse=0, sep=1, movbe=0, adx=0
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cpuid: aes=0, sha=0, xsave=0, xsaveopt=0, x86_64=1, 1g_pages=1, pcid=0, fsgsbase=1
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cpuid: smep=0, smap=0, mwait=1, vmx=1
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print_timestamps: enabled=0
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port_e9_hack: enabled=0
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private_colormap: enabled=0
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clock: sync=none, time0=local, rtc_sync=0
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magic_break: enabled=1
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# no cmosimage
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# no loader
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log: -
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@ -22,25 +22,25 @@ times 512 dq 0 ;reserved the rest for page entries
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GDT64: ; Global Descriptor Table (64-bit).
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.NULL: equ $ - GDT64 ; The null descriptor.
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; NULL
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 0 ; Access.
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db 0 ; Granularity.
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db 0 ; Base (high).
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.CODE: equ $ - GDT64 ; The code descriptor.
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SLCT_CODE equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10011000b ; Access.
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db 10011010b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.DATA: equ $ - GDT64 ; The data descriptor.
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SLCT_DATA equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10010000b ; Access.
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db 10010010b ; Access.
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db 00000000b ; Granularity.
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db 0 ; Base (high).
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.GDT64_PTR: ; The GDT-pointer.
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@ -54,9 +54,6 @@ mov eax, cr0 ; Set the A-register to control r
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and eax, 01111111111111111111111111111111b ; Clear the PG-bit, which is bit 31.
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mov cr0, eax ; Set control register 0 to the A-register.
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;pure magic
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xchg bx,bx
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; write values for pml4
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mov eax,PML4_BASE
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mov dword [eax], PDPT_BASE + 3
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@ -101,14 +98,14 @@ or eax, 1 << 31 ; Set the PG-bit, which is bit 31
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mov cr0, eax ; Set control register 0 to the A-register.
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; enter x64
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;lgdt [GDT64.GDT64_PTR]
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jmp GDT64.CODE:entry
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lgdt [GDT64.GDT64_PTR]
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jmp SLCT_CODE:entry
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[SECTION .text]
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[BITS 64]
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entry:
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cli
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mov ax,GDT64.DATA
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mov ax,SLCT_DATA
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mov ds,ax
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mov es,ax
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mov fs,ax
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@ -3,14 +3,31 @@
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#include "print.h"
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#include "mem.h"
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#include "multiboot.h"
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#include "../../../x86/src/c/print.h"
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uint8_t g_gdt[8*9];
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gdt_ptr_t g_gdt_ptr;
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extern uint64_t text_pos;
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extern void HLT_CPU(void);
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extern void BOCHS_MAGIC_BREAKPOINT();
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void HYPKERNEL64 hk_main(void)
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extern void HYPKERNEL64 HLT_CPU(void);
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extern void HYPKERNEL64 BOCHS_MAGIC_BREAKPOINT();
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extern void HYPKERNEL64 hk_flush_gdt(gdt_ptr_t* gdt_ptr, uint64_t code_slct, uint64_t data_slct);
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void HYPKERNEL64 hk_main(multiboot_info_t* multiboot_info)
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{
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hk_clear_screen();
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hk_printf("Welcome to HYP OS. Kernel is now running in x64 mode.\n");
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text_pos = 0;
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hk_printf("Kernel is now running in x64 mode. Multiboot info is located at %X.\n\n", (uint64_t)multiboot_info);
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hk_printf("*Setting up GDT...");
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hk_write_segment_descriptor((void*)&g_gdt[0], 0, 0, 0);
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hk_write_segment_descriptor((void*)&g_gdt[8], 0, 0, SEG_DPL_0 | SEG_CODE_DATA | SEG_PRESENT | SEG_LONG | SEG_TYPE_CODE_X);
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hk_write_segment_descriptor((void*)&g_gdt[16], 0, 0, SEG_DPL_0 | SEG_CODE_DATA | SEG_PRESENT | SEG_LONG | SEG_TYPE_DATA_RW);
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hk_write_segment_descriptor((void*)&g_gdt[24], 0, 0, SEG_DPL_3 | SEG_CODE_DATA | SEG_PRESENT | SEG_LONG | SEG_TYPE_CODE_X);
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hk_write_segment_descriptor((void*)&g_gdt[32], 0, 0, SEG_DPL_3 | SEG_CODE_DATA | SEG_PRESENT | SEG_LONG | SEG_TYPE_DATA_RW);
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hk_write_segment_descriptor((void*)&g_gdt[40], 0, 0xFFFFF, SEG_DPL_0 | SEG_GRANULARITY | SEG_CODE_DATA | SEG_PRESENT | SEG_32_BITS | SEG_TYPE_CODE_X);
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hk_write_segment_descriptor((void*)&g_gdt[48], 0, 0xFFFFF, SEG_DPL_0 | SEG_GRANULARITY | SEG_CODE_DATA | SEG_PRESENT | SEG_32_BITS | SEG_TYPE_DATA_RW);
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hk_write_segment_descriptor((void*)&g_gdt[56], 0, 0xFFFFF, SEG_DPL_3 | SEG_GRANULARITY | SEG_CODE_DATA | SEG_PRESENT | SEG_32_BITS | SEG_TYPE_CODE_X);
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hk_write_segment_descriptor((void*)&g_gdt[64], 0, 0xFFFFF, SEG_DPL_3 | SEG_GRANULARITY | SEG_CODE_DATA | SEG_PRESENT | SEG_32_BITS | SEG_TYPE_DATA_RW);
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g_gdt_ptr.base = (uint64_t)g_gdt;
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g_gdt_ptr.limit = 8*9-1;
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hk_flush_gdt(&g_gdt_ptr, SEG_SELECTOR(1, 0), SEG_SELECTOR(2, 0));
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hk_printf("Done.\n\n");
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HLT_CPU();
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}
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@ -59,7 +59,6 @@ hk_init_x64:
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push ebp
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mov ebp,esp
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cli
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xchg bx,bx
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mov edi,[ss:ebp+8] ;System V ABI
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jmp 0x100000 ;hard-coded
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mov esp,ebp
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