122 lines
2.8 KiB
C
122 lines
2.8 KiB
C
#include <arch/intr.h>
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#include <arch/mem.h>
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#include <arch/print.h>
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#include <kern/print.h>
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#include <kern/status.h>
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#include <kern/brute.h>
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#include "cpu.h"
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#define HAL_CORE_COUNT 1
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static uint8 cpu_idts[HAL_CORE_COUNT][IDT_ENTRY_NUM * IDT_ENTRY_SIZE];
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static struct hal_idt_ptr cpu_idt_ptrs[HAL_CORE_COUNT];
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static void *k_intr_disps[HAL_CORE_COUNT];
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int
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arch_raise_irql(ATTR_UNUSED int irql)
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{
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return 0;
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}
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int
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arch_lower_irql(ATTR_UNUSED int irql)
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{
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return 0;
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}
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int
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arch_get_irql()
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{
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return 0;
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}
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void
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hal_write_gate(void *gate, const uint64 offset, const uint32 selector, uint32 const attr)
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{
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((uint8 *) gate)[0] = (uint8) (offset & 0xFFu);
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((uint8 *) gate)[1] = (uint8) ((offset >> 8u) & 0xFFu);
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((uint8 *) gate)[2] = (uint8) (selector & 0xFFu);
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((uint8 *) gate)[3] = (uint8) ((selector >> 8u) & 0xFFu);
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((uint8 *) gate)[4] = (uint8) (attr & 0xFFu);
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((uint8 *) gate)[5] = (uint8) ((attr >> 8u) & 0xFFu);
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((uint8 *) gate)[6] = (uint8) ((offset >> 16u) & 0xFFu);
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((uint8 *) gate)[7] = (uint8) ((offset >> 24u) & 0xFFu);
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((uint8 *) gate)[8] = (uint8) ((offset >> 32u) & 0xFFu);
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((uint8 *) gate)[9] = (uint8) ((offset >> 40u) & 0xFFu);
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((uint8 *) gate)[10] = (uint8) ((offset >> 48u) & 0xFFu);
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((uint8 *) gate)[11] = (uint8) ((offset >> 56u) & 0xFFu);
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((uint8 *) gate)[12] = 0;
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((uint8 *) gate)[13] = 0;
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((uint8 *) gate)[14] = 0;
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((uint8 *) gate)[15] = 0;
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}
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void KABI
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hal_interrupt_dispatcher(uint64 int_vec, struct interrupt_context *context)
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{
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uint32 coreid = 0;
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if (k_intr_disps[coreid] == NULL) {
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kprintf("Unhandled interrupt %ld at 0x%lx.\n", int_vec, context->rip);
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}
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/*else
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{
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k_intr_disps[coreid]((uint32) int_vec, context);
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}*/
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}
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static void
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populate_idt(void)
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{
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}
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void
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arch_intr_init(void)
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{
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uint32 coreid;
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uint32 eax;
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uint32 ebx;
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uint32 ecx;
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uint32 edx;
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// detect APIC first
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eax = 1;
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arch_cpuid(&eax, &ebx, &ecx, &edx);
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if (!(edx & (1u << 9u))) {
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BRUTE("ERROR: APIC is not present.\n");
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}
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coreid = 0;
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// get idt ptr ready
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cpu_idt_ptrs[coreid].base = (uint64) &cpu_idts[coreid];
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cpu_idt_ptrs[coreid].limit = IDT_ENTRY_NUM * IDT_ENTRY_SIZE - 1;
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// clear dispatch table
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k_intr_disps[coreid] = NULL;
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// hook asm interrupt handlers
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populate_idt();
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arch_flush_idt(&cpu_idt_ptrs[coreid]);
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// disable PIC
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arch_write_port_8(0xa1, 0xff);
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arch_write_port_8(0x21, 0xff);
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uint64 apic_base_reg = 0;
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ATTR_UNUSED uint64 apic_base = 0;
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ecx = 0;
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arch_read_msr(&ecx, &edx, &eax);
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apic_base_reg = ((uint64) edx << 32u) + (uint64) eax;
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//apic_base = apic_base_reg & bit_field_mask(12, 35);
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// hardware enable APIC
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ecx = 0;
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// eax = (uint32) ((apic_base_reg & bit_field_mask(0, 31)) | (1 << 11));
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arch_write_msr(&ecx, &edx, &eax);
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}
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