334 lines
9.9 KiB
NASM
334 lines
9.9 KiB
NASM
; Copyright 2016 secXsQuared
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; Distributed under GPL license
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; See COPYING under root for details
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%include "hal/addr.inc"
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MULTIBOOT_TAG_ALIGNMENT equ 8
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MULTIBOOT_HEADER_ALIGNMENT equ 8
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MULTIBOOT_LOADED_MAGIC equ 0x36d76289
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MULTIBOOT_MAGIC_NUMBER equ 0xE85250D6
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MULTIBOOT_ARCH equ 0
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; NASM does not like
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MULTIBOOT_CHECK_SUM equ (0xFFFFFFFF - (MULTIBOOT_MAGIC_NUMBER + MULTIBOOT_HEADER_SIZE + MULTIBOOT_ARCH) + 1)
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MULTIBOOT_REQ_LOADERNAME equ 2
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MULTIBOOT_REQ_MMAP equ 6
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MULTIBOOT_REQ_EFI_64 equ 12
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MULTIBOOT_REQ_EFI_MMAP equ 17
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[SECTION .multiboot_header]
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[BITS 32]
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;====================
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;header tag
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align MULTIBOOT_HEADER_ALIGNMENT
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multiboot_header_tag:
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dd MULTIBOOT_MAGIC_NUMBER
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dd MULTIBOOT_ARCH
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dd MULTIBOOT_HEADER_SIZE
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dd MULTIBOOT_CHECK_SUM
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;====================
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;INFO_REQUEST_TAG
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align MULTIBOOT_TAG_ALIGNMENT
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multiboot_info_tag:
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dw 0x1 ; type=1
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dw 0x0 ; flag=0
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dd MULTIBOOT_INFO_TAG_SIZE
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dd MULTIBOOT_REQ_LOADERNAME
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dd MULTIBOOT_REQ_MMAP
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dd MULTIBOOT_REQ_EFI_64
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dd MULTIBOOT_REQ_EFI_MMAP
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MULTIBOOT_INFO_TAG_SIZE equ ($ - multiboot_info_tag)
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;====================
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;MODULE ALIGNMENT TAG
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align MULTIBOOT_TAG_ALIGNMENT
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dw 0x6; type=6
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dw 0x0; flag=0
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dd 0x8
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;====================
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;End_tag
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align MULTIBOOT_TAG_ALIGNMENT
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dw 0x0
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dw 0x0
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dd 0x8
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;====================
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MULTIBOOT_HEADER_SIZE equ ($ - multiboot_header_tag)
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[SECTION .text]
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[BITS 32]
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align 4096
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global hal_entry_32
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hal_entry_32:
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; close interrupt
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cli
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cld
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; check loaded by grub
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cmp eax,MULTIBOOT_LOADED_MAGIC
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je .loaded_by_grub
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hlt
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.loaded_by_grub:
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; set stack pointer
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mov esp, GET_PADDR(kernel_stack_end)
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; save multiboot_info*
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mov esi,ebx
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; check x64 support
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call halp_ensure_support_x64
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cmp eax,1
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je .init_x64
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hlt
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.init_x64:
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; disable paging first
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mov eax, cr0 ; Set the A-register to control register 0.
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and eax, 0x7FFFFFFF ; Clear the PG-bit, which is bit 31.
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mov cr0, eax ; Set control register 0 to the A-register.
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; for pages mapped here, attributes are always:
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; PRESENT - 1 << 0
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; RW - 1 << 1
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; RING0 - 0 << 2
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; Page Level Write Back - 0 << 3
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; Page Cache Enabled - 0 << 4
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; Not Accessed - 0 << 5
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; Not dirty - 0 << 6
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; No PAT - 0 << 7 (must be 0 for recursive)
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; Not Global - 0 << 8
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; Execution Enabled - 0 << 63
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; To summary - 3 + ADDR
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; since 4k aligned, we can just add the attribute
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PAGE_TABLE_ATTRIBUTE equ 0011b
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; need to map the PDE (1GB region) of the identity mapping + 2 * PTE (identity + vaddr)
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; also need to map the kernel itself to the VIRT_ADDR + PHYS_ADDR
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; calculate the Nth 2MB within the first 1GB
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mov eax, HAL_KERNEL_BASE_PADDR
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mov ecx, 1*1024*1024*1024;
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xor edx, edx
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div ecx ; we need the remainder here (EDX)
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mov eax, edx
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mov ecx, 2*1024*1024 ; 2MB
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xor edx, edx
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div ecx ; divide ecx:eax by ecx EAX = quotient, EDX = remainder, 0 in this case
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mov edx, eax
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; map the identity PDE
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mov eax, GET_PADDR(pde_base_kernel_static_identity)
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mov dword [eax + edx * 8], GET_PADDR(pte_base_kernel_static) + PAGE_TABLE_ATTRIBUTE
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; map the kernel static PDE
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mov eax, GET_PADDR(pde_base_kernel_static)
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; map the first 2MB of the last 1GB to kernel static pte
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mov dword [eax + edx * 8], GET_PADDR(pte_base_kernel_static) + PAGE_TABLE_ATTRIBUTE
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; map everything from the start of the kernel (0MB)
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mov eax, GET_PADDR(pte_base_kernel_static)
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mov edx, 0 ;512 times
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mov ecx, HAL_KERNEL_BASE_PADDR + PAGE_TABLE_ATTRIBUTE
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.pte_static_loop:
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mov dword [eax + edx * 8], ecx
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add ecx, 4096 ;4k per entry
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inc edx
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cmp edx, 512
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jne .pte_static_loop
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; enable PAE
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mov eax, cr4 ; Set the A-register to control register 4.
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or eax, 1 << 5 ; Set the PAE-bit, which is the 6th bit (bit 5).
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mov cr4, eax ; Set control register 4 to the A-register.
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; enable x86_64
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mov ecx, 0xC0000080 ; Set the C-register to 0xC0000080, which is the EFER MSR.
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rdmsr ; Read from the model-specific register.
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or eax, 1 << 8 ; Set the LM-bit which is the 9th bit (bit 8).
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wrmsr ; Write to the model-specific register.
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; let cr3 point at page table
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mov eax, GET_PADDR(pml4_base)
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mov cr3, eax
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; enable paging, enter compatibility mode
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mov eax, cr0 ; Set the A-register to control register 0.
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or eax, 1 << 31 ; Set the PG-bit, which is bit 31.
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mov cr0, eax ; Set control register 0 to the A-register.
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; enter x64
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lgdt [GET_PADDR(GDT64.GDT64_PTR)]
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jmp SLCT_CODE:GET_PADDR(halp_entry_64)
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hlt
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halp_ensure_support_x64:
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push ebp
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mov ebp,esp
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz .not_supported
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mov eax, 0x80000000 ; Set the A-register to 0x80000000.
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cpuid ; CPU identification.
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cmp eax, 0x80000001 ; Compare the A-register with 0x80000001.
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jb .not_supported ; It is less, there is no long mode.
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mov eax, 0x80000001 ; Set the A-register to 0x80000001.
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cpuid ; CPU identification.
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz .not_supported ; They aren't, there is no long mode.
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mov eax,1
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jmp .end
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.not_supported:
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xor eax,eax
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.end:
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mov esp,ebp
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pop ebp
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ret
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[SECTION .text]
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[BITS 64]
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extern hal_main
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halp_entry_64:
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; note that we are still at the identity mapping
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mov rax, .entry_64
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jmp rax
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.entry_64:
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mov ax,SLCT_DATA
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mov ds,ax
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mov es,ax
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mov fs,ax
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mov gs,ax
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mov ss,ax
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; set correct rsp to the new kernel stack vaddr, the top of which is the start of the kernel
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mov rsp, HAL_KERNEL_BASE_VADDR
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mov rdi, rsi ; multiboot_info*
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add rdi, HAL_KERNEL_BASE_VADDR
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call hal_main
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hlt
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[SECTION .data]
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[BITS 64]
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; we only map two sections: the last 512 GB for kernel and the second last 512 GB for
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; recursive page table. YA BOI GUZMA
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; 0xFFFF 8000 0000 0000 unmapped kernel
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; 0xFFFF FF00 0000 0000 512 GB Recursive page table (MAP THIS)
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; 0xFFFF FF80 0000 0000 510 GB Kernel Dynamic
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; inside dynamic, the lowest addr is for heap and the highest is for the stack
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; 0xFFFF FFFF 8000 0000 to 0xFFFF FFFF FFFF FFFF 2 GB Kernel static (MAP THIS)
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align 4096
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pml4_base:
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; 512 GB per entry, we need 4 ENTRIES, BUT ONE IS MAPPED TO ITSELF
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; within the first 512G (Definitely since grub does not load to more than 4G), identity map the kernel
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dq GET_PADDR(pdpt_base_identity) + PAGE_TABLE_ATTRIBUTE
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times 509 dq 0
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; 511th entry for 2nd last 512G
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dq GET_PADDR(pml4_base) + PAGE_TABLE_ATTRIBUTE
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; 512th entry for last 512G (kernel space)
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dq GET_PADDR(pdpt_base) + PAGE_TABLE_ATTRIBUTE
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align 4096
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; 1GB per entry
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pdpt_base:
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; this pdpt is for the pml4 last 512 GB entry
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; we need 3 ENTRIES, 1 for kernel and 2 for kernel dynamics (first 1GB heap + last 1GB stack)
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; map the 1st GB to kernel dynamic heap
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dq GET_PADDR(pde_base_kernel_dynamic_heap) + PAGE_TABLE_ATTRIBUTE
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times 508 dq 0
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; map the 510th GB to kernel dynamic stack
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dq GET_PADDR(pde_base_kernel_dynamic_stack) + PAGE_TABLE_ATTRIBUTE
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; map the 511th GB to kernel static space
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dq GET_PADDR(pde_base_kernel_static) + PAGE_TABLE_ATTRIBUTE
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; the 512th GB is unmapped
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dq 0
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pdpt_base_identity:
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; this pdpt is for the kernel identity mapping
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; the kernel is definitely loaded to the first 1GB
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dq GET_PADDR(pde_base_kernel_static_identity) + PAGE_TABLE_ATTRIBUTE
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times 511 dq 0
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align 4096
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; 2MB per entry
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pde_base_kernel_dynamic_heap:
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; this pde is for the kernel dynamic pdpt entry (kernel heap), we need 1 entry to map the initial 2M
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; map the first 2MB of the 510 GB to kernel heap
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dq GET_PADDR(pte_base_kernel_dynamic_heap) + PAGE_TABLE_ATTRIBUTE
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times 511 dq 0
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pde_base_kernel_dynamic_stack:
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; this pde is for the kernel dynamic pdpt entry (kernel stack), we need 1 entry to map the last 2M
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times 511 dq 0
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; map the last 2MB of the 510 GB to kernel stack
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dq GET_PADDR(pte_base_kernel_dynamic_stack) + PAGE_TABLE_ATTRIBUTE
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pde_base_kernel_static:
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; this pde is for the kernel static pdpt entry (kernel core), we need 1 entry to map the initial 2M
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; map the first 2MB of the last 1GB to kernel static pte
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times 512 dq 0
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pde_base_kernel_static_identity:
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; this pde is for the kernel static identity pdpt entry (kernel core), we need 1 entry to map the initial 2M
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times 512 dq 0
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align 4096
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; 4KB per entry
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pte_base_kernel_dynamic_heap:
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; this pte is for the kernel dynamic heap pde entry, we need 1 entry to map the kernel heap (4k)
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; map the heap segment (first 4k)
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dq GET_PADDR(kernel_heap) + PAGE_TABLE_ATTRIBUTE
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times 511 dq 0
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pte_base_kernel_dynamic_stack:
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; this pte is for the kernel dynamic stack pde entry, we need 1 entry to map the kernel stack (4k)
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times 511 dq 0
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; map the stack segment (last 4k)
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dq GET_PADDR(kernel_stack) + PAGE_TABLE_ATTRIBUTE
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pte_base_kernel_static:
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; this pte is for the kernel static pde entry, we need 512 entries, map the complete 1st 2MB (TODO: calculate kernel size)
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times 512 dq 0
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align 4096
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; long mode gdt
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GDT64: ; Global Descriptor Table (64-bit).
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; NULL
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 0 ; Access.
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db 0 ; Granularity.
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db 0 ; Base (high).
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SLCT_CODE equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10011010b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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SLCT_DATA equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10010010b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.GDT64_PTR: ; The GDT-pointer.
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dw $ - GDT64 - 1 ; Limit.
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dq GET_PADDR(GDT64) ; Base.
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align 4096
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kernel_stack:
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times 4096 db 0
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kernel_stack_end:
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align 4096
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kernel_heap:
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times 4096 db 0 |