2017-01-11 01:53:54 +00:00
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/*-
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* Copyright (c) 2017 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include <dev/mmc/bridge.h>
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2017-03-06 23:47:59 +00:00
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#include <dev/sdhci/sdhci.h>
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2017-01-11 01:53:54 +00:00
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#include "mmcbr_if.h"
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#include "sdhci_if.h"
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static const struct sdhci_acpi_device {
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const char* hid;
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int uid;
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const char *desc;
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u_int quirks;
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} sdhci_acpi_devices[] = {
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- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug [1]. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.
1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
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{ "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
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- Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)
Of these "partitions", only the enhanced user data area one actually
slices the user data area partition and, thus, gets handled with the
help of geom_flashmap(4). The other types of partitions have address
space independent from the default partition and need to be switched
to via CMD6 (SWITCH), i. e. constitute a set of additional "disks".
The second kind of these "partitions" doesn't fit that well into the
design of mmc(4) and mmcsd(4). I've decided to let mmcsd(4) hook all
of these "partitions" up as disk(9)'s (except for the RPMB partition
as it didn't seem to make much sense to be able to put a file-system
there and may require authentication; therefore, RPMB partitions are
solely accessible via the newly added IOCTL interface currently; see
also below). This approach for one resulted in cleaner code. Second,
it retains the notion of mmcsd(4) children corresponding to a single
physical device each. With the addition of some layering violations,
it also would have been possible for mmc(4) to add separate mmcsd(4)
instances with one disk each for all of these "partitions", however.
Still, both mmc(4) and mmcsd(4) share some common code now e. g. for
issuing CMD6, which has been factored out into mmc_subr.c.
Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.
CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.
- Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications. However, quite some work is
left to be done in this regard; all other R1B-type commands done by
the MMC layer also should be followed by a SEND_STATUS (CMD13), the
erase timeout calculations/handling as documented in specifications
are entirely ignored so far, the MMC layer doesn't provide timeouts
applicable up to the bridge drivers and at least sdhci(4) currently
is hardcoding 1 s as timeout for all command types unconditionally.
Let alone already available return codes often not being checked in
the MMC layer ...
- Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter will be added to ports as sysutils/mmc-utils in
a bit. Among others, the `mmc` tool of the GNU mmc-utils allows for
partitioning eMMC devices (tested working).
- For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.
- Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.
- In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC
controllers as such in order to match the PCI one.
Additionally, in the entry for the 80860F14 SDXC controller remove
the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.
OKed by: imp
Submitted by: ian (mmc_switch_status() implementation)
2017-03-16 22:23:04 +00:00
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug [1]. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.
1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
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{ "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller",
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o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug [1]. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.
1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
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{ "80860F16", 0, "Intel Bay Trail/Braswell SDXC Controller",
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o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug [1]. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.
1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
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{ "80865ACA", 0, "Intel Apollo Lake SDXC Controller",
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SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",
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SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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2018-09-29 00:35:36 +00:00
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{ "AMDI0040", 0, "AMD eMMC 5.0 Controller",
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SDHCI_QUIRK_32BIT_DMA_SIZE },
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2017-01-11 01:53:54 +00:00
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{ NULL, 0, NULL, 0}
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};
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static char *sdhci_ids[] = {
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"80860F14",
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"80860F16",
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- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug [1]. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.
1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
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"80865ACA",
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"80865ACC",
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2018-09-29 00:35:36 +00:00
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"AMDI0040",
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2017-01-11 01:53:54 +00:00
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NULL
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};
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struct sdhci_acpi_softc {
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u_int quirks; /* Chip specific quirks */
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struct resource *irq_res; /* IRQ resource */
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2017-01-29 00:05:49 +00:00
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void *intrhand; /* Interrupt handle */
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2017-01-11 01:53:54 +00:00
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struct sdhci_slot slot;
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struct resource *mem_res; /* Memory resource */
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};
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static void sdhci_acpi_intr(void *arg);
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static int sdhci_acpi_detach(device_t dev);
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static uint8_t
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused,
|
|
|
|
|
bus_size_t off)
|
2017-01-11 01:53:54 +00:00
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_barrier(sc->mem_res, 0, 0xFF,
|
|
|
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
|
|
|
return bus_read_1(sc->mem_res, off);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused,
|
|
|
|
|
bus_size_t off, uint8_t val)
|
2017-01-11 01:53:54 +00:00
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_barrier(sc->mem_res, 0, 0xFF,
|
|
|
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
|
|
|
bus_write_1(sc->mem_res, off, val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint16_t
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused,
|
|
|
|
|
bus_size_t off)
|
2017-01-11 01:53:54 +00:00
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_barrier(sc->mem_res, 0, 0xFF,
|
|
|
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
|
|
|
return bus_read_2(sc->mem_res, off);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused,
|
|
|
|
|
bus_size_t off, uint16_t val)
|
2017-01-11 01:53:54 +00:00
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_barrier(sc->mem_res, 0, 0xFF,
|
|
|
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
|
|
|
bus_write_2(sc->mem_res, off, val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused,
|
|
|
|
|
bus_size_t off)
|
2017-01-11 01:53:54 +00:00
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_barrier(sc->mem_res, 0, 0xFF,
|
|
|
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
|
|
|
return bus_read_4(sc->mem_res, off);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused,
|
|
|
|
|
bus_size_t off, uint32_t val)
|
2017-01-11 01:53:54 +00:00
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_barrier(sc->mem_res, 0, 0xFF,
|
|
|
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
|
|
|
bus_write_4(sc->mem_res, off, val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
|
2017-01-11 01:53:54 +00:00
|
|
|
bus_size_t off, uint32_t *data, bus_size_t count)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_read_multi_stream_4(sc->mem_res, off, data, count);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2017-03-17 22:57:37 +00:00
|
|
|
sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
|
2017-01-11 01:53:54 +00:00
|
|
|
bus_size_t off, uint32_t *data, bus_size_t count)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
bus_write_multi_stream_4(sc->mem_res, off, data, count);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct sdhci_acpi_device *
|
|
|
|
|
sdhci_acpi_find_device(device_t dev)
|
|
|
|
|
{
|
2018-10-26 00:05:46 +00:00
|
|
|
char *hid;
|
2017-01-11 01:53:54 +00:00
|
|
|
int i, uid;
|
|
|
|
|
ACPI_HANDLE handle;
|
|
|
|
|
ACPI_STATUS status;
|
2018-10-26 00:05:46 +00:00
|
|
|
int rv;
|
2017-01-11 01:53:54 +00:00
|
|
|
|
2018-10-26 00:05:46 +00:00
|
|
|
rv = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids, &hid);
|
|
|
|
|
if (rv > 0)
|
2017-01-11 01:53:54 +00:00
|
|
|
return (NULL);
|
|
|
|
|
|
|
|
|
|
handle = acpi_get_handle(dev);
|
|
|
|
|
status = acpi_GetInteger(handle, "_UID", &uid);
|
|
|
|
|
if (ACPI_FAILURE(status))
|
|
|
|
|
uid = 0;
|
|
|
|
|
|
|
|
|
|
for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) {
|
|
|
|
|
if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0)
|
|
|
|
|
continue;
|
|
|
|
|
if ((sdhci_acpi_devices[i].uid != 0) &&
|
|
|
|
|
(sdhci_acpi_devices[i].uid != uid))
|
|
|
|
|
continue;
|
2017-03-06 23:47:59 +00:00
|
|
|
return (&sdhci_acpi_devices[i]);
|
2017-01-11 01:53:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
sdhci_acpi_probe(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
const struct sdhci_acpi_device *acpi_dev;
|
|
|
|
|
|
|
|
|
|
acpi_dev = sdhci_acpi_find_device(dev);
|
|
|
|
|
if (acpi_dev == NULL)
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
|
|
device_set_desc(dev, acpi_dev->desc);
|
|
|
|
|
|
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
sdhci_acpi_attach(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
int rid, err;
|
|
|
|
|
const struct sdhci_acpi_device *acpi_dev;
|
|
|
|
|
|
|
|
|
|
acpi_dev = sdhci_acpi_find_device(dev);
|
|
|
|
|
if (acpi_dev == NULL)
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
|
|
sc->quirks = acpi_dev->quirks;
|
|
|
|
|
|
|
|
|
|
/* Allocate IRQ. */
|
|
|
|
|
rid = 0;
|
|
|
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
|
|
|
RF_ACTIVE);
|
|
|
|
|
if (sc->irq_res == NULL) {
|
|
|
|
|
device_printf(dev, "can't allocate IRQ\n");
|
|
|
|
|
return (ENOMEM);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
|
|
|
&rid, RF_ACTIVE);
|
|
|
|
|
if (sc->mem_res == NULL) {
|
|
|
|
|
device_printf(dev, "can't allocate memory resource for slot\n");
|
|
|
|
|
sdhci_acpi_detach(dev);
|
|
|
|
|
return (ENOMEM);
|
|
|
|
|
}
|
2017-01-29 00:05:49 +00:00
|
|
|
|
2018-05-14 21:46:06 +00:00
|
|
|
/*
|
|
|
|
|
* Intel Bay Trail and Braswell eMMC controllers share the same IDs,
|
|
|
|
|
* but while with these former DDR52 is affected by the VLI54 erratum,
|
|
|
|
|
* these latter require the timeout clock to be hardcoded to 1 MHz.
|
|
|
|
|
*/
|
- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail
and Braswell eMMC and SDXC controllers share the same IDs. Like in
the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ
quirk (see r311794 for the corresponding change to the sdhci(4) PCI
PCI front-end), though. However, due to the shared ACPI IDs, this
is trickier to do.
- Intel Apollo Lake eMMC and SDXC controllers are affected by the
APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May
Lead to Unpredictable System Behavior") silicon bug [1]. When this
erratum hits, typically both SDHCI and XHCI controllers wedge.
According to Intel, using ADMA2 with 64-bit addressing and 96-bit
descriptors serves as a workaround. Until such times when sdhci(4)
has ADMA2 support, flag DMA as broken for affected interfaces.
This turns out to work around the problem, too, at the cost of
performance.
- In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC
and SDXC controllers, too.
1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf
2017-05-14 21:33:01 +00:00
|
|
|
if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 &&
|
|
|
|
|
SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
|
|
|
|
|
SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807)
|
2018-05-14 21:46:06 +00:00
|
|
|
sc->quirks |= SDHCI_QUIRK_MMC_DDR52 |
|
|
|
|
|
SDHCI_QUIRK_DATA_TIMEOUT_1MHZ;
|
o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
|
|
|
sc->quirks &= ~sdhci_quirk_clear;
|
|
|
|
|
sc->quirks |= sdhci_quirk_set;
|
2017-01-11 01:53:54 +00:00
|
|
|
sc->slot.quirks = sc->quirks;
|
|
|
|
|
|
|
|
|
|
err = sdhci_init_slot(dev, &sc->slot, 0);
|
|
|
|
|
if (err) {
|
|
|
|
|
device_printf(dev, "failed to init slot\n");
|
|
|
|
|
sdhci_acpi_detach(dev);
|
|
|
|
|
return (err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Activate the interrupt */
|
|
|
|
|
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
|
|
|
NULL, sdhci_acpi_intr, sc, &sc->intrhand);
|
|
|
|
|
if (err) {
|
|
|
|
|
device_printf(dev, "can't setup IRQ\n");
|
|
|
|
|
sdhci_acpi_detach(dev);
|
|
|
|
|
return (err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Process cards detection. */
|
|
|
|
|
sdhci_start_slot(&sc->slot);
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
sdhci_acpi_detach(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
|
|
if (sc->intrhand)
|
|
|
|
|
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
|
|
|
|
if (sc->irq_res)
|
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
|
|
|
rman_get_rid(sc->irq_res), sc->irq_res);
|
|
|
|
|
|
|
|
|
|
if (sc->mem_res) {
|
|
|
|
|
sdhci_cleanup_slot(&sc->slot);
|
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
|
|
|
rman_get_rid(sc->mem_res), sc->mem_res);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
sdhci_acpi_shutdown(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
sdhci_acpi_suspend(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = bus_generic_suspend(dev);
|
|
|
|
|
if (err)
|
|
|
|
|
return (err);
|
|
|
|
|
sdhci_generic_suspend(&sc->slot);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
sdhci_acpi_resume(device_t dev)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = device_get_softc(dev);
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
sdhci_generic_resume(&sc->slot);
|
|
|
|
|
err = bus_generic_resume(dev);
|
|
|
|
|
if (err)
|
|
|
|
|
return (err);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
sdhci_acpi_intr(void *arg)
|
|
|
|
|
{
|
|
|
|
|
struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg;
|
|
|
|
|
|
|
|
|
|
sdhci_generic_intr(&sc->slot);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static device_method_t sdhci_methods[] = {
|
|
|
|
|
/* device_if */
|
|
|
|
|
DEVMETHOD(device_probe, sdhci_acpi_probe),
|
|
|
|
|
DEVMETHOD(device_attach, sdhci_acpi_attach),
|
|
|
|
|
DEVMETHOD(device_detach, sdhci_acpi_detach),
|
|
|
|
|
DEVMETHOD(device_shutdown, sdhci_acpi_shutdown),
|
|
|
|
|
DEVMETHOD(device_suspend, sdhci_acpi_suspend),
|
|
|
|
|
DEVMETHOD(device_resume, sdhci_acpi_resume),
|
|
|
|
|
|
|
|
|
|
/* Bus interface */
|
|
|
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
|
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
|
|
|
|
|
|
|
|
/* mmcbr_if */
|
2017-01-29 00:05:49 +00:00
|
|
|
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
|
|
|
DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
|
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of:
- Correcting and extending the infrastructure for negotiating and
enabling post-DDR52 modes already added as part of r315598. In
fact, HS400ES now should work as well but hasn't been activated
due to lack of corresponding hardware.
- Adding support executing standard SDHCI initial tuning as well
as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I
SD card modes. Currently, corresponding methods are only hooked
up to the ACPI and PCI front-ends of sdhci(4), though. Moreover,
sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD
layer in order to not break operations with other sdhci(4) front-
ends. Likewise, sdhci(4) now no longer offers modes requiring the
set_uhs_timing method introduced in r315598 to be implemented/
hooked up (previously, this method was used with DDR52 only, which
in turn is only available with Intel controllers so far, i. e. no
such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ
support and the switch_vccq method.
- Addition of locking to the IOCTL half of mmcsd(4) to prevent races
with detachment and suspension, especially since it's required to
immediately switch away from RPMB partitions again after an access
to these (so re-tuning can take place anew, given that the current
eMMC specification v5.1 doesn't allow tuning commands to be issued
with a RPMB partition selected). Therefore, the existing part_mtx
lock in the mmcsd(4) softc is additionally renamed to disk_mtx in
order to denote that it only refers to the disk(9) half, likewise
for corresponding macros.
On the system where the addition of DDR52 support increased the read
throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
quadrupled compared to pre-r315598.
Also, with the advent of (re-)tuning support, most infrastructure
necessary for SD card UHS-I modes up to SDR104 now is also in place.
Note, though, that the standard SDHCI way of (re-)tuning is special
in several ways, which also is why sending the actual tuning requests
to the device is part of sdhci(4). SDHCI implementations not following
the specification, MMC and non-SDHCI SD card controllers likely will
use a generic implementation in the MMC/SD layer for executing tuning,
which hasn't been written so far, though.
However, in fact this isn't a feature-only change; there are boards
based on Intel Bay Trail where DDR52 is problematic and the suggested
workaround is to use HS200 mode instead. So far exact details are
unknown, however, i. e. whether that's due to a defect in these SoCs
or on the boards.
Moreover, due to the above changes requiring to be aware of possible
MMC siblings in the fast path of mmc(4), corresponding information
now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now
all are guaranteed to operate on the same set of devices as there no
longer is any use of device_get_children(9), which can fail in low
memory situations. Likewise, mmc_calculate_clock() now longer will
trigger a panic due to the latter.
o Fix a bug in the failure reporting of mmcsd_delete(); in case of an
error when the starting block of a previously stored erase request
is used (in order to be able to erase a full erase sector worth of
data), the starting block of the newly supplied bio_pblkno has to be
returned for indicating no progress. Otherwise, upper layers might
be told that a negative number of BIOs have been completed, leading
to a panic.
o Fix 2 bugs on resume:
- Things done in fork1(9) like the acquisition of an SX lock or the
sleepable memory allocation are incompatible with a MTX_DEF taken.
Thus, mmcsd_resume() must not call kproc_create(9), which in turn
uses fork1(9), with the disk_mtx (formerly part_mtx) held.
- In mmc_suspend(), the bus is powered down, which in the typical
case of a device being selected at the time of suspension, causes
the device deselection as part of the bus acquisition by mmc(4) in
mmc_scan() to fail as the bus isn't powered up again before later
in mmc_go_discovery(). Thus, power down with the bus acquired in
mmc_suspend(), which will trigger the deselection up-front.
o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]
o Fix missing variable initialization in mmc_switch_status(). [2]
o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]
o Handle the case of device_add_child(9) failing, for example due to
a memory shortage, gracefully in mmc(4) and sdhci(4), including not
leaking memory for the instance variables in case of mmc(4) (which
might or might not fix [4] as the latter problem has been discovered
independently).
o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
gracefully instead of calling panic(9).
o Again, check and handle the return values of some additional function
calls in mmc(4) instead of assuming that everything went right or mark
non-fatal errors by casting the return value to void.
o Correct a typo in the Linux IOCTL compatibility; it should have been
MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.
o Now that we are reaching ever faster speeds (more improvement in this
regard is to be expected when adding ADMA support to sdhci(4)), apply
a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging
to be off or caching erase sector and maximum data sizes as well support
of block addressing in mmsd(4) (instead of doing 2 indirections on every
read/write request for determining the maximum data size for example).
Reported by: Coverity
CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]
2017-07-23 16:11:47 +00:00
|
|
|
DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
|
|
|
|
|
DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
|
2017-01-29 00:05:49 +00:00
|
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
|
|
|
DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
|
2017-01-11 01:53:54 +00:00
|
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
|
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
|
|
|
|
o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
|
|
|
/* SDHCI accessors */
|
2017-01-11 01:53:54 +00:00
|
|
|
DEVMETHOD(sdhci_read_1, sdhci_acpi_read_1),
|
|
|
|
|
DEVMETHOD(sdhci_read_2, sdhci_acpi_read_2),
|
|
|
|
|
DEVMETHOD(sdhci_read_4, sdhci_acpi_read_4),
|
|
|
|
|
DEVMETHOD(sdhci_read_multi_4, sdhci_acpi_read_multi_4),
|
|
|
|
|
DEVMETHOD(sdhci_write_1, sdhci_acpi_write_1),
|
|
|
|
|
DEVMETHOD(sdhci_write_2, sdhci_acpi_write_2),
|
|
|
|
|
DEVMETHOD(sdhci_write_4, sdhci_acpi_write_4),
|
|
|
|
|
DEVMETHOD(sdhci_write_multi_4, sdhci_acpi_write_multi_4),
|
o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
2017-03-19 23:27:17 +00:00
|
|
|
DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
|
2017-01-11 01:53:54 +00:00
|
|
|
|
|
|
|
|
DEVMETHOD_END
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static driver_t sdhci_acpi_driver = {
|
|
|
|
|
"sdhci_acpi",
|
|
|
|
|
sdhci_methods,
|
|
|
|
|
sizeof(struct sdhci_acpi_softc),
|
|
|
|
|
};
|
|
|
|
|
static devclass_t sdhci_acpi_devclass;
|
|
|
|
|
|
|
|
|
|
DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, sdhci_acpi_devclass, NULL,
|
|
|
|
|
NULL);
|
|
|
|
|
MODULE_DEPEND(sdhci_acpi, sdhci, 1, 1, 1);
|
2017-07-09 16:57:24 +00:00
|
|
|
|
|
|
|
|
#ifndef MMCCAM
|
2017-03-07 22:42:44 +00:00
|
|
|
MMC_DECLARE_BRIDGE(sdhci_acpi);
|
2017-07-09 16:57:24 +00:00
|
|
|
#endif
|
