132 lines
3.4 KiB
ArmAsm
132 lines
3.4 KiB
ArmAsm
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/*-
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* Copyright (C) 2012 Margarida Gouveia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <machine/bat.h>
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/*
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* When we are invoked from Wii loaders, the state of the MMU and the BAT
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* mappings can vary. In this file we try to reset the MMU to a state
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* that lets us boot FreeBSD.
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*
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* N.B.: keep the BAT0 in sync with mmu_oea.c and never touch BAT1 later.
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*
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* This file is being included from aim/locore32.S.
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*/
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#define MMU_REALMODE() \
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mfmsr %r12; \
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rlwinm %r12, %r12, 0, ~(PSL_DR|PSL_IR);\
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sync; \
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bl 1f; \
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1: \
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mflr %r11; \
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clrlwi %r11, %r11, 3; /* XXX why? */ \
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addi %r11, %r11, 2f - 1b; \
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mtsrr0 %r11; \
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mtsrr1 %r12; /* Disables the MMU */ \
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isync; \
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rfi; \
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2:
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#define MMU_VIRTUALMODE() \
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bl 3f; \
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3: \
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mflr %r11; \
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addi %r11, %r11, 4f - 3b; \
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mfmsr %r12; \
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ori %r12, %r12, PSL_DR|PSL_IR; \
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mtsrr0 %r11; \
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mtsrr1 %r12; /* Enables the MMU */ \
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isync; \
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rfi; \
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4:
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MMU_REALMODE()
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/* Reset standard BATs */
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li %r11, 0
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mtibatu 0, %r11
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mtibatl 0, %r11
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mtdbatu 0, %r11
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mtdbatl 0, %r11
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mtibatu 1, %r11
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mtibatl 1, %r11
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mtdbatu 1, %r11
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mtdbatl 1, %r11
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mtibatu 2, %r11
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mtibatl 2, %r11
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mtdbatu 2, %r11
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mtdbatl 2, %r11
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mtibatu 3, %r11
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mtibatl 3, %r11
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mtdbatu 3, %r11
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mtdbatl 3, %r11
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/* Reset high BATs. IBAT[4-7][UL] + DBAT[4-7][UL] */
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mtspr 560, %r11
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mtspr 561, %r11
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mtspr 562, %r11
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mtspr 563, %r11
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mtspr 564, %r11
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mtspr 565, %r11
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mtspr 566, %r11
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mtspr 567, %r11
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mtspr 568, %r11
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mtspr 569, %r11
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mtspr 570, %r11
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mtspr 571, %r11
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mtspr 572, %r11
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mtspr 573, %r11
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mtspr 574, %r11
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mtspr 575, %r11
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/*
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* We need to setup BAT0 as in mmu_oea.c.
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*/
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li %r11, BATU(0x00000000, BAT_BL_256M, BAT_Vs)
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li %r12, BATL(0x00000000, BAT_M, BAT_PP_RW)
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mtdbatu 0, %r11
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mtdbatl 0, %r12
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mtibatu 0, %r11
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mtibatl 0, %r12
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isync
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/*
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* We use BAT1 to be able to write I/O memory, including the
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* framebuffer registers.
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*/
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/* BATU(0x0c000000, BAT_BL_32M, BAT_Vs) */
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lis %r11, 0x0c00
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ori %r11, %r11, BAT_BL_32M|BAT_Vs
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/* BATL(0x0c000000, BAT_I|BAT_G, BAT_PP_RW) */
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lis %r12, 0x0c00
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ori %r12, %r12, BAT_I|BAT_G|BAT_PP_RW
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mtdbatu 1, %r11
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mtdbatl 1, %r12
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isync
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MMU_VIRTUALMODE()
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