2013-03-20 15:39:27 +00:00
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/*
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* This file was generated automatically from PDF file by mkiomuxreg_imx51.rb
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*
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*/
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/*-
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2013-05-08 09:42:50 +00:00
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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2013-03-20 15:39:27 +00:00
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* All rights reserved.
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*
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* Portions of this software were developed by Oleksandr Rybalko
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IMX51_IOMUXREG_H
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#define _IMX51_IOMUXREG_H
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#define IOMUXC_MUX_CTL 0x001c /* multiplex control */
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#define IOMUX_CONFIG_SION (1 << 4)
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#define IOMUX_CONFIG_ALT0 (0)
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#define IOMUX_CONFIG_ALT1 (1)
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#define IOMUX_CONFIG_ALT2 (2)
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#define IOMUX_CONFIG_ALT3 (3)
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#define IOMUX_CONFIG_ALT4 (4)
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#define IOMUX_CONFIG_ALT5 (5)
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#define IOMUX_CONFIG_ALT6 (6)
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#define IOMUX_CONFIG_ALT7 (7)
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#define IOMUXC_PAD_CTL 0x03f0 /* pad control */
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#define PAD_CTL_HVE (1 << 13)
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#define PAD_CTL_DDR_INPUT (1 << 9)
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#define PAD_CTL_HYS (1 << 8)
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#define PAD_CTL_PKE (1 << 7)
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#define PAD_CTL_PUE (1 << 6)
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#define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE)
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#define PAD_CTL_KEEPER (PAD_CTL_PKE|0)
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#define PAD_CTL_PUS_100K_PD (0x0 << 4)
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#define PAD_CTL_PUS_47K_PU (0x1 << 4)
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#define PAD_CTL_PUS_100K_PU (0x2 << 4)
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#define PAD_CTL_PUS_22K_PU (0x3 << 4)
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#define PAD_CTL_ODE (1 << 3) /* opendrain */
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#define PAD_CTL_DSE_LOW (0x0 << 1)
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#define PAD_CTL_DSE_MID (0x1 << 1)
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#define PAD_CTL_DSE_HIGH (0x2 << 1)
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#define PAD_CTL_DSE_MAX (0x3 << 1)
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#define PAD_CTL_SRE (1 << 0)
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#define IOMUXC_INPUT_CTL 0x08c4 /* input control */
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#define INPUT_DAISY_0 0
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#define INPUT_DAISY_1 1
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#define INPUT_DAISY_2 2
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#define INPUT_DAISY_3 3
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#define INPUT_DAISY_4 4
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#define INPUT_DAISY_5 5
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#define INPUT_DAISY_6 6
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#define INPUT_DAISY_7 7
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/*
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* IOMUX index
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*/
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#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff)
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#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff)
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#define IOMUX_PIN(mux_adr, pad_adr) \
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(((mux_adr) << 16) | (((pad_adr) << 0)))
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#define IOMUX_MUX_NONE 0xffff
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#define IOMUX_PAD_NONE 0xffff
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/* register offset address */
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#define IOMUXC_GPR0 0x0000
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#define IOMUXC_GPR1 0x0004
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#define IOMUXC_OBSERVE_MUX_0 0x0008
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#define IOMUXC_OBSERVE_MUX_1 0x000c
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#define IOMUXC_OBSERVE_MUX_2 0x0010
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#define IOMUXC_OBSERVE_MUX_3 0x0014
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#define IOMUXC_OBSERVE_MUX_4 0x0018
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x001c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x0020
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x0024
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x0028
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x002c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x0030
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x0034
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x0038
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x003c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x0040
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x0044
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x0048
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x004c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x0050
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x0054
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x0058
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 0x005c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 0x0060
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 0x0064
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 0x0068
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 0x006c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 0x0070
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 0x0074
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 0x0078
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 0x007c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 0x0080
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 0x0084
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 0x0088
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 0x008c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 0x0090
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 0x0094
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 0x0098
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 0x009c
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 0x00a0
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 0x00a4
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 0x00a8
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 0x00ac
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 0x00b0
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 0x00b4
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 0x00b8
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 0x00bc
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 0x00c0
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A26 0x00c4
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_A27 0x00c8
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x00cc
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x00d0
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 0x00d4
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 0x00d8
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x00dc
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x00e0
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x00e4
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 0x00e8
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3 0x00ec
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4 0x00f0
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5 0x00f4
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK 0x00f8
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x00fc
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#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE 0x0100
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#define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1 0x0104
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B 0x0108
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B 0x010c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE 0x0110
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE 0x0114
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B 0x0118
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 0x011c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 0x0120
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 0x0124
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 0x0128
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND 0x012c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 0x0130
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 0x0134
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 0x0138
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 0x013c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 0x0140
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 0x0144
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 0x0148
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 0x014c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT 0x0150
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 0x0154
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 0x0158
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 0x015c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 0x0160
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 0x0164
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 0x0168
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 0x016c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 0x0170
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 0x0174
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 0x0178
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 0x017c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 0x0180
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 0x0184
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 0x0188
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 0x018c
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#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 0x0190
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8 0x0194
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9 0x0198
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10 0x019c
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11 0x01a0
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12 0x01a4
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13 0x01a8
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14 0x01ac
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15 0x01b0
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16 0x01b4
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17 0x01b8
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18 0x01bc
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19 0x01c0
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC 0x01c4
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#define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC 0x01c8
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12 0x01cc
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13 0x01d0
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14 0x01d4
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15 0x01d8
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16 0x01dc
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17 0x01e0
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18 0x01e4
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19 0x01e8
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC 0x01ec
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC 0x01f0
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#define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK 0x01f4
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#define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK 0x01f8
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#define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT 0x01fc
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#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD 0x0200
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#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD 0x0204
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#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK 0x0208
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#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS 0x020c
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#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI 0x0210
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#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO 0x0214
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#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0 0x0218
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#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1 0x021c
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#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY 0x0220
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#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK 0x0224
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#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x0228
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#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x022c
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#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS 0x0230
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#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS 0x0234
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#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD 0x0238
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#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD 0x023c
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#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD 0x0240
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#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD 0x0244
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#define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE 0x0248
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x024c
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x0250
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0254
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x0258
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x025c
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0260
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0264
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0268
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x026c
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#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 0x0270
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#define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B 0x0274
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK 0x0278
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR 0x027c
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP 0x0280
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT 0x0284
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0 0x0288
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1 0x028c
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2 0x0290
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3 0x0294
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4 0x0298
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5 0x029c
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6 0x02a0
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#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7 0x02a4
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11 0x02a8
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12 0x02ac
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13 0x02b0
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS 0x02b4
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS 0x02b8
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#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN 0x02bc
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#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO 0x02c0
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#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK 0x02c4
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#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS 0x02c8
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0 0x02cc
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1 0x02d0
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2 0x02d4
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3 0x02d8
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4 0x02dc
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5 0x02e0
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6 0x02e4
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7 0x02e8
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8 0x02ec
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9 0x02f0
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10 0x02f4
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11 0x02f8
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12 0x02fc
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13 0x0300
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14 0x0304
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15 0x0308
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16 0x030c
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17 0x0310
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18 0x0314
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19 0x0318
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20 0x031c
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21 0x0320
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22 0x0324
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#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23 0x0328
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3 0x032c
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#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2 0x0330
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#define IOMUXC_SW_MUX_CTL_PAD_DI_GP1 0x0334
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#define IOMUXC_SW_MUX_CTL_PAD_DI_GP2 0x0338
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#define IOMUXC_SW_MUX_CTL_PAD_DI_GP3 0x033c
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#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4 0x0340
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#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2 0x0344
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#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3 0x0348
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#define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK 0x034c
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#define IOMUXC_SW_MUX_CTL_PAD_DI_GP4 0x0350
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0 0x0354
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1 0x0358
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2 0x035c
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3 0x0360
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4 0x0364
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5 0x0368
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6 0x036c
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7 0x0370
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8 0x0374
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9 0x0378
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10 0x037c
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11 0x0380
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12 0x0384
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13 0x0388
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14 0x038c
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#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15 0x0390
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#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x0394
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#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x0398
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#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x039c
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#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x03a0
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#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x03a4
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#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x03a8
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0 0x03ac
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1 0x03b0
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#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x03b4
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#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x03b8
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#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x03bc
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#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x03c0
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#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x03c4
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#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x03c8
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2 0x03cc
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3 0x03d0
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#define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ 0x03d4
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4 0x03d8
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5 0x03dc
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6 0x03e0
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7 0x03e4
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8 0x03e8
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#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9 0x03ec
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 0x03f0
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 0x03f4
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 0x03f8
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 0x03fc
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 0x0400
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 0x0404
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 0x0408
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 0x040c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 0x0410
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 0x0414
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 0x0418
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 0x041c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 0x0420
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 0x0424
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 0x0428
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 0x042c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 0x0430
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 0x0434
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 0x0438
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 0x043c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 0x0440
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 0x0444
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 0x0448
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 0x044c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 0x0450
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 0x0454
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A26 0x0458
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_A27 0x045c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 0x0460
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 0x0464
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 0x0468
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 0x046c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE 0x0470
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 0x0474
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 0x0478
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 0x047c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3 0x0480
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4 0x0484
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5 0x0488
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK 0x048c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT 0x0490
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA 0x0494
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0498
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x049c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE 0x04a0
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x04a4
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x04a8
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE 0x04ac
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x04b0
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x04b4
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK 0x04b8
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x04bc
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x04c0
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x04c4
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x04c8
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 0x04cc
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 0x04d0
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x04d4
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x04d8
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x04dc
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x04e0
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B 0x04e4
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B 0x04e8
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE 0x04ec
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE 0x04f0
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B 0x04f4
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 0x04f8
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 0x04fc
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 0x0500
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 0x0504
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 0x0508
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 0x050c
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#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 0x0510
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND 0x0514
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 0x0518
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 0x051c
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 0x0520
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 0x0524
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 0x0528
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 0x052c
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 0x0530
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 0x0534
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT 0x0538
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 0x053c
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 0x0540
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 0x0544
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 0x0548
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 0x054c
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 0x0550
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 0x0554
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 0x0558
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 0x055c
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 0x0560
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 0x0564
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 0x0568
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 0x056c
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 0x0570
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 0x0574
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#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 0x0578
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8 0x057c
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9 0x0580
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10 0x0584
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11 0x0588
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12 0x058c
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13 0x0590
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14 0x0594
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15 0x0598
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16 0x059c
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17 0x05a0
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18 0x05a4
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19 0x05a8
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC 0x05ac
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC 0x05b0
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK 0x05b4
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#define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK 0x05b8
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12 0x05bc
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13 0x05c0
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14 0x05c4
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15 0x05c8
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16 0x05cc
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17 0x05d0
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18 0x05d4
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19 0x05d8
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC 0x05dc
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC 0x05e0
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#define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK 0x05e4
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#define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK 0x05e8
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#define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT 0x05ec
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#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD 0x05f0
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#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD 0x05f4
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#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK 0x05f8
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#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS 0x05fc
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#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI 0x0600
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#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO 0x0604
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#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 0x0608
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#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 0x060c
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#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY 0x0610
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#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK 0x0614
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#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x0618
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#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x061c
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#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS 0x0620
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#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS 0x0624
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#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD 0x0628
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#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD 0x062c
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#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD 0x0630
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#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD 0x0634
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#define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE 0x0638
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x063c
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x0640
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x0644
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x0648
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x064c
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x0650
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x0654
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x0658
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x065c
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#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 0x0660
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#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0664
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#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x0668
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#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x066c
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#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x0670
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#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0674
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK 0x0678
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR 0x067c
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP 0x0680
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT 0x0684
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0 0x0688
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1 0x068c
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2 0x0690
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3 0x0694
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4 0x0698
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5 0x069c
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6 0x06a0
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#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7 0x06a4
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 0x06a8
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12 0x06ac
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13 0x06b0
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS 0x06b4
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS 0x06b8
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#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN 0x06bc
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#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO 0x06c0
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#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK 0x06c4
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#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS 0x06c8
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0 0x06cc
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1 0x06d0
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2 0x06d4
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3 0x06d8
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4 0x06dc
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5 0x06e0
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6 0x06e4
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7 0x06e8
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8 0x06ec
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9 0x06f0
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10 0x06f4
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11 0x06f8
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12 0x06fc
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13 0x0700
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14 0x0704
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15 0x0708
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16 0x070c
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17 0x0710
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18 0x0714
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19 0x0718
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20 0x071c
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21 0x0720
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22 0x0724
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#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23 0x0728
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3 0x072c
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK 0x0730
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2 0x0734
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#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15 0x0738
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#define IOMUXC_SW_PAD_CTL_PAD_DI_GP1 0x073c
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#define IOMUXC_SW_PAD_CTL_PAD_DI_GP2 0x0740
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#define IOMUXC_SW_PAD_CTL_PAD_DI_GP3 0x0744
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#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4 0x0748
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#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2 0x074c
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#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3 0x0750
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#define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK 0x0754
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#define IOMUXC_SW_PAD_CTL_PAD_DI_GP4 0x0758
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0 0x075c
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1 0x0760
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2 0x0764
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3 0x0768
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4 0x076c
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5 0x0770
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6 0x0774
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7 0x0778
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8 0x077c
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9 0x0780
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10 0x0784
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11 0x0788
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12 0x078c
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13 0x0790
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14 0x0794
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#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15 0x0798
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#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x079c
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#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x07a0
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#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x07a4
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#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x07a8
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#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x07ac
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#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x07b0
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0 0x07b4
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1 0x07b8
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#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x07bc
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#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x07c0
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#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x07c4
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#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x07c8
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#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x07cc
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#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x07d0
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2 0x07d4
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3 0x07d8
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#define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B 0x07dc
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#define IOMUXC_SW_PAD_CTL_PAD_POR_B 0x07e0
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#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x07e4
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#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x07e8
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#define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY 0x07ec
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#define IOMUXC_SW_PAD_CTL_PAD_CKIL 0x07f0
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#define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ 0x07f4
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#define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ 0x07f8
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#define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ 0x07fc
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#define IOMUXC_SW_PAD_CTL_PAD_CLK_SS 0x0800
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4 0x0804
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5 0x0808
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6 0x080c
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7 0x0810
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8 0x0814
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#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9 0x0818
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#define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0 0x081c
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#define IOMUXC_SW_PAD_CTL_GRP_DDRPKS 0x0820
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1 0x0824
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#define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0 0x0828
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 0x082c
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#define IOMUXC_SW_PAD_CTL_GRP_INDDR 0x0830
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2 0x0834
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#define IOMUXC_SW_PAD_CTL_GRP_PKEDDR 0x0838
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#define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 0x083c
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#define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0 0x0840
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3 0x0844
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#define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 0x0848
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#define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS 0x084c
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4 0x0850
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#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5 0x0854
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#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6 0x0858
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#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 0x085c
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#define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0 0x0860
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#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 0x0864
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#define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0 0x0868
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#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 0x086c
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#define IOMUXC_SW_PAD_CTL_GRP_HVDDR 0x0870
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#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 0x0874
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 0x0878
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#define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS 0x087c
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 0x0880
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#define IOMUXC_SW_PAD_CTL_GRP_DDRPUS 0x0884
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1 0x0888
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 0x088c
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#define IOMUXC_SW_PAD_CTL_GRP_PKEADDR 0x0890
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2 0x0894
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3 0x0898
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 0x089c
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#define IOMUXC_SW_PAD_CTL_GRP_INMODE1 0x08a0
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 0x08a4
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#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4 0x08a8
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 0x08ac
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#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 0x08b0
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#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5 0x08b4
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#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 0x08b8
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#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 0x08bc
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#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6 0x08c0
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#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 0x08c4
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#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 0x08c8
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#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 0x08cc
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#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 0x08d0
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#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT 0x08d4
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#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT 0x08d8
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#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT 0x08dc
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#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT 0x08e0
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#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT 0x08e4
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#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT 0x08e8
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#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT 0x08ec
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#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT 0x08f0
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#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT 0x08f4
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#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT 0x08f8
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#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT 0x08fc
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#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT 0x0900
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#define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT 0x0904
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#define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT 0x0908
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#define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT 0x090c
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#define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT 0x0910
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#define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT 0x0914
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#define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT 0x0918
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#define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT 0x091c
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#define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT 0x0920
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#define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT 0x0924
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#define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT 0x0928
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#define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT 0x092c
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#define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT 0x0930
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#define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT 0x0934
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#define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT 0x0938
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#define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT 0x093c
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#define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT 0x0940
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#define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT 0x0944
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#define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT 0x0948
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#define IOMUXC_FEC_FEC_COL_SELECT_INPUT 0x094c
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#define IOMUXC_FEC_FEC_CRS_SELECT_INPUT 0x0950
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#define IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0x0954
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#define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT 0x0958
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#define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT 0x095c
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#define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT 0x0960
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#define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT 0x0964
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#define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 0x0968
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#define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 0x096c
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#define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 0x0970
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#define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 0x0974
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#define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT 0x0978
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#define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT 0x097c
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#define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT 0x0980
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#define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT 0x0984
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#define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT 0x0988
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#define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT 0x098c
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#define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT 0x0990
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#define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT 0x0994
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#define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT 0x0998
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#define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT 0x09a4
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#define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT 0x09a8
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#define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT 0x09ac
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#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT 0x09b0
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#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT 0x09b4
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#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT 0x09b8
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#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT 0x09bc
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#define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT 0x09c0
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#define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT 0x09c4
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#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 0x09c8
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#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 0x09cc
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#define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT 0x09d0
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#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 0x09d4
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#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 0x09d8
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#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 0x09dc
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#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 0x09e0
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#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 0x09e4
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#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 0x09e8
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#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 0x09ec
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#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 0x09f0
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#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 0x09f4
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#define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT 0x09f8
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT 0x09fc
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT 0x0a00
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT 0x0a04
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT 0x0a08
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT 0x0a0c
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT 0x0a10
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT 0x0a14
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#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT 0x0a18
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#define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT 0x0a1c
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#define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT 0x0a20
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#define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT 0x0a24
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/* MUX & PAD Control */
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#define MUX_PIN(name) \
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IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
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IOMUXC_SW_PAD_CTL_PAD_##name)
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#define MUX_PIN_MUX(name) \
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IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE)
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#define MUX_PIN_PAD(name) \
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IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name)
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#define MUX_PIN_GRP(name) \
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IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name)
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#define MUX_PIN_PATH(name) \
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IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE)
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/* INPUT Control */
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#define MUX_SELECT(name) (name##_SELECT_INPUT)
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#endif /* _IMX51_IOMUXREG_H */
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