freebsd-dev/sys/dev/aic7xxx/aic7770.c

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/*
* Product specific probe and attach routines for:
* 27/284X and aic7770 motherboard SCSI controllers
*
* Copyright (c) 1994-1998, 2000, 2001 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
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* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
* NO WARRANTY
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7770.c#31 $
*
* $FreeBSD$
*/
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
#ifdef __linux__
#include "aic7xxx_osm.h"
#include "aic7xxx_inline.h"
#include "aic7xxx_93cx6.h"
#else
#include <dev/aic7xxx/aic7xxx_osm.h>
#include <dev/aic7xxx/aic7xxx_inline.h>
#include <dev/aic7xxx/aic7xxx_93cx6.h>
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
#endif
#define ID_AIC7770 0x04907770
#define ID_AHA_274x 0x04907771
#define ID_AHA_284xB 0x04907756 /* BIOS enabled */
#define ID_AHA_284x 0x04907757 /* BIOS disabled*/
#define ID_OLV_274x 0x04907782 /* Olivetti OEM */
#define ID_OLV_274xD 0x04907783 /* Olivetti OEM (Differential) */
aic7xxx.c: aic7xxx.h: Split out core chip initialization into ahc_chip_init(). This will allow us to reset the chip correctly at times other than initial chip setup. aic7770.c aic7xxx_pci.c: Flesh out bus chip init methods for our two bus attachments and use these, in addition to bus suspend/resume hooks to get the core in better shape for handling these events. When disabling PCI parity error checking, use FAILDIS. Although the chip docs indicate that clearing PERRESPEN should also work, it does not. Auto-disable pci parity error checking after informing the user of AHC_PCI_TARGET_PERR_THRESH number of parity errors observed as a target. aic7xxx.h: aic7xxx_pci.c aic7770.c aic7xxx.c Add the instruction_ram_size softc field. Remove the now unused stack_size softc field. Modify ahc_loadseq to return a failure code and to actually check the downloaded instruction count against the limit set in our softc. Modify callers of ahc_loadseq to handle load failures as appropriate. Set instruction RAM sizes for each chip type. aic7xxx_pci.c: Add some delay in the aic785X termination control code. This may fix problems with the 2930. Be consistent in how we access config space registers. 16bit registers are accessed using 16bit ops. aic7xxx.c: Correct spelling errors. Have ahc_force_renegotiation() take a devinfo as is done in the U320 driver. Use this argument to correct a bug in the selection timeout handler where we forced a renegotiation with the last device that had set SAVED_SCSIID. SAVED_SCSIID is only updated once a selection is *sucessfull* and so is stale for any selection timeout. Cleanup the setup of the devinfo for busfree events. We now use this devinfo for a call to ahc_force_renegotiation() at the bottom of the routine, so it must be initialized in all cases. In ahc_pause_and_flushwork(), adjust the loop so that it will exit in the hot-eject case even if the INT_PEND mask is something other than 0xFF (as it is in this driver). Correct a wrapping string constant. Call ahc_fini_scbdata() after shutdown so that any ahc_chip_init() routine that might access SCB data will not access free'd memory. Correctly setup our buffer tag to indicate that 39bit addressing is available if in 39bit addressing mode. Rearrange some variable declarations based on type size. aic7xxx.c aic7xxx.h: aic7xxx.reg: Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AHC_OFFSET_UNKNOWN. Change AHC_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. Change MAX_OFFSET to 0x7f which is the max offset U160 aic7xxx controllers can negotiate. This ensures that curr->offset will not match AHC_OFFSET_UNKNOWN. aic7xxx_inline.h: Have our inline interrupt handler return with a value indicating whether we serviced a real interrupt. This is required for Linux support. Return earlier if the interrupt is not for us.
2003-05-03 23:55:38 +00:00
static int aic7770_chip_init(struct ahc_softc *ahc);
static int aic7770_suspend(struct ahc_softc *ahc);
static int aic7770_resume(struct ahc_softc *ahc);
static int aha2840_load_seeprom(struct ahc_softc *ahc);
static ahc_device_setup_t ahc_aic7770_VL_setup;
static ahc_device_setup_t ahc_aic7770_EISA_setup;;
static ahc_device_setup_t ahc_aic7770_setup;
struct aic7770_identity aic7770_ident_table[] =
{
{
ID_AHA_274x,
0xFFFFFFFF,
"Adaptec 274X SCSI adapter",
ahc_aic7770_EISA_setup
},
{
ID_AHA_284xB,
0xFFFFFFFE,
"Adaptec 284X SCSI adapter",
ahc_aic7770_VL_setup
},
{
ID_AHA_284x,
0xFFFFFFFE,
"Adaptec 284X SCSI adapter (BIOS Disabled)",
ahc_aic7770_VL_setup
},
{
ID_OLV_274x,
0xFFFFFFFF,
"Adaptec (Olivetti OEM) 274X SCSI adapter",
ahc_aic7770_EISA_setup
},
{
ID_OLV_274xD,
0xFFFFFFFF,
"Adaptec (Olivetti OEM) 274X Differential SCSI adapter",
ahc_aic7770_EISA_setup
},
/* Generic chip probes for devices we don't know 'exactly' */
{
ID_AIC7770,
0xFFFFFFFF,
"Adaptec aic7770 SCSI adapter",
ahc_aic7770_EISA_setup
}
};
const int ahc_num_aic7770_devs = NUM_ELEMENTS(aic7770_ident_table);
struct aic7770_identity *
aic7770_find_device(uint32_t id)
{
struct aic7770_identity *entry;
int i;
for (i = 0; i < ahc_num_aic7770_devs; i++) {
entry = &aic7770_ident_table[i];
if (entry->full_id == (id & entry->id_mask))
return (entry);
}
return (NULL);
}
int
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
aic7770_config(struct ahc_softc *ahc, struct aic7770_identity *entry, u_int io)
{
u_long l;
int error;
int have_seeprom;
u_int hostconf;
This is an MFC candidate. ahc_eisa.c: Change aic7770_map_int to take an additional irq parameter. Although we can get the irq from the eisa dev under FreeBSD, we can't do this under linux, so the OSM interface must supply this. ahc_pci.c: Move ahc_power_state_change() to the OSM. This allows us to use a platform supplied function that does the same thing. -current will move to the FreeBSD native API in the near future. aic7770.c: Sync up with core changes to support Linux EISA. We now store a 2 bit primary channel number rather than a bit flag that only allows b to be the primary channel. Adjust for this change. aic7xxx.c: Namespace and staticization cleanup. All exported symbols use an "ahc_" prefix to avoid collisions with other modules. Correct a logic bug that prevented us from dropping ATN during some exceptional conditions during message processing. Take advantage of a new flag managed by the sequencer that indicates if an SCB fetch is in progress. If so, the currently selected SCB needs to be returned to the free list to prevent an SCB leak. This leak is a rarity and would only occur if a bus reset or timeout resulting in a bus reset occurred in the middle of an SCB fetch. Don't attempt to perform ULTRA transfers on ultra capable adapters missing the external precision resistor required for ultra speeds. I've never encountered an adapter configured this way, but better safe than sorry. Handle the case of 5MHz user sync rate set as "0" instead of 0x1c in scratch ram. If we lookup a period of 0 in our table (async), clear the scsi offset. aic7xxx.h: Adjust for the primary channel being represented as a 2 bit integer in the flags member of the ahc softc. Cleanup the flags definitions so that comment blocks are not cramped. Update seeprom definitions to correctly reflect the fact that the primary channel is represented as a 2 bit integer. Add AHC_ULTRA_DIASABLED softc flag to denote controllers missing the external precision resistor. aic7xxx.reg: Add DFCACHETH to the definition of DFSTATUS for completness sake. Add SEQ_FLAGS2 which currently only contains the SCB_DMA (SCB DMA in progress) flag. aic7xxx.seq: Correct a problem when one lun has a disconnected untagged transaction and another lun has disconnected tagged transactions. Just because an entry is found in the untagged table doesn't mean that it will match. If the match on the lun fails, cleanup the SCB (return it to the disconnected list or free it), and snoop for a tag message. Before this change, we reported an unsolicited reselection. This bug was introduced about a month ago during an overly aggressive optimization pass on the reselection code. When cleaning up an SCB, we can't just blindly free the SCB. In the paging case, if the SCB came off of the disconnected list, its state may never have been updated in host memory. So, check the disconnected bit in SCB_CONTROL and return the SCB to the disconnected list if appropriate. Manage the SCB_DMA flag of SEQ_FLAGS2. More carefully shutdown the S/G dma engine in all cases by using a subroutine. Supposedly not doing this can cause an arbiter hang on some ULTRA2 chips. Formatting cleanup. On some chips, at least the aic7856, the transition from MREQPEND to HDONE can take a full 4 clock cycles. Test HDONE one more time to avoid this race. We only want our FIFO hung recovery code to execute when the engine is really hung. aic7xxx_93cx6.c: Sync perforce ids. aic7xxx_freebsd.c: Adjust for the primary channel being a 2 bit integer rather than a flag for 'B' channel being the primary. Namespace cleanup. Unpause the sequencer in one error recovery path that neglected to do so. This could have caused us to perform a bus reset when a recovery message might have otherwise been successful. aic7xxx_freebsd.h: Use AHC_PCI_CONFIG for controlling compilation of PCI support consistently throughout the driver. Move ahc_power_state_change() to OSM. aic7xxx_inline.h Namespace cleanup. Adjust our interrupt handler so it will work in the edge interrupt case. We must process all interrupt sources when the interrupt fires or risk not ever getting an interrupt again. This involves marking the fact that we are relying on an edge interrupt in ahc->flags and checking for this condition in addition to the AHC_ALL_INTERRUPTS flag. This fixes hangs on the 284X and any other aic7770 installation where level interrupts are not available. aic7xxx_pci.c: Move the powerstate manipulation code into the OSM. Several OSes now provide this functionality natively. Take another shot at using the data stored in scratch ram if the SCB2 signature is correct and no SEEPROM data is available. In the past this failed if external SCB ram was configured because the memory port was locked. We now release the memory port prior to testing the values in SCB2 and re-acquire it prior to doing termination control. Adjust for new 2 bit primary channel setting. Trust the STPWLEVEL setting on v 3.X BIOSes too. Configure any 785X ID in the same fashion and assume that any device with a rev id of 1 or higher has the PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
u_int irq;
u_int intdef;
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
error = entry->setup(ahc);
have_seeprom = 0;
if (error != 0)
return (error);
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
error = aic7770_map_registers(ahc, io);
if (error != 0)
return (error);
Major update to the aic7xxx driver: ahc_eisa.c: ahc_pci.c: Conform to new aic7xxx IRQ API. Adapt to aic7xxx_freebsd -> aic7xxx_osm changes. aic7770.c: Disable card generated interrupt early in our probe for "extra safety" Commonize some seeprom code with the PCI side of the driver. aic7xxx.c: Correctly initialize a few scratch ram locations during a sequencer restart. This avoids spurious sequencer ram parity errors in some configurations. Include the softc in ahc_update_residual calls. We need it for some diagnostics in this code path. Flag a data overrun on an auto-request sense failure as a CAM_AUTOSENSE_FAIL rather than a CAM_DATA_RUN_ERR. Force a renegotiation after noticing a parity error. This covers targets that lose our negotiation settings but don't bother to give us a unit attention condition. This can happen if a target fails during a reselection of us during a cable pull. Convert some code to using constants. Fix some typos. Correct target mode message loop handling. ahc_clear_msg_state was not clearing the "need to go to message out phase" bit once our loop was over. Simplify some abort handling code. Include tag information in target mode immediate notify events. When shutting down EISA controllers, don't EISA BIOS settings in the high portions of scratch ram. This fixes warm boot issues on some systems. Save a bit of space by only allocating the SCBs that we can use. Avoid some code paths in ahc_abort_scbs() if we are currently acting as a target. Correctly cleanup stranded SCBs in the card's SCB array. These are SCBs who's mapping has already been torn down by code that aborted the SCB by seeing it in another list first. Add a comment about some potential bus reset issues for target mode on Twin (EISA only) controllers. aic7xxx.h: Cleanup the hardware scb definitions a bit. Allocate a ful 256 byte scb mapping index. This simplifies the lookup code since the table covers all possible (and potentially bogus) values. Make AHC_DEBUG work again. aic7xxx.reg: Updates to hardware SCB definition. New definitions for target mode fixes. aic7xxx.seq: In target mode, initialize SAVED_LUN just after we receive the identify message. It may be required in the error recovery path when a normal cdb packet (includes lun) is not sent up to the host for processing. Respond to irregular messages during a selection in target mode. Defer looking for space for a cdb packet until we are about to enter command phase. We want to be able to handle irregular messages even if we would otherwise return QUEUE_FULL or BUSY. Add support for sending Ignore Wide Residue messages as a target. In the disable disconnect case in target mode, set our transfer rate correctly once data are availble. aic7xxx_93cx6.c: aic7xxx_93cx6.h: Add the ability to write and erase the seeprom. aic7xxx_inline.h: Correct Big Endian handling of large cdb sizes (> 12 bytes). Adaptec to changes in the calc_residual API. Correct a target mode bug where we always attempted to service the input queue even if no progress could be made due to lack of ATIOs. aic7xxx_osm.c: Adaptec to new IRQ mapping API. The new API allows the core to only enable our IRQ mapping once it is safe (sufficient initialization) to do so. Slap bootverbose protection around some diagnostics. Only attempt DT phases if we are wide. aic7xxx_osm.h: Enable big endian support. Adjust for IRQ API change. aic7xxx_pci.c: Be more careful about relying on subvendor 9005 information. We now only trust it for HBAs. This should allow the driver to attach to some MBs where the subvendor/device information does not follow the Adaptec spec. Only enable interrupts on the card once we are fully setup. Disable external SCB ram usage on the aic7895. I have not been able to make it 100% reliable. Adjust to seeprom routines being properly prefixed with "ahc". Fix a few bugs in the external SCB ram probing routine. We need to clear any parity errors we've triggered during the probe to avoid future, fatal, interrupts. If we detect an invalid cable combination, pretent there are no cable at all. This will enable all of the terminators which is probably the safest configuration we can "guess". MFC after: 4 days
2002-04-24 16:58:51 +00:00
/*
* Before we continue probing the card, ensure that
* its interrupts are *disabled*. We don't want
* a misstep to hang the machine in an interrupt
* storm.
*/
ahc_intr_enable(ahc, FALSE);
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
ahc->description = entry->name;
error = ahc_softc_init(ahc);
aic7xxx.c: aic7xxx.h: Split out core chip initialization into ahc_chip_init(). This will allow us to reset the chip correctly at times other than initial chip setup. aic7770.c aic7xxx_pci.c: Flesh out bus chip init methods for our two bus attachments and use these, in addition to bus suspend/resume hooks to get the core in better shape for handling these events. When disabling PCI parity error checking, use FAILDIS. Although the chip docs indicate that clearing PERRESPEN should also work, it does not. Auto-disable pci parity error checking after informing the user of AHC_PCI_TARGET_PERR_THRESH number of parity errors observed as a target. aic7xxx.h: aic7xxx_pci.c aic7770.c aic7xxx.c Add the instruction_ram_size softc field. Remove the now unused stack_size softc field. Modify ahc_loadseq to return a failure code and to actually check the downloaded instruction count against the limit set in our softc. Modify callers of ahc_loadseq to handle load failures as appropriate. Set instruction RAM sizes for each chip type. aic7xxx_pci.c: Add some delay in the aic785X termination control code. This may fix problems with the 2930. Be consistent in how we access config space registers. 16bit registers are accessed using 16bit ops. aic7xxx.c: Correct spelling errors. Have ahc_force_renegotiation() take a devinfo as is done in the U320 driver. Use this argument to correct a bug in the selection timeout handler where we forced a renegotiation with the last device that had set SAVED_SCSIID. SAVED_SCSIID is only updated once a selection is *sucessfull* and so is stale for any selection timeout. Cleanup the setup of the devinfo for busfree events. We now use this devinfo for a call to ahc_force_renegotiation() at the bottom of the routine, so it must be initialized in all cases. In ahc_pause_and_flushwork(), adjust the loop so that it will exit in the hot-eject case even if the INT_PEND mask is something other than 0xFF (as it is in this driver). Correct a wrapping string constant. Call ahc_fini_scbdata() after shutdown so that any ahc_chip_init() routine that might access SCB data will not access free'd memory. Correctly setup our buffer tag to indicate that 39bit addressing is available if in 39bit addressing mode. Rearrange some variable declarations based on type size. aic7xxx.c aic7xxx.h: aic7xxx.reg: Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AHC_OFFSET_UNKNOWN. Change AHC_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. Change MAX_OFFSET to 0x7f which is the max offset U160 aic7xxx controllers can negotiate. This ensures that curr->offset will not match AHC_OFFSET_UNKNOWN. aic7xxx_inline.h: Have our inline interrupt handler return with a value indicating whether we serviced a real interrupt. This is required for Linux support. Return earlier if the interrupt is not for us.
2003-05-03 23:55:38 +00:00
if (error != 0)
return (error);
ahc->bus_chip_init = aic7770_chip_init;
ahc->bus_suspend = aic7770_suspend;
ahc->bus_resume = aic7770_resume;
This is an MFC candidate. ahc_eisa.c: Change aic7770_map_int to take an additional irq parameter. Although we can get the irq from the eisa dev under FreeBSD, we can't do this under linux, so the OSM interface must supply this. ahc_pci.c: Move ahc_power_state_change() to the OSM. This allows us to use a platform supplied function that does the same thing. -current will move to the FreeBSD native API in the near future. aic7770.c: Sync up with core changes to support Linux EISA. We now store a 2 bit primary channel number rather than a bit flag that only allows b to be the primary channel. Adjust for this change. aic7xxx.c: Namespace and staticization cleanup. All exported symbols use an "ahc_" prefix to avoid collisions with other modules. Correct a logic bug that prevented us from dropping ATN during some exceptional conditions during message processing. Take advantage of a new flag managed by the sequencer that indicates if an SCB fetch is in progress. If so, the currently selected SCB needs to be returned to the free list to prevent an SCB leak. This leak is a rarity and would only occur if a bus reset or timeout resulting in a bus reset occurred in the middle of an SCB fetch. Don't attempt to perform ULTRA transfers on ultra capable adapters missing the external precision resistor required for ultra speeds. I've never encountered an adapter configured this way, but better safe than sorry. Handle the case of 5MHz user sync rate set as "0" instead of 0x1c in scratch ram. If we lookup a period of 0 in our table (async), clear the scsi offset. aic7xxx.h: Adjust for the primary channel being represented as a 2 bit integer in the flags member of the ahc softc. Cleanup the flags definitions so that comment blocks are not cramped. Update seeprom definitions to correctly reflect the fact that the primary channel is represented as a 2 bit integer. Add AHC_ULTRA_DIASABLED softc flag to denote controllers missing the external precision resistor. aic7xxx.reg: Add DFCACHETH to the definition of DFSTATUS for completness sake. Add SEQ_FLAGS2 which currently only contains the SCB_DMA (SCB DMA in progress) flag. aic7xxx.seq: Correct a problem when one lun has a disconnected untagged transaction and another lun has disconnected tagged transactions. Just because an entry is found in the untagged table doesn't mean that it will match. If the match on the lun fails, cleanup the SCB (return it to the disconnected list or free it), and snoop for a tag message. Before this change, we reported an unsolicited reselection. This bug was introduced about a month ago during an overly aggressive optimization pass on the reselection code. When cleaning up an SCB, we can't just blindly free the SCB. In the paging case, if the SCB came off of the disconnected list, its state may never have been updated in host memory. So, check the disconnected bit in SCB_CONTROL and return the SCB to the disconnected list if appropriate. Manage the SCB_DMA flag of SEQ_FLAGS2. More carefully shutdown the S/G dma engine in all cases by using a subroutine. Supposedly not doing this can cause an arbiter hang on some ULTRA2 chips. Formatting cleanup. On some chips, at least the aic7856, the transition from MREQPEND to HDONE can take a full 4 clock cycles. Test HDONE one more time to avoid this race. We only want our FIFO hung recovery code to execute when the engine is really hung. aic7xxx_93cx6.c: Sync perforce ids. aic7xxx_freebsd.c: Adjust for the primary channel being a 2 bit integer rather than a flag for 'B' channel being the primary. Namespace cleanup. Unpause the sequencer in one error recovery path that neglected to do so. This could have caused us to perform a bus reset when a recovery message might have otherwise been successful. aic7xxx_freebsd.h: Use AHC_PCI_CONFIG for controlling compilation of PCI support consistently throughout the driver. Move ahc_power_state_change() to OSM. aic7xxx_inline.h Namespace cleanup. Adjust our interrupt handler so it will work in the edge interrupt case. We must process all interrupt sources when the interrupt fires or risk not ever getting an interrupt again. This involves marking the fact that we are relying on an edge interrupt in ahc->flags and checking for this condition in addition to the AHC_ALL_INTERRUPTS flag. This fixes hangs on the 284X and any other aic7770 installation where level interrupts are not available. aic7xxx_pci.c: Move the powerstate manipulation code into the OSM. Several OSes now provide this functionality natively. Take another shot at using the data stored in scratch ram if the SCB2 signature is correct and no SEEPROM data is available. In the past this failed if external SCB ram was configured because the memory port was locked. We now release the memory port prior to testing the values in SCB2 and re-acquire it prior to doing termination control. Adjust for new 2 bit primary channel setting. Trust the STPWLEVEL setting on v 3.X BIOSes too. Configure any 785X ID in the same fashion and assume that any device with a rev id of 1 or higher has the PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
error = ahc_reset(ahc);
if (error != 0)
return (error);
This is an MFC candidate. ahc_eisa.c: Change aic7770_map_int to take an additional irq parameter. Although we can get the irq from the eisa dev under FreeBSD, we can't do this under linux, so the OSM interface must supply this. ahc_pci.c: Move ahc_power_state_change() to the OSM. This allows us to use a platform supplied function that does the same thing. -current will move to the FreeBSD native API in the near future. aic7770.c: Sync up with core changes to support Linux EISA. We now store a 2 bit primary channel number rather than a bit flag that only allows b to be the primary channel. Adjust for this change. aic7xxx.c: Namespace and staticization cleanup. All exported symbols use an "ahc_" prefix to avoid collisions with other modules. Correct a logic bug that prevented us from dropping ATN during some exceptional conditions during message processing. Take advantage of a new flag managed by the sequencer that indicates if an SCB fetch is in progress. If so, the currently selected SCB needs to be returned to the free list to prevent an SCB leak. This leak is a rarity and would only occur if a bus reset or timeout resulting in a bus reset occurred in the middle of an SCB fetch. Don't attempt to perform ULTRA transfers on ultra capable adapters missing the external precision resistor required for ultra speeds. I've never encountered an adapter configured this way, but better safe than sorry. Handle the case of 5MHz user sync rate set as "0" instead of 0x1c in scratch ram. If we lookup a period of 0 in our table (async), clear the scsi offset. aic7xxx.h: Adjust for the primary channel being represented as a 2 bit integer in the flags member of the ahc softc. Cleanup the flags definitions so that comment blocks are not cramped. Update seeprom definitions to correctly reflect the fact that the primary channel is represented as a 2 bit integer. Add AHC_ULTRA_DIASABLED softc flag to denote controllers missing the external precision resistor. aic7xxx.reg: Add DFCACHETH to the definition of DFSTATUS for completness sake. Add SEQ_FLAGS2 which currently only contains the SCB_DMA (SCB DMA in progress) flag. aic7xxx.seq: Correct a problem when one lun has a disconnected untagged transaction and another lun has disconnected tagged transactions. Just because an entry is found in the untagged table doesn't mean that it will match. If the match on the lun fails, cleanup the SCB (return it to the disconnected list or free it), and snoop for a tag message. Before this change, we reported an unsolicited reselection. This bug was introduced about a month ago during an overly aggressive optimization pass on the reselection code. When cleaning up an SCB, we can't just blindly free the SCB. In the paging case, if the SCB came off of the disconnected list, its state may never have been updated in host memory. So, check the disconnected bit in SCB_CONTROL and return the SCB to the disconnected list if appropriate. Manage the SCB_DMA flag of SEQ_FLAGS2. More carefully shutdown the S/G dma engine in all cases by using a subroutine. Supposedly not doing this can cause an arbiter hang on some ULTRA2 chips. Formatting cleanup. On some chips, at least the aic7856, the transition from MREQPEND to HDONE can take a full 4 clock cycles. Test HDONE one more time to avoid this race. We only want our FIFO hung recovery code to execute when the engine is really hung. aic7xxx_93cx6.c: Sync perforce ids. aic7xxx_freebsd.c: Adjust for the primary channel being a 2 bit integer rather than a flag for 'B' channel being the primary. Namespace cleanup. Unpause the sequencer in one error recovery path that neglected to do so. This could have caused us to perform a bus reset when a recovery message might have otherwise been successful. aic7xxx_freebsd.h: Use AHC_PCI_CONFIG for controlling compilation of PCI support consistently throughout the driver. Move ahc_power_state_change() to OSM. aic7xxx_inline.h Namespace cleanup. Adjust our interrupt handler so it will work in the edge interrupt case. We must process all interrupt sources when the interrupt fires or risk not ever getting an interrupt again. This involves marking the fact that we are relying on an edge interrupt in ahc->flags and checking for this condition in addition to the AHC_ALL_INTERRUPTS flag. This fixes hangs on the 284X and any other aic7770 installation where level interrupts are not available. aic7xxx_pci.c: Move the powerstate manipulation code into the OSM. Several OSes now provide this functionality natively. Take another shot at using the data stored in scratch ram if the SCB2 signature is correct and no SEEPROM data is available. In the past this failed if external SCB ram was configured because the memory port was locked. We now release the memory port prior to testing the values in SCB2 and re-acquire it prior to doing termination control. Adjust for new 2 bit primary channel setting. Trust the STPWLEVEL setting on v 3.X BIOSes too. Configure any 785X ID in the same fashion and assume that any device with a rev id of 1 or higher has the PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
/* Make sure we have a valid interrupt vector */
intdef = ahc_inb(ahc, INTDEF);
irq = intdef & VECTOR;
switch (irq) {
case 9:
case 10:
case 11:
case 12:
case 14:
case 15:
break;
default:
printf("aic7770_config: illegal irq setting %d\n", intdef);
return (ENXIO);
}
if ((intdef & EDGE_TRIG) != 0)
ahc->flags |= AHC_EDGE_INTERRUPT;
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
switch (ahc->chip & (AHC_EISA|AHC_VL)) {
case AHC_EISA:
{
u_int biosctrl;
u_int scsiconf;
u_int scsiconf1;
biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL);
scsiconf = ahc_inb(ahc, SCSICONF);
scsiconf1 = ahc_inb(ahc, SCSICONF + 1);
/* Get the primary channel information */
if ((biosctrl & CHANNEL_B_PRIMARY) != 0)
This is an MFC candidate. ahc_eisa.c: Change aic7770_map_int to take an additional irq parameter. Although we can get the irq from the eisa dev under FreeBSD, we can't do this under linux, so the OSM interface must supply this. ahc_pci.c: Move ahc_power_state_change() to the OSM. This allows us to use a platform supplied function that does the same thing. -current will move to the FreeBSD native API in the near future. aic7770.c: Sync up with core changes to support Linux EISA. We now store a 2 bit primary channel number rather than a bit flag that only allows b to be the primary channel. Adjust for this change. aic7xxx.c: Namespace and staticization cleanup. All exported symbols use an "ahc_" prefix to avoid collisions with other modules. Correct a logic bug that prevented us from dropping ATN during some exceptional conditions during message processing. Take advantage of a new flag managed by the sequencer that indicates if an SCB fetch is in progress. If so, the currently selected SCB needs to be returned to the free list to prevent an SCB leak. This leak is a rarity and would only occur if a bus reset or timeout resulting in a bus reset occurred in the middle of an SCB fetch. Don't attempt to perform ULTRA transfers on ultra capable adapters missing the external precision resistor required for ultra speeds. I've never encountered an adapter configured this way, but better safe than sorry. Handle the case of 5MHz user sync rate set as "0" instead of 0x1c in scratch ram. If we lookup a period of 0 in our table (async), clear the scsi offset. aic7xxx.h: Adjust for the primary channel being represented as a 2 bit integer in the flags member of the ahc softc. Cleanup the flags definitions so that comment blocks are not cramped. Update seeprom definitions to correctly reflect the fact that the primary channel is represented as a 2 bit integer. Add AHC_ULTRA_DIASABLED softc flag to denote controllers missing the external precision resistor. aic7xxx.reg: Add DFCACHETH to the definition of DFSTATUS for completness sake. Add SEQ_FLAGS2 which currently only contains the SCB_DMA (SCB DMA in progress) flag. aic7xxx.seq: Correct a problem when one lun has a disconnected untagged transaction and another lun has disconnected tagged transactions. Just because an entry is found in the untagged table doesn't mean that it will match. If the match on the lun fails, cleanup the SCB (return it to the disconnected list or free it), and snoop for a tag message. Before this change, we reported an unsolicited reselection. This bug was introduced about a month ago during an overly aggressive optimization pass on the reselection code. When cleaning up an SCB, we can't just blindly free the SCB. In the paging case, if the SCB came off of the disconnected list, its state may never have been updated in host memory. So, check the disconnected bit in SCB_CONTROL and return the SCB to the disconnected list if appropriate. Manage the SCB_DMA flag of SEQ_FLAGS2. More carefully shutdown the S/G dma engine in all cases by using a subroutine. Supposedly not doing this can cause an arbiter hang on some ULTRA2 chips. Formatting cleanup. On some chips, at least the aic7856, the transition from MREQPEND to HDONE can take a full 4 clock cycles. Test HDONE one more time to avoid this race. We only want our FIFO hung recovery code to execute when the engine is really hung. aic7xxx_93cx6.c: Sync perforce ids. aic7xxx_freebsd.c: Adjust for the primary channel being a 2 bit integer rather than a flag for 'B' channel being the primary. Namespace cleanup. Unpause the sequencer in one error recovery path that neglected to do so. This could have caused us to perform a bus reset when a recovery message might have otherwise been successful. aic7xxx_freebsd.h: Use AHC_PCI_CONFIG for controlling compilation of PCI support consistently throughout the driver. Move ahc_power_state_change() to OSM. aic7xxx_inline.h Namespace cleanup. Adjust our interrupt handler so it will work in the edge interrupt case. We must process all interrupt sources when the interrupt fires or risk not ever getting an interrupt again. This involves marking the fact that we are relying on an edge interrupt in ahc->flags and checking for this condition in addition to the AHC_ALL_INTERRUPTS flag. This fixes hangs on the 284X and any other aic7770 installation where level interrupts are not available. aic7xxx_pci.c: Move the powerstate manipulation code into the OSM. Several OSes now provide this functionality natively. Take another shot at using the data stored in scratch ram if the SCB2 signature is correct and no SEEPROM data is available. In the past this failed if external SCB ram was configured because the memory port was locked. We now release the memory port prior to testing the values in SCB2 and re-acquire it prior to doing termination control. Adjust for new 2 bit primary channel setting. Trust the STPWLEVEL setting on v 3.X BIOSes too. Configure any 785X ID in the same fashion and assume that any device with a rev id of 1 or higher has the PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
ahc->flags |= 1;
if ((biosctrl & BIOSMODE) == BIOSDISABLED) {
ahc->flags |= AHC_USEDEFAULTS;
} else {
if ((ahc->features & AHC_WIDE) != 0) {
ahc->our_id = scsiconf1 & HWSCSIID;
if (scsiconf & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_A;
} else {
ahc->our_id = scsiconf & HSCSIID;
ahc->our_id_b = scsiconf1 & HSCSIID;
if (scsiconf & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_A;
if (scsiconf1 & TERM_ENB)
ahc->flags |= AHC_TERM_ENB_B;
}
}
if ((ahc_inb(ahc, HA_274_BIOSGLOBAL) & HA_274_EXTENDED_TRANS))
ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B;
break;
}
case AHC_VL:
{
have_seeprom = aha2840_load_seeprom(ahc);
break;
}
default:
break;
}
if (have_seeprom == 0) {
free(ahc->seep_config, M_DEVBUF);
ahc->seep_config = NULL;
}
/*
* Ensure autoflush is enabled
*/
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
/* Setup the FIFO threshold and the bus off time */
hostconf = ahc_inb(ahc, HOSTCONF);
ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH);
ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF);
aic7xxx.c: aic7xxx.h: Split out core chip initialization into ahc_chip_init(). This will allow us to reset the chip correctly at times other than initial chip setup. aic7770.c aic7xxx_pci.c: Flesh out bus chip init methods for our two bus attachments and use these, in addition to bus suspend/resume hooks to get the core in better shape for handling these events. When disabling PCI parity error checking, use FAILDIS. Although the chip docs indicate that clearing PERRESPEN should also work, it does not. Auto-disable pci parity error checking after informing the user of AHC_PCI_TARGET_PERR_THRESH number of parity errors observed as a target. aic7xxx.h: aic7xxx_pci.c aic7770.c aic7xxx.c Add the instruction_ram_size softc field. Remove the now unused stack_size softc field. Modify ahc_loadseq to return a failure code and to actually check the downloaded instruction count against the limit set in our softc. Modify callers of ahc_loadseq to handle load failures as appropriate. Set instruction RAM sizes for each chip type. aic7xxx_pci.c: Add some delay in the aic785X termination control code. This may fix problems with the 2930. Be consistent in how we access config space registers. 16bit registers are accessed using 16bit ops. aic7xxx.c: Correct spelling errors. Have ahc_force_renegotiation() take a devinfo as is done in the U320 driver. Use this argument to correct a bug in the selection timeout handler where we forced a renegotiation with the last device that had set SAVED_SCSIID. SAVED_SCSIID is only updated once a selection is *sucessfull* and so is stale for any selection timeout. Cleanup the setup of the devinfo for busfree events. We now use this devinfo for a call to ahc_force_renegotiation() at the bottom of the routine, so it must be initialized in all cases. In ahc_pause_and_flushwork(), adjust the loop so that it will exit in the hot-eject case even if the INT_PEND mask is something other than 0xFF (as it is in this driver). Correct a wrapping string constant. Call ahc_fini_scbdata() after shutdown so that any ahc_chip_init() routine that might access SCB data will not access free'd memory. Correctly setup our buffer tag to indicate that 39bit addressing is available if in 39bit addressing mode. Rearrange some variable declarations based on type size. aic7xxx.c aic7xxx.h: aic7xxx.reg: Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AHC_OFFSET_UNKNOWN. Change AHC_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. Change MAX_OFFSET to 0x7f which is the max offset U160 aic7xxx controllers can negotiate. This ensures that curr->offset will not match AHC_OFFSET_UNKNOWN. aic7xxx_inline.h: Have our inline interrupt handler return with a value indicating whether we serviced a real interrupt. This is required for Linux support. Return earlier if the interrupt is not for us.
2003-05-03 23:55:38 +00:00
ahc->bus_softc.aic7770_softc.busspd = hostconf & DFTHRSH;
ahc->bus_softc.aic7770_softc.bustime = (hostconf << 2) & BOFF;
/*
* Generic aic7xxx initialization.
*/
error = ahc_init(ahc);
if (error != 0)
return (error);
error = aic7770_map_int(ahc, irq);
if (error != 0)
return (error);
ahc_list_lock(&l);
ahc_eisa.c: Initialize rid to 0. This doesn't seem to make any difference (the driver doesn't care what rid it gets and no-one seems to check rid's value), but follows standard conventions. Pass in our device_t to ahc_alloc(). We now use device_T softc storage, so passing NULL results in a panic. Set the unit number in our softc so that the driver core can retrieve it. ahc_pci.c: Set the unit number in our softc so that the driver core can retrieve it. aic7770.c: Insert our softc into the list of softcs when initialization is successful. aic7xxx.c: Remove a workaround for an aic7895 bug we will never trigger. Add additional diagnostic info to ahc_dump_card_state(). Always panic the system if a sequencer assertion fails. AHC_SCB_BTT is a "flag" not a "feature". Check the right field in the softc. Replace a hard coded number with a constant. Guard against looping forever in ahc_pause_and_flushwork(). A hot eject or card failure may make the intstat register return 0xFF, so limit the number of interrupts we'll process. Correct the code in ahc_search_qinfifo() that guarantees that the sequencer will see an abort collision if the qinfifo is modified when a DMA is in progress. We now do this fixup after modifying the queue. This guarantees that the HSCB we place at the head of the queue is not the same as the old head. Using "next hscb" (guaranteed not to be the same as the first SCB) before clearing the queue could free up the original head hscb to be used during a remove operation placing it again at the head of the qinfifo. aic7xxx.h: Reduce the maximum number of outstanding commands to 253 from 254. To handle our output queue correctly on machines that only support 32bit stores, we must clear the array 4 bytes at a time. To avoid colliding with a DMA write from the sequencer, we must be sure that 4 slots are empty when we write to clear the queue. This reduces us to 253 SCBs: 1 that just completed and the known three additional empty slots in the queue that preceed it. Yahoo was able to force this race on one of their systems. Interrupts were disabled for such a time that the entire output queue was filled (254 entries complete without any processing), and our 32bit write to clear the status clobbered one entry. Add a feature tag for devices that are removable. aic7xxx.reg: Never use the sequencer interrupt value of 0xF0. We need to guanrantee that an INTSTAT value of 0xFF can only occur during card failure or a hot-eject. Align the busy targets table with the begining of scratch space. This seems to appease a chip bug in the aic7895. aic7xxx.seq: Be sure to disable select-out after a bus free event that occurs early in a selection. If we don't disable select-out, we will believe that it is enabled even though a new selection will never occur. Move the clearing of SELDI to just before a jump. This appeases another chip bug of the aic7895. Make the target mode command loop a bit more efficient. AHC_SCB_BTT is a "flag" not a "feature". Check the right field in the softc. Properly cleanup the last SCB we tested against should we fail to properly find an SCB for a reselection. Add some additional sequencer debugging code. aic7xxx_freebsd.c: Limit the driver to 253 outstanding commands per adapter. Guard against overflow in timeout handling. aic7xxx_inline.h: AHC_SCB_BTT is a "flag" not a "feature". Check the right field in the softc. aic7xxx_pci.c: Set the removable feature for the apa1480 cardbus and the 29160C Compact PCI card. Don't report high byte termination information for narrow cards. Use a PCI read rather than a questionable delay when fetching/setting termination settings.
2001-01-22 21:03:48 +00:00
/*
* Link this softc in with all other ahc instances.
*/
ahc_softc_insert(ahc);
/*
* Enable the board's BUS drivers
*/
ahc_outb(ahc, BCTL, ENABLE);
ahc_list_unlock(&l);
aic7770.c: aic7xxx_pci.c: Enable board generation of interrupts only once our handler is in place and all other setup has occurred. aic7xxx.c: More conversion of data types to ahc_* names. tmode_tstate and tmode_lstate are the latest victims. Clean up the check condition path by branching early rather than indenting a giant block of code. Add support for target mode initiated sync negotiation. The code has been tested by forcing the feature on for all devices, but for the moment is left inaccesible until a decent mechanism for controlling the behavior is complete. Implementing this feature required the removal of the old "target message request" mechanism. The old method required setting one of the 16 bit fields to initiate negotiation with a particular target. This had the nice effect of being easy to change the request and have it effect the next command. We now set the MK_MESSAGE bit on any new command when negotiation is required. When the negotiation is successful, we walk through and clean up the bit on any pending commands. Since we have to walk the commands to reset the SCSI syncrate values so no additional work is required. The only drawback of this approach is that the negotiation is deferred until the next command is queued to the controller. On the plus side, we regain two bytes of sequencer scratch ram and 6 sequencer instructions. When cleaning up a target mode instance, never remove the "master" target mode state object. The master contains all of the saved SEEPROM settings that control things like transfer negotiations. This data will be cloned as the defaults if a target mode instance is re-instantiated. Correct a bug in ahc_set_width(). We neglected to update the pending scbs to reflect the new parameters. Since wide negotiation is almost always followed by sync negotiation it is doubtful that this had any real effect. When in the target role, don't complain about "Target Initiated" negotiation requests when an initiator negotiates with us. Defer enabling board interrupts until after ahc_intr_enable() is called. Pull all info that used to be in ahc_timeout for the FreeBSD OSM into ahc_dump_card_state(). This info should be printed out on all platforms. aic7xxx.h: Add the SCB_AUTO_NEGOITATE scb flag. This allows us to discern the reason the MK_MESSAGE flag is set in the hscb control byte. We only want to clear MK_MESSAGE in ahc_update_pending_scbs() if the MK_MESSAGE was set due to an auto transfer negotiation. Add the auto_negotiate bitfield for each tstate so that behavior can be controlled for each of our enabled SCSI IDs. Use a bus interrupt handler vector in our softc rather than hard coding the PCI interrupt handler. This makes it easier to build the different bus attachments to the aic7xxx driver as modules. aic7xxx.reg: Remove the TARGET_MSG_REQUEST definition for sequencer ram. aic7xxx.seq: Fix a few target mode bugs: o If MK_MESSAGE is set in an SCB, transition to message in phase and notify the kernel so that message delivery can occur. This is currently only used for target mode initiated transfer negotiation. o Allow a continue target I/O to compile without executing a status phase or disconnecting. If we have not been granted the disconnect privledge but this transfer is larger than MAXPHYS, it may take several CTIOs to get the job done. Remove the tests of the TARGET_MSG_REQUEST field in scratch ram. aic7xxx_freebsd.c: Add support for CTIOs that don't disconnect. We now defer the clearing of our pending target state until we see a CTIO for that device that has completed sucessfully. Be sure to return early if we are in a target only role and see an initiator only CCB type in our action routine. If a CTIO has the CAM_DIS_DISCONNECT flag set, propogate this flag to the SCB. This flag has no effect if we've been asked to deliver status as well. We will complete the command and release the bus in that case. Handle the new auto_negotiate field in the tstate correctly. Make sure that SCBs for "immediate" (i.e. to continue a non disconnected transaction) CTIO requests get a proper mapping in the SCB lookup table. Without this, we'll complain when the transaction completes. Update ahc_timeout() to reflect the changes to ahc_dump_card_state(). aic7xxx_inline.h: Use ahc->bus_intr rather than ahc_pci_intr.
2001-03-29 00:36:35 +00:00
return (0);
}
aic7xxx.c: aic7xxx.h: Split out core chip initialization into ahc_chip_init(). This will allow us to reset the chip correctly at times other than initial chip setup. aic7770.c aic7xxx_pci.c: Flesh out bus chip init methods for our two bus attachments and use these, in addition to bus suspend/resume hooks to get the core in better shape for handling these events. When disabling PCI parity error checking, use FAILDIS. Although the chip docs indicate that clearing PERRESPEN should also work, it does not. Auto-disable pci parity error checking after informing the user of AHC_PCI_TARGET_PERR_THRESH number of parity errors observed as a target. aic7xxx.h: aic7xxx_pci.c aic7770.c aic7xxx.c Add the instruction_ram_size softc field. Remove the now unused stack_size softc field. Modify ahc_loadseq to return a failure code and to actually check the downloaded instruction count against the limit set in our softc. Modify callers of ahc_loadseq to handle load failures as appropriate. Set instruction RAM sizes for each chip type. aic7xxx_pci.c: Add some delay in the aic785X termination control code. This may fix problems with the 2930. Be consistent in how we access config space registers. 16bit registers are accessed using 16bit ops. aic7xxx.c: Correct spelling errors. Have ahc_force_renegotiation() take a devinfo as is done in the U320 driver. Use this argument to correct a bug in the selection timeout handler where we forced a renegotiation with the last device that had set SAVED_SCSIID. SAVED_SCSIID is only updated once a selection is *sucessfull* and so is stale for any selection timeout. Cleanup the setup of the devinfo for busfree events. We now use this devinfo for a call to ahc_force_renegotiation() at the bottom of the routine, so it must be initialized in all cases. In ahc_pause_and_flushwork(), adjust the loop so that it will exit in the hot-eject case even if the INT_PEND mask is something other than 0xFF (as it is in this driver). Correct a wrapping string constant. Call ahc_fini_scbdata() after shutdown so that any ahc_chip_init() routine that might access SCB data will not access free'd memory. Correctly setup our buffer tag to indicate that 39bit addressing is available if in 39bit addressing mode. Rearrange some variable declarations based on type size. aic7xxx.c aic7xxx.h: aic7xxx.reg: Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AHC_OFFSET_UNKNOWN. Change AHC_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. Change MAX_OFFSET to 0x7f which is the max offset U160 aic7xxx controllers can negotiate. This ensures that curr->offset will not match AHC_OFFSET_UNKNOWN. aic7xxx_inline.h: Have our inline interrupt handler return with a value indicating whether we serviced a real interrupt. This is required for Linux support. Return earlier if the interrupt is not for us.
2003-05-03 23:55:38 +00:00
static int
aic7770_chip_init(struct ahc_softc *ahc)
{
ahc_outb(ahc, BUSSPD, ahc->bus_softc.aic7770_softc.busspd);
ahc_outb(ahc, BUSTIME, ahc->bus_softc.aic7770_softc.bustime);
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
ahc_outb(ahc, BCTL, ENABLE);
return (ahc_chip_init(ahc));
}
static int
aic7770_suspend(struct ahc_softc *ahc)
{
return (ahc_suspend(ahc));
}
static int
aic7770_resume(struct ahc_softc *ahc)
{
return (ahc_resume(ahc));
}
/*
* Read the 284x SEEPROM.
*/
static int
aha2840_load_seeprom(struct ahc_softc *ahc)
{
struct seeprom_descriptor sd;
struct seeprom_config *sc;
int have_seeprom;
uint8_t scsi_conf;
sd.sd_ahc = ahc;
sd.sd_control_offset = SEECTL_2840;
sd.sd_status_offset = STATUS_2840;
sd.sd_dataout_offset = STATUS_2840;
sd.sd_chip = C46;
sd.sd_MS = 0;
sd.sd_RDY = EEPROM_TF;
sd.sd_CS = CS_2840;
sd.sd_CK = CK_2840;
sd.sd_DO = DO_2840;
sd.sd_DI = DI_2840;
sc = ahc->seep_config;
if (bootverbose)
printf("%s: Reading SEEPROM...", ahc_name(ahc));
have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
aic7xxx.c: aic7xxx.h: Split out core chip initialization into ahc_chip_init(). This will allow us to reset the chip correctly at times other than initial chip setup. aic7770.c aic7xxx_pci.c: Flesh out bus chip init methods for our two bus attachments and use these, in addition to bus suspend/resume hooks to get the core in better shape for handling these events. When disabling PCI parity error checking, use FAILDIS. Although the chip docs indicate that clearing PERRESPEN should also work, it does not. Auto-disable pci parity error checking after informing the user of AHC_PCI_TARGET_PERR_THRESH number of parity errors observed as a target. aic7xxx.h: aic7xxx_pci.c aic7770.c aic7xxx.c Add the instruction_ram_size softc field. Remove the now unused stack_size softc field. Modify ahc_loadseq to return a failure code and to actually check the downloaded instruction count against the limit set in our softc. Modify callers of ahc_loadseq to handle load failures as appropriate. Set instruction RAM sizes for each chip type. aic7xxx_pci.c: Add some delay in the aic785X termination control code. This may fix problems with the 2930. Be consistent in how we access config space registers. 16bit registers are accessed using 16bit ops. aic7xxx.c: Correct spelling errors. Have ahc_force_renegotiation() take a devinfo as is done in the U320 driver. Use this argument to correct a bug in the selection timeout handler where we forced a renegotiation with the last device that had set SAVED_SCSIID. SAVED_SCSIID is only updated once a selection is *sucessfull* and so is stale for any selection timeout. Cleanup the setup of the devinfo for busfree events. We now use this devinfo for a call to ahc_force_renegotiation() at the bottom of the routine, so it must be initialized in all cases. In ahc_pause_and_flushwork(), adjust the loop so that it will exit in the hot-eject case even if the INT_PEND mask is something other than 0xFF (as it is in this driver). Correct a wrapping string constant. Call ahc_fini_scbdata() after shutdown so that any ahc_chip_init() routine that might access SCB data will not access free'd memory. Correctly setup our buffer tag to indicate that 39bit addressing is available if in 39bit addressing mode. Rearrange some variable declarations based on type size. aic7xxx.c aic7xxx.h: aic7xxx.reg: Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AHC_OFFSET_UNKNOWN. Change AHC_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. Change MAX_OFFSET to 0x7f which is the max offset U160 aic7xxx controllers can negotiate. This ensures that curr->offset will not match AHC_OFFSET_UNKNOWN. aic7xxx_inline.h: Have our inline interrupt handler return with a value indicating whether we serviced a real interrupt. This is required for Linux support. Return earlier if the interrupt is not for us.
2003-05-03 23:55:38 +00:00
/*start_addr*/0, sizeof(*sc)/2);
if (have_seeprom) {
if (ahc_verify_cksum(sc) == 0) {
if(bootverbose)
printf ("checksum error\n");
have_seeprom = 0;
} else if (bootverbose) {
printf("done.\n");
}
}
if (!have_seeprom) {
if (bootverbose)
printf("%s: No SEEPROM available\n", ahc_name(ahc));
ahc->flags |= AHC_USEDEFAULTS;
} else {
/*
* Put the data we've collected down into SRAM
* where ahc_init will find it.
*/
int i;
int max_targ;
uint16_t discenable;
max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8;
discenable = 0;
for (i = 0; i < max_targ; i++){
uint8_t target_settings;
target_settings = (sc->device_flags[i] & CFXFER) << 4;
if (sc->device_flags[i] & CFSYNCH)
target_settings |= SOFS;
if (sc->device_flags[i] & CFWIDEB)
target_settings |= WIDEXFER;
if (sc->device_flags[i] & CFDISC)
discenable |= (0x01 << i);
ahc_outb(ahc, TARG_SCSIRATE + i, target_settings);
}
ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
ahc->our_id = sc->brtime_id & CFSCSIID;
scsi_conf = (ahc->our_id & 0x7);
if (sc->adapter_control & CFSPARITY)
scsi_conf |= ENSPCHK;
if (sc->adapter_control & CFRESETB)
scsi_conf |= RESET_SCSI;
if (sc->bios_control & CF284XEXTEND)
ahc->flags |= AHC_EXTENDED_TRANS_A;
/* Set SCSICONF info */
ahc_outb(ahc, SCSICONF, scsi_conf);
if (sc->adapter_control & CF284XSTERM)
ahc->flags |= AHC_TERM_ENB_A;
}
return (have_seeprom);
}
static int
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
ahc_aic7770_VL_setup(struct ahc_softc *ahc)
{
int error;
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
error = ahc_aic7770_setup(ahc);
ahc->chip |= AHC_VL;
return (error);
}
static int
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
ahc_aic7770_EISA_setup(struct ahc_softc *ahc)
{
int error;
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
error = ahc_aic7770_setup(ahc);
ahc->chip |= AHC_EISA;
return (error);
}
static int
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
ahc_aic7770_setup(struct ahc_softc *ahc)
{
ahc_pci.c: If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
2001-07-18 21:39:48 +00:00
ahc->channel = 'A';
ahc->channel_b = 'B';
ahc->chip = AHC_AIC7770;
ahc->features = AHC_AIC7770_FE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
ahc->flags |= AHC_PAGESCBS;
aic7xxx.c: aic7xxx.h: Split out core chip initialization into ahc_chip_init(). This will allow us to reset the chip correctly at times other than initial chip setup. aic7770.c aic7xxx_pci.c: Flesh out bus chip init methods for our two bus attachments and use these, in addition to bus suspend/resume hooks to get the core in better shape for handling these events. When disabling PCI parity error checking, use FAILDIS. Although the chip docs indicate that clearing PERRESPEN should also work, it does not. Auto-disable pci parity error checking after informing the user of AHC_PCI_TARGET_PERR_THRESH number of parity errors observed as a target. aic7xxx.h: aic7xxx_pci.c aic7770.c aic7xxx.c Add the instruction_ram_size softc field. Remove the now unused stack_size softc field. Modify ahc_loadseq to return a failure code and to actually check the downloaded instruction count against the limit set in our softc. Modify callers of ahc_loadseq to handle load failures as appropriate. Set instruction RAM sizes for each chip type. aic7xxx_pci.c: Add some delay in the aic785X termination control code. This may fix problems with the 2930. Be consistent in how we access config space registers. 16bit registers are accessed using 16bit ops. aic7xxx.c: Correct spelling errors. Have ahc_force_renegotiation() take a devinfo as is done in the U320 driver. Use this argument to correct a bug in the selection timeout handler where we forced a renegotiation with the last device that had set SAVED_SCSIID. SAVED_SCSIID is only updated once a selection is *sucessfull* and so is stale for any selection timeout. Cleanup the setup of the devinfo for busfree events. We now use this devinfo for a call to ahc_force_renegotiation() at the bottom of the routine, so it must be initialized in all cases. In ahc_pause_and_flushwork(), adjust the loop so that it will exit in the hot-eject case even if the INT_PEND mask is something other than 0xFF (as it is in this driver). Correct a wrapping string constant. Call ahc_fini_scbdata() after shutdown so that any ahc_chip_init() routine that might access SCB data will not access free'd memory. Correctly setup our buffer tag to indicate that 39bit addressing is available if in 39bit addressing mode. Rearrange some variable declarations based on type size. aic7xxx.c aic7xxx.h: aic7xxx.reg: Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AHC_OFFSET_UNKNOWN. Change AHC_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. Change MAX_OFFSET to 0x7f which is the max offset U160 aic7xxx controllers can negotiate. This ensures that curr->offset will not match AHC_OFFSET_UNKNOWN. aic7xxx_inline.h: Have our inline interrupt handler return with a value indicating whether we serviced a real interrupt. This is required for Linux support. Return earlier if the interrupt is not for us.
2003-05-03 23:55:38 +00:00
ahc->instruction_ram_size = 448;
return (0);
}