2005-01-06 01:43:34 +00:00
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/*-
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2004-04-11 19:32:20 +00:00
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* Device driver for Specialix I/O8+ multiport serial card.
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*
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* Copyright 2003 Frank Mayhar <frank@exit.com>
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*
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* Derived from the "si" driver by Peter Wemm <peter@netplex.com.au>, using
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* lots of information from the Linux "specialix" driver by Roger Wolff
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* <R.E.Wolff@BitWizard.nl> and from the Intel CD1865 "Intelligent Eight-
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* Channel Communications Controller" datasheet. Roger was also nice
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* enough to answer numerous questions about stuff specific to the I/O8+
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* not covered by the CD1865 datasheet.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notices, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notices, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHORS BE LIABLE.
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*
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* $FreeBSD$
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*/
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/*
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* Per-channel soft information structure, stored in the driver. It's called
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* "sx_port" just because the si driver calls it "si_port."
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*
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* This information is mostly visible via ioctl().
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*/
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struct sx_port {
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int sp_chan; /* Channel number, for convenience. */
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struct tty *sp_tty;
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int sp_state;
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int sp_delta_overflows;
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2004-10-08 06:45:10 +00:00
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struct sx_softc *sp_sc;
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2004-04-11 19:32:20 +00:00
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int sp_debug; /* debug mask */
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};
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/*
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* Various important values.
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*/
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#define SX_NUMCHANS 8 /* Eight channels on an I/O8+. */
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#define SX_PCI_IO_SPACE 8 /* How much address space to use. */
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#define SX_CCR_TIMEOUT 10000 /* Channel Command Register timeout, 10ms. */
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#define SX_GSVR_TIMEOUT 1000 /* GSVR reset timeout, 1ms. */
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#define SX_CD1865_ID 0x10 /* ID of the I/O8+ CD1865 chip. */
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#define SX_EI 0x80 /* "Enable interrupt" flag for I/O8+ commands.*/
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#define SX_DATA_REG 0 /* Data register. */
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#define SX_ADDR_REG 1 /* Address register. */
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/*
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* The I/O8+ has a 25MHz oscillator on board, but the CD1865 runs at half
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* that.
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*/
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#define SX_CD1865_CLOCK 12500000 /* CD1865 clock on I/O8+. */
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#define SX_CD1865_TICK 4000 /* Timer tick rate, via prescaler. */
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#define SX_CD1865_PRESCALE (SX_CD1865_CLOCK/SX_CD1865_TICK) /* Prescale value.*/
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/* Buffer parameters */
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#define SX_BUFFERSIZE CD1865_RFIFOSZ /* Just the size of the receive FIFO. */
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#define SX_I_HIGH_WATER (TTYHOG - 2 * SX_BUFFERSIZE)
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/*
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* Precomputed bitrate clock divisors. Formula is
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*
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* Clock rate (Hz) 12500000
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* divisor = --------------- or ------------
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* 16 * bit rate 16 * bitrate
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*
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* All values are rounded to the nearest integer.
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*/
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#define CLK75 0x28b1 /* 10416.666667 */
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#define CLK110 0x1bbe /* 7102.272727 */
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#define CLK150 0x1458 /* 5208.333333 */
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#define CLK300 0x0a2c /* 2604.166667 */
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#define CLK600 0x0516 /* 1302.083333 */
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#define CLK1200 0x028b /* 651.0416667 */
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#define CLK2000 0x0187 /* 390.625 */
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#define CLK2400 0x0146 /* 325.5208333 */
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#define CLK4800 0x00a3 /* 162.7604167 */
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#define CLK7200 0x006d /* 108.5069444 */
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#define CLK9600 0x0051 /* 81.38020833 */
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#define CLK19200 0x0029 /* 40.69010417 */
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#define CLK38400 0x0014 /* 20.34505208 */
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#define CLK57600 0x000e /* 13.56336806 */
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#define CLK115200 0x0007 /* 6.781684028 */
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/* sp_state */
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#define SX_SS_CLOSED 0x00000 /* Port is closed. */
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#define SX_SS_OPEN 0x00001 /* Port is open and active. */
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#define SX_SS_XMIT 0x00002 /* We're transmitting data. */
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#define SX_SS_INTR 0x00004 /* We're processing an interrupt. */
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#define SX_SS_CLOSING 0x00008 /* in the middle of an sxclose() */
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#define SX_SS_WAITWRITE 0x00010
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#define SX_SS_BLOCKWRITE 0x00020
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#define SX_SS_DTR_OFF 0x00040 /* DTR held off */
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#define SX_SS_IFLOW 0x00080 /* Input (RTS) flow control on. */
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#define SX_SS_OFLOW 0x00100 /* Output (CTS) flow control on. */
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#define SX_SS_IRCV 0x00200 /* In a receive interrupt. */
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#define SX_SS_IMODEM 0x00400 /* In a modem-signal interrupt. */
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#define SX_SS_IRCVEXC 0x00800 /* In a receive-exception interrupt. */
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#define SX_SS_IXMIT 0x01000 /* In a transmit interrupt. */
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#define SX_SS_OSTOP 0x02000 /* Stopped by output flow control. */
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#define SX_SS_ISTOP 0x04000 /* Stopped by input flow control. */
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#define SX_SS_DTRPIN 0x08000 /* DTR/RTS pin is DTR. */
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#define SX_SS_DOBRK 0x10000 /* Change break status. */
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#define SX_SS_BREAK 0x20000 /* Doing break. */
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#define SX_DTRPIN(pp) ((pp)->sp_state & SX_SS_DTRPIN) /* DTR/RTS pin is DTR.*/
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#define SX_XMITTING(pp) ((pp)->sp_state & SX_SS_XMIT) /* We're transmitting. */
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#define SX_INTR(pp) ((pp)->sp_state & SX_SS_INTR) /* In an interrupt. */
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#define SX_IXMIT(pp) ((pp)->sp_state & SX_SS_IXMIT) /* Transmit interrupt. */
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#define SX_IFLOW(pp) ((pp)->sp_state & SX_SS_IFLOW) /* Input flow control. */
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#define SX_OFLOW(pp) ((pp)->sp_state & SX_SS_OFLOW) /* Output flow control.*/
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#define SX_IRCV(pp) ((pp)->sp_state & SX_SS_IRCV) /* Receive interrupt. */
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#define SX_IMODEM(pp) ((pp)->sp_state & SX_SS_IMODEM) /* Modem state change.*/
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#define SX_IRCVEXC(pp) ((pp)->sp_state & SX_SS_IRCVEXC) /* Rcv exception. */
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#define SX_OSTOP(pp) ((pp)->sp_state & SX_SS_OSTOP) /* Output stopped. */
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#define SX_ISTOP(pp) ((pp)->sp_state & SX_SS_ISTOP) /* Input stopped. */
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#define SX_DOBRK(pp) ((pp)->sp_state & SX_SS_DOBRK) /* Change break status.*/
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#define SX_BREAK(pp) ((pp)->sp_state & SX_SS_BREAK) /* Doing break. */
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#define DBG_ENTRY 0x00000001
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#define DBG_DRAIN 0x00000002
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#define DBG_OPEN 0x00000004
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#define DBG_CLOSE 0x00000008
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/* 0x00000010*/
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#define DBG_WRITE 0x00000020
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#define DBG_PARAM 0x00000040
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#define DBG_INTR 0x00000080
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#define DBG_IOCTL 0x00000100
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/* 0x00000200 */
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/* 0x00000400*/
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#define DBG_OPTIM 0x00000800
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#define DBG_START 0x00001000
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#define DBG_EXIT 0x00002000
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#define DBG_FAIL 0x00004000
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#define DBG_STOP 0x00008000
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#define DBG_AUTOBOOT 0x00010000
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#define DBG_MODEM 0x00020000
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#define DBG_MODEM_STATE 0x00040000
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#define DBG_RECEIVE 0x00080000
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#define DBG_POLL 0x00100000
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#define DBG_TRANSMIT 0x00200000
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#define DBG_RECEIVE_EXC 0x00400000
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#define DBG_PRINTF 0x80000000
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#define DBG_ALL 0xffffffff
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