2011-03-21 09:58:24 +00:00
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/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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2014-09-23 12:37:01 +00:00
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* Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
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2011-03-21 09:58:24 +00:00
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* Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX4_FW_H
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#define MLX4_FW_H
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#include "mlx4.h"
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#include "icm.h"
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struct mlx4_mod_stat_cfg {
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u8 log_pg_sz;
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u8 log_pg_sz_m;
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};
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struct mlx4_dev_cap {
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int max_srq_sz;
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int max_qp_sz;
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int reserved_qps;
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int max_qps;
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int reserved_srqs;
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int max_srqs;
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int max_cq_sz;
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int reserved_cqs;
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int max_cqs;
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int max_mpts;
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int reserved_eqs;
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int max_eqs;
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2017-02-10 15:22:21 +00:00
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int num_sys_eqs;
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2011-03-21 09:58:24 +00:00
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int reserved_mtts;
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int max_mrw_sz;
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int reserved_mrws;
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int max_mtt_seg;
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int max_requester_per_qp;
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int max_responder_per_qp;
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int max_rdma_global;
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int local_ca_ack_delay;
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int num_ports;
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u32 max_msg_sz;
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int ib_mtu[MLX4_MAX_PORTS + 1];
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int max_port_width[MLX4_MAX_PORTS + 1];
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int max_vl[MLX4_MAX_PORTS + 1];
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int max_gids[MLX4_MAX_PORTS + 1];
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int max_pkeys[MLX4_MAX_PORTS + 1];
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u64 def_mac[MLX4_MAX_PORTS + 1];
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u16 eth_mtu[MLX4_MAX_PORTS + 1];
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int trans_type[MLX4_MAX_PORTS + 1];
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int vendor_oui[MLX4_MAX_PORTS + 1];
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u16 wavelength[MLX4_MAX_PORTS + 1];
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u64 trans_code[MLX4_MAX_PORTS + 1];
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u16 stat_rate_support;
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2013-09-29 00:35:03 +00:00
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int fs_log_max_ucast_qp_range_size;
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int fs_max_num_qp_per_entry;
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2011-03-21 09:58:24 +00:00
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u64 flags;
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2013-09-29 00:35:03 +00:00
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u64 flags2;
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2011-03-21 09:58:24 +00:00
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int reserved_uars;
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int uar_size;
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int min_page_sz;
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int bf_reg_size;
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int bf_regs_per_page;
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int max_sq_sg;
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int max_sq_desc_sz;
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int max_rq_sg;
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int max_rq_desc_sz;
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int max_qp_per_mcg;
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int reserved_mgms;
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int max_mcgs;
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int reserved_pds;
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int max_pds;
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int reserved_xrcds;
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int max_xrcds;
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int qpc_entry_sz;
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int rdmarc_entry_sz;
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int altc_entry_sz;
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int aux_entry_sz;
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int srq_entry_sz;
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int cqc_entry_sz;
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int eqc_entry_sz;
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int dmpt_entry_sz;
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int cmpt_entry_sz;
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int mtt_entry_sz;
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int resize_srq;
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u32 bmme_flags;
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u32 reserved_lkey;
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u64 max_icm_sz;
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int max_gso_sz;
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2013-09-29 00:35:03 +00:00
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int max_rss_tbl_sz;
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2011-03-21 09:58:24 +00:00
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u8 supported_port_types[MLX4_MAX_PORTS + 1];
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2013-09-29 00:35:03 +00:00
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u8 suggested_type[MLX4_MAX_PORTS + 1];
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u8 default_sense[MLX4_MAX_PORTS + 1];
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2011-03-21 09:58:24 +00:00
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u8 log_max_macs[MLX4_MAX_PORTS + 1];
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u8 log_max_vlans[MLX4_MAX_PORTS + 1];
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u32 max_basic_counters;
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2013-09-29 00:35:03 +00:00
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u32 sync_qp;
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u8 timestamp_support;
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u32 max_extended_counters;
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};
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struct mlx4_func_cap {
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u8 num_ports;
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u8 flags;
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u32 pf_context_behaviour;
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int qp_quota;
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int cq_quota;
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int srq_quota;
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int mpt_quota;
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int mtt_quota;
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int max_eq;
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int reserved_eq;
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int mcg_quota;
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u32 qp0_tunnel_qpn;
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u32 qp0_proxy_qpn;
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u32 qp1_tunnel_qpn;
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u32 qp1_proxy_qpn;
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u8 physical_port;
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u8 port_flags;
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2014-09-23 12:37:01 +00:00
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u8 def_counter_index;
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Change mlx4 QP allocation scheme.
When using Blue-Flame, BF, the QPN overrides the VLAN, CV, and SV
fields in the WQE. Thus, BF may only be used for QPNs with bits 6,7
unset.
The current ethernet driver code reserves a TX QP range with 256b
alignment.
This is wrong because if there are more than 64 TX QPs in use, QPNs >=
base + 65 will have bits 6/7 set.
This problem is not specific for the Ethernet driver, any entity that
tries to reserve more than 64 BF-enabled QPs should fail. Also, using
ranges is not necessary here and is wasteful.
The new mechanism introduced here will support reservation for "Eth
QPs eligible for BF" for all drivers: bare-metal, multi-PF, and VFs
(when hypervisors support WC in VMs). The flow we use is:
1. In mlx4_en, allocate Tx QPs one by one instead of a range allocation,
and request "BF enabled QPs" if BF is supported for the function
2. In the ALLOC_RES FW command, change param1 to:
a. param1[23:0] - number of QPs
b. param1[31-24] - flags controlling QPs reservation
Bit 31 refers to Eth blueflame supported QPs. Those QPs must have bits
6 and 7 unset in order to be used in Ethernet.
Bits 24-30 of the flags are currently reserved.
When a function tries to allocate a QP, it states the required
attributes for this QP. Those attributes are considered "best-effort".
If an attribute, such as Ethernet BF enabled QP, is a must-have
attribute, the function has to check that attribute is supported
before trying to do the allocation.
In a lower layer of the code, mlx4_qp_reserve_range masks out the bits
which are unsupported. If SRIOV is used, the PF validates those
attributes and masks out unsupported attributes as well. In order to
notify VFs which attributes are supported, the VF uses QUERY_FUNC_CAP
command. This command's mailbox is filled by the PF, which notifies
which QP allocation attributes it supports.
Obtained from: Linux (dual BSD/GPLv2 licensed)
Submitted by: Dexuan Cui @ microsoft . com
Differential Revision: https://reviews.freebsd.org/D8868
MFC after: 2 weeks
Sponsored by: Mellanox Technologies
2017-02-10 15:28:18 +00:00
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u8 extra_flags;
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2011-03-21 09:58:24 +00:00
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};
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2017-02-10 15:22:21 +00:00
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struct mlx4_func {
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int bus;
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int device;
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int function;
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int physical_function;
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int rsvd_eqs;
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int max_eq;
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int rsvd_uars;
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};
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2011-03-21 09:58:24 +00:00
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struct mlx4_adapter {
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2014-09-23 12:37:01 +00:00
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u16 vsd_vendor_id;
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2011-03-21 09:58:24 +00:00
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char board_id[MLX4_BOARD_ID_LEN];
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2014-09-23 12:37:01 +00:00
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char vsd[MLX4_VSD_LEN];
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2011-03-21 09:58:24 +00:00
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u8 inta_pin;
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};
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struct mlx4_init_hca_param {
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u64 qpc_base;
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u64 rdmarc_base;
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u64 auxc_base;
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u64 altc_base;
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u64 srqc_base;
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u64 cqc_base;
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u64 eqc_base;
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u64 mc_base;
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u64 dmpt_base;
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u64 cmpt_base;
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u64 mtt_base;
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2013-09-29 00:35:03 +00:00
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u64 global_caps;
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2011-03-21 09:58:24 +00:00
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u16 log_mc_entry_sz;
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u16 log_mc_hash_sz;
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2013-09-29 00:35:03 +00:00
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u16 hca_core_clock;
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2011-03-21 09:58:24 +00:00
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u8 log_num_qps;
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u8 log_num_srqs;
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u8 log_num_cqs;
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u8 log_num_eqs;
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2017-02-10 15:22:21 +00:00
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u16 num_sys_eqs;
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2011-03-21 09:58:24 +00:00
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u8 log_rd_per_qp;
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u8 log_mc_table_sz;
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u8 log_mpt_sz;
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u8 log_uar_sz;
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2013-09-29 00:35:03 +00:00
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u8 uar_page_sz; /* log pg sz in 4k chunks */
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2014-09-23 12:37:01 +00:00
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u8 mw_enable; /* Enable memory windows */
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u8 fs_hash_enable_bits;
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2013-09-29 00:35:03 +00:00
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u8 steering_mode; /* for QUERY_HCA */
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u64 dev_cap_enabled;
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2011-03-21 09:58:24 +00:00
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};
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struct mlx4_init_ib_param {
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int port_width;
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int vl_cap;
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int mtu_cap;
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u16 gid_cap;
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u16 pkey_cap;
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int set_guid0;
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u64 guid0;
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int set_node_guid;
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u64 node_guid;
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int set_si_guid;
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u64 si_guid;
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};
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struct mlx4_set_ib_param {
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int set_si_guid;
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int reset_qkey_viol;
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u64 si_guid;
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u32 cap_mask;
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};
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int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
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2013-09-29 00:35:03 +00:00
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int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
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struct mlx4_func_cap *func_cap);
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int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
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struct mlx4_vhcr *vhcr,
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struct mlx4_cmd_mailbox *inbox,
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struct mlx4_cmd_mailbox *outbox,
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struct mlx4_cmd_info *cmd);
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2011-03-21 09:58:24 +00:00
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int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
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int mlx4_UNMAP_FA(struct mlx4_dev *dev);
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int mlx4_RUN_FW(struct mlx4_dev *dev);
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int mlx4_QUERY_FW(struct mlx4_dev *dev);
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int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
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int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
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2013-09-29 00:35:03 +00:00
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int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
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2011-03-21 09:58:24 +00:00
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int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
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int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
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int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
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int mlx4_NOP(struct mlx4_dev *dev);
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int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
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2017-02-10 15:22:21 +00:00
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int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave);
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2013-09-29 00:35:03 +00:00
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void mlx4_opreq_action(struct work_struct *work);
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2011-03-21 09:58:24 +00:00
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#endif /* MLX4_FW_H */
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