178 lines
7.1 KiB
C
178 lines
7.1 KiB
C
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/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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* NETLOGIC_BSD */
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#ifndef __NLM_BRIDGE_H__
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#define __NLM_BRIDGE_H__
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/**
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* @file_name mio.h
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* @author Netlogic Microsystems
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* @brief Basic definitions of XLP memory and io subsystem
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*/
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/* BRIDGE specific registers */
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#define XLP_BRIDGE_MODE_REG 0x40
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#define XLP_BRIDGE_PCI_CFG_BASE_REG 0x41
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#define XLP_BRIDGE_PCI_CFG_LIMIT_REG 0x42
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#define XLP_BRIDGE_PCIE_CFG_BASE_REG 0x43
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#define XLP_BRIDGE_PCIE_CFG_LIMIT_REG 0x44
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#define XLP_BRIDGE_BUSNUM_BAR0_REG 0x45
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#define XLP_BRIDGE_BUSNUM_BAR1_REG 0x46
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#define XLP_BRIDGE_BUSNUM_BAR2_REG 0x47
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#define XLP_BRIDGE_BUSNUM_BAR3_REG 0x48
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#define XLP_BRIDGE_BUSNUM_BAR4_REG 0x49
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#define XLP_BRIDGE_BUSNUM_BAR5_REG 0x4a
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#define XLP_BRIDGE_BUSNUM_BAR6_REG 0x4b
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#define XLP_BRIDGE_FLASH_BAR0_REG 0x4c
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#define XLP_BRIDGE_FLASH_BAR1_REG 0x4d
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#define XLP_BRIDGE_FLASH_BAR2_REG 0x4e
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#define XLP_BRIDGE_FLASH_BAR3_REG 0x4f
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#define XLP_BRIDGE_FLASH_LIMIT0_REG 0x50
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#define XLP_BRIDGE_FLASH_LIMIT1_REG 0x51
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#define XLP_BRIDGE_FLASH_LIMIT2_REG 0x52
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#define XLP_BRIDGE_FLASH_LIMIT3_REG 0x53
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#define XLP_BRIDGE_DRAM_BAR_REG(i) (0x54 + (i))
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#define XLP_BRIDGE_DRAM_BAR0_REG 0x54
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#define XLP_BRIDGE_DRAM_BAR1_REG 0x55
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#define XLP_BRIDGE_DRAM_BAR2_REG 0x56
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#define XLP_BRIDGE_DRAM_BAR3_REG 0x57
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#define XLP_BRIDGE_DRAM_BAR4_REG 0x58
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#define XLP_BRIDGE_DRAM_BAR5_REG 0x59
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#define XLP_BRIDGE_DRAM_BAR6_REG 0x5a
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#define XLP_BRIDGE_DRAM_BAR7_REG 0x5b
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#define XLP_BRIDGE_DRAM_LIMIT_REG(i) (0x5c + (i))
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#define XLP_BRIDGE_DRAM_LIMIT0_REG 0x5c
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#define XLP_BRIDGE_DRAM_LIMIT1_REG 0x5d
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#define XLP_BRIDGE_DRAM_LIMIT2_REG 0x5e
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#define XLP_BRIDGE_DRAM_LIMIT3_REG 0x5f
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#define XLP_BRIDGE_DRAM_LIMIT4_REG 0x60
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#define XLP_BRIDGE_DRAM_LIMIT5_REG 0x61
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#define XLP_BRIDGE_DRAM_LIMIT6_REG 0x62
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#define XLP_BRIDGE_DRAM_LIMIT7_REG 0x63
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN0_REG 0x64
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN1_REG 0x65
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN2_REG 0x66
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN3_REG 0x67
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN4_REG 0x68
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN5_REG 0x69
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN6_REG 0x6a
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#define XLP_BRIDGE_DRAM_NODE_TRANSLN7_REG 0x6b
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN0_REG 0x6c
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN1_REG 0x6d
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN2_REG 0x6e
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN3_REG 0x6f
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN4_REG 0x70
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN5_REG 0x71
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN6_REG 0x72
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#define XLP_BRIDGE_DRAM_CHNL_TRANSLN7_REG 0x73
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#define XLP_BRIDGE_PCIEMEM_BASE0_REG 0x74
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#define XLP_BRIDGE_PCIEMEM_BASE1_REG 0x75
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#define XLP_BRIDGE_PCIEMEM_BASE2_REG 0x76
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#define XLP_BRIDGE_PCIEMEM_BASE3_REG 0x77
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#define XLP_BRIDGE_PCIEMEM_LIMIT0_REG 0x78
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#define XLP_BRIDGE_PCIEMEM_LIMIT1_REG 0x79
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#define XLP_BRIDGE_PCIEMEM_LIMIT2_REG 0x7a
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#define XLP_BRIDGE_PCIEMEM_LIMIT3_REG 0x7b
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#define XLP_BRIDGE_PCIEIO_BASE0_REG 0x7c
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#define XLP_BRIDGE_PCIEIO_BASE1_REG 0x7d
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#define XLP_BRIDGE_PCIEIO_BASE2_REG 0x7e
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#define XLP_BRIDGE_PCIEIO_BASE3_REG 0x7f
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#define XLP_BRIDGE_PCIEIO_LIMIT0_REG 0x80
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#define XLP_BRIDGE_PCIEIO_LIMIT1_REG 0x81
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#define XLP_BRIDGE_PCIEIO_LIMIT2_REG 0x82
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#define XLP_BRIDGE_PCIEIO_LIMIT3_REG 0x83
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#define XLP_BRIDGE_PCIEMEM_BASE4_REG 0x84
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#define XLP_BRIDGE_PCIEMEM_BASE5_REG 0x85
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#define XLP_BRIDGE_PCIEMEM_BASE6_REG 0x86
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#define XLP_BRIDGE_PCIEMEM_LIMIT4_REG 0x87
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#define XLP_BRIDGE_PCIEMEM_LIMIT5_REG 0x88
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#define XLP_BRIDGE_PCIEMEM_LIMIT6_REG 0x89
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#define XLP_BRIDGE_PCIEIO_BASE4_REG 0x8a
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#define XLP_BRIDGE_PCIEIO_BASE5_REG 0x8b
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#define XLP_BRIDGE_PCIEIO_BASE6_REG 0x8c
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#define XLP_BRIDGE_PCIEIO_LIMIT4_REG 0x8d
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#define XLP_BRIDGE_PCIEIO_LIMIT5_REG 0x8e
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#define XLP_BRIDGE_PCIEIO_LIMIT6_REG 0x8f
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#define XLP_BRIDGE_NBU_EVENT_CNT_CTL_REG 0x90
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#define XLP_BRIDGE_EVNTCTR1_LOW_REG 0x91
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#define XLP_BRIDGE_EVNTCTR1_HI_REG 0x92
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#define XLP_BRIDGE_EVNT_CNT_CTL2_REG 0x93
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#define XLP_BRIDGE_EVNTCTR2_LOW_REG 0x94
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#define XLP_BRIDGE_EVNTCTR2_HI_REG 0x95
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#define XLP_BRIDGE_TRACEBUF_MATCH_REG0 0x96
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#define XLP_BRIDGE_TRACEBUF_MATCH_REG1 0x97
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#define XLP_BRIDGE_TRACEBUF_MATCH_LOW_REG 0x98
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#define XLP_BRIDGE_TRACEBUF_MATCH_HI_REG 0x99
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#define XLP_BRIDGE_TRACEBUF_CTRL_REG 0x9a
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#define XLP_BRIDGE_TRACEBUF_INIT_REG 0x9b
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#define XLP_BRIDGE_TRACEBUF_ACCESS_REG 0x9c
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#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG0 0x9d
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#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG1 0x9d
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#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG2 0x9f
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#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG3 0xa0
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#define XLP_BRIDGE_TRACEBUF_STATUS_REG 0xa1
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#define XLP_BRIDGE_ADDRESS_ERROR0_REG 0xa2
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#define XLP_BRIDGE_ADDRESS_ERROR1_REG 0xa3
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#define XLP_BRIDGE_ADDRESS_ERROR2_REG 0xa4
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#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR0_REG 0xa5
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#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR1_REG 0xa6
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#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR2_REG 0xa7
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#define XLP_BRIDGE_LINE_FLUSH_REG0 0xa8
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#define XLP_BRIDGE_LINE_FLUSH_REG1 0xa9
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#define XLP_BRIDGE_NODE_ID_REG 0xaa
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#define XLP_BRIDGE_ERROR_INTERRUPT_EN_REG 0xab
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#define XLP_BRIDGE_PCIE0_WEIGHT_REG 0x300
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#define XLP_BRIDGE_PCIE1_WEIGHT_REG 0x301
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#define XLP_BRIDGE_PCIE2_WEIGHT_REG 0x302
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#define XLP_BRIDGE_PCIE3_WEIGHT_REG 0x303
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#define XLP_BRIDGE_USB_WEIGHT_REG 0x304
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#define XLP_BRIDGE_NET_WEIGHT_REG 0x305
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#define XLP_BRIDGE_POE_WEIGHT_REG 0x306
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#define XLP_BRIDGE_CMS_WEIGHT_REG 0x307
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#define XLP_BRIDGE_DMAENG_WEIGHT_REG 0x308
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#define XLP_BRIDGE_SEC_WEIGHT_REG 0x309
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#define XLP_BRIDGE_COMP_WEIGHT_REG 0x30a
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#define XLP_BRIDGE_GIO_WEIGHT_REG 0x30b
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#define XLP_BRIDGE_FLASH_WEIGHT_REG 0x30c
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_rdreg_bridge(b, r) nlm_read_reg_kseg(b, r)
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#define nlm_wreg_bridge(b, r, v) nlm_write_reg_kseg(b, r, v)
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#define nlm_pcibase_bridge(node) nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
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#define nlm_regbase_bridge(node) nlm_pcibase_bridge(node)
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#endif
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#endif
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