126 lines
4.8 KiB
C
126 lines
4.8 KiB
C
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/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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* NETLOGIC_BSD */
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#ifndef __NLM_SYS_H__
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#define __NLM_SYS_H__
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/**
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* @file_name sys.h
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* @author Netlogic Microsystems
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* @brief HAL for System configuration registers
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*/
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#define XLP_SYS_CHIP_RESET_REG 0x40
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#define XLP_SYS_POWER_ON_RESET_REG 0x41
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#define XLP_SYS_EFUSE_DEVICE_CFG_STATUS0_REG 0x42
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#define XLP_SYS_EFUSE_DEVICE_CFG_STATUS1_REG 0x43
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#define XLP_SYS_EFUSE_DEVICE_CFG_STATUS2_REG 0x44
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#define XLP_SYS_EFUSE_DEVICE_CFG3_REG 0x45
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#define XLP_SYS_EFUSE_DEVICE_CFG4_REG 0x46
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#define XLP_SYS_EFUSE_DEVICE_CFG5_REG 0x47
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#define XLP_SYS_EFUSE_DEVICE_CFG6_REG 0x48
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#define XLP_SYS_EFUSE_DEVICE_CFG7_REG 0x49
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#define XLP_SYS_PLL_CTRL_REG 0x4a
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#define XLP_SYS_CPU_RESET_REG 0x4b
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#define XLP_SYS_CPU_NONCOHERENT_MODE_REG 0x4d
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#define XLP_SYS_CORE_DFS_DIS_CTRL_REG 0x4e
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#define XLP_SYS_CORE_DFS_RST_CTRL_REG 0x4f
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#define XLP_SYS_CORE_DFS_BYP_CTRL_REG 0x50
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#define XLP_SYS_CORE_DFS_PHA_CTRL_REG 0x51
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#define XLP_SYS_CORE_DFS_DIV_INC_CTRL_REG 0x52
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#define XLP_SYS_CORE_DFS_DIV_DEC_CTRL_REG 0x53
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#define XLP_SYS_CORE_DFS_DIV_VALUE_REG 0x54
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#define XLP_SYS_RESET_REG 0x55
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#define XLP_SYS_DFS_DIS_CTRL_REG 0x56
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#define XLP_SYS_DFS_RST_CTRL_REG 0x57
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#define XLP_SYS_DFS_BYP_CTRL_REG 0x58
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#define XLP_SYS_DFS_DIV_INC_CTRL_REG 0x59
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#define XLP_SYS_DFS_DIV_DEC_CTRL_REG 0x5a
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#define XLP_SYS_DFS_DIV_VALUE0_REG 0x5b
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#define XLP_SYS_DFS_DIV_VALUE1_REG 0x5c
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#define XLP_SYS_SENSE_AMP_DLY_REG 0x5d
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#define XLP_SYS_SOC_SENSE_AMP_DLY_REG 0x5e
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#define XLP_SYS_CTRL0_REG 0x5f
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#define XLP_SYS_CTRL1_REG 0x60
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#define XLP_SYS_TIMEOUT_BS1_REG 0x61
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#define XLP_SYS_BYTE_SWAP_REG 0x62
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#define XLP_SYS_VRM_VID_REG 0x63
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#define XLP_SYS_PWR_RAM_CMD_REG 0x64
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#define XLP_SYS_PWR_RAM_ADDR_REG 0x65
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#define XLP_SYS_PWR_RAM_DATA0_REG 0x66
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#define XLP_SYS_PWR_RAM_DATA1_REG 0x67
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#define XLP_SYS_PWR_RAM_DATA2_REG 0x68
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#define XLP_SYS_PWR_UCODE_REG 0x69
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#define XLP_SYS_CPU0_PWR_STATUS_REG 0x6a
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#define XLP_SYS_CPU1_PWR_STATUS_REG 0x6b
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#define XLP_SYS_CPU2_PWR_STATUS_REG 0x6c
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#define XLP_SYS_CPU3_PWR_STATUS_REG 0x6d
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#define XLP_SYS_CPU4_PWR_STATUS_REG 0x6e
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#define XLP_SYS_CPU5_PWR_STATUS_REG 0x6f
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#define XLP_SYS_CPU6_PWR_STATUS_REG 0x70
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#define XLP_SYS_CPU7_PWR_STATUS_REG 0x71
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#define XLP_SYS_STATUS_REG 0x72
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#define XLP_SYS_INT_POL_REG 0x73
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#define XLP_SYS_INT_TYPE_REG 0x74
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#define XLP_SYS_INT_STATUS_REG 0x75
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#define XLP_SYS_INT_MASK0_REG 0x76
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#define XLP_SYS_INT_MASK1_REG 0x77
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#define XLP_SYS_UCO_S_ECC_REG 0x78
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#define XLP_SYS_UCO_M_ECC_REG 0x79
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#define XLP_SYS_UCO_ADDR_REG 0x7a
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#define XLP_SYS_UCO_INSTR_REG 0x7b
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#define XLP_SYS_MEM_BIST0_REG 0x7c
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#define XLP_SYS_MEM_BIST1_REG 0x7d
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#define XLP_SYS_MEM_BIST2_REG 0x7e
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#define XLP_SYS_MEM_BIST3_REG 0x7f
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#define XLP_SYS_MEM_BIST4_REG 0x80
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#define XLP_SYS_MEM_BIST5_REG 0x81
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#define XLP_SYS_MEM_BIST6_REG 0x82
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#define XLP_SYS_MEM_BIST7_REG 0x83
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#define XLP_SYS_MEM_BIST8_REG 0x84
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#define XLP_SYS_MEM_BIST9_REG 0x85
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#define XLP_SYS_MEM_BIST10_REG 0x86
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#define XLP_SYS_MEM_BIST11_REG 0x87
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#define XLP_SYS_MEM_BIST12_REG 0x88
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#define XLP_SYS_SCRTCH0_REG 0x89
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#define XLP_SYS_SCRTCH1_REG 0x8a
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#define XLP_SYS_SCRTCH2_REG 0x8b
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#define XLP_SYS_SCRTCH3_REG 0x8c
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_rdreg_sys(b, r) nlm_read_reg_kseg(b,r)
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#define nlm_wreg_sys(b, r, v) nlm_write_reg_kseg(b,r,v)
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#define nlm_pcibase_sys(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
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#define nlm_regbase_sys(node) nlm_pcibase_sys(node)
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#endif
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#endif
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