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freebsd-dev/sys/dev/bhnd/bhndb/bhndb_pcivar.h

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Bring over the initial rewrite of the broadcom bus support found in their SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
2016-02-26 03:34:08 +00:00
/*-
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
* Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
* Copyright (c) 2017 The FreeBSD Foundation
Bring over the initial rewrite of the broadcom bus support found in their SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
2016-02-26 03:34:08 +00:00
* All rights reserved.
*
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
* Portions of this software were developed by Landon Fuller
* under sponsorship from the FreeBSD Foundation.
*
Bring over the initial rewrite of the broadcom bus support found in their SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
2016-02-26 03:34:08 +00:00
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
#ifndef _BHND_BHNDB_PCIVAR_H_
#define _BHND_BHNDB_PCIVAR_H_
#include "bhndbvar.h"
/*
* bhndb(4) PCI driver subclass.
*/
DECLARE_CLASS(bhndb_pci_driver);
struct bhndb_pci_softc;
/*
* An interconnect-specific function implementing BHNDB_SET_WINDOW_ADDR
*/
bhnd: Add support for supplying bus I/O callbacks when initializing an EROM parser. This allows us to use the EROM parser API in cases where the standard bus space I/O APIs are unsuitable. In particular, this will allow us to parse the device enumeration table directly from bhndb(4) drivers, prior to full attach and configuration of the bridge. Approved by: adrian (mentor) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12510
2017-09-27 19:48:34 +00:00
typedef int (*bhndb_pci_set_regwin_t)(device_t dev, device_t pci_dev,
Bring over the initial rewrite of the broadcom bus support found in their SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
2016-02-26 03:34:08 +00:00
const struct bhndb_regwin *rw, bhnd_addr_t addr);
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
/**
* PCI/PCIe bridge-level device quirks
*/
enum {
/** No quirks */
BHNDB_PCI_QUIRK_NONE = 0,
/**
* The core requires fixup of the BAR0 SROM shadow to point at the
* current PCI core.
*/
BHNDB_PCI_QUIRK_SRSH_WAR = (1<<0),
/**
* The PCI (rev <= 5) core does not provide interrupt status/mask
* registers; these siba-only devices require routing backplane
* interrupt flags via the SIBA_CFG0_INTVEC register.
*/
BHNDB_PCI_QUIRK_SIBA_INTVEC = (1<<1),
bhnd(4): Implement backplane interrupt handling. This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit)
2016-09-05 22:11:46 +00:00
};
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
/** bhndb_pci quirk table entry */
struct bhndb_pci_quirk {
struct bhnd_chip_match chip_desc; /**< chip match descriptor */
struct bhnd_core_match core_desc; /**< core match descriptor */
uint32_t quirks; /**< quirk flags */
};
#define BHNDB_PCI_QUIRK(_rev, _flags) { \
{ BHND_MATCH_ANY }, \
{ BHND_MATCH_CORE_REV(_rev) }, \
_flags, \
}
#define BHNDB_PCI_QUIRK_END \
{ { BHND_MATCH_ANY }, { BHND_MATCH_ANY }, 0 }
#define BHNDB_PCI_IS_QUIRK_END(_q) \
(BHND_MATCH_IS_ANY(&(_q)->core_desc) && \
BHND_MATCH_IS_ANY(&(_q)->chip_desc) && \
(_q)->quirks == 0)
/** bhndb_pci core table entry */
struct bhndb_pci_core {
struct bhnd_core_match match; /**< core match descriptor */
struct bhndb_pci_quirk *quirks; /**< quirk table */
};
bhndb_pci(4): fix incorrect BHND_PCI_SRSH_PI workaround On a SPROM-less device, the PCI(e) bridge core will be initialized with its power-on-reset defaults; this can leave the SPROM-derived BHND_PCI_SRSH_PI value pointing to the wrong backplane address. This value is used by the PCI core when performing address translation between the static register windows in BAR0 that map the PCI core's register block, and backplane address space. Previously, bhndb_pci(4) incorrectly used the potentially invalid static BAR0 PCI register windows when attempting to correct the BHND_PCI_SRSH_PI value in the PCI core's SPROM shadow. Instead, we now read/update BHND_PCI_SRSH_PI by fetching the PCI core's backplane address from the core enumeration table, and then using a dynamic register window to explicitly map the PCI core's register block into BAR0. Sponsored by: The FreeBSD Foundation
2018-01-17 03:34:26 +00:00
#define BHNDB_PCI_CORE(_device, _quirks) { \
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
{ BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_ ## _device) }, \
_quirks \
}
bhndb_pci(4): fix incorrect BHND_PCI_SRSH_PI workaround On a SPROM-less device, the PCI(e) bridge core will be initialized with its power-on-reset defaults; this can leave the SPROM-derived BHND_PCI_SRSH_PI value pointing to the wrong backplane address. This value is used by the PCI core when performing address translation between the static register windows in BAR0 that map the PCI core's register block, and backplane address space. Previously, bhndb_pci(4) incorrectly used the potentially invalid static BAR0 PCI register windows when attempting to correct the BHND_PCI_SRSH_PI value in the PCI core's SPROM shadow. Instead, we now read/update BHND_PCI_SRSH_PI by fetching the PCI core's backplane address from the core enumeration table, and then using a dynamic register window to explicitly map the PCI core's register block into BAR0. Sponsored by: The FreeBSD Foundation
2018-01-17 03:34:26 +00:00
#define BHNDB_PCI_CORE_END { { BHND_MATCH_ANY }, NULL }
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
#define BHNDB_PCI_IS_CORE_END(_c) BHND_MATCH_IS_ANY(&(_c)->match)
Bring over the initial rewrite of the broadcom bus support found in their SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
2016-02-26 03:34:08 +00:00
struct bhndb_pci_softc {
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
struct bhndb_softc bhndb; /**< parent softc */
device_t dev; /**< bridge device */
device_t parent; /**< parent PCI device */
bhnd_devclass_t pci_devclass; /**< PCI core's devclass */
uint32_t pci_quirks; /**< PCI bridge-level quirks */
int msi_count; /**< MSI count, or 0 */
struct bhndb_intr_isrc *isrc; /**< host interrupt source */
bhnd(4): Implement backplane interrupt handling. This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit)
2016-09-05 22:11:46 +00:00
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
struct mtx mtx;
bhndb_pci_set_regwin_t set_regwin; /**< regwin handler */
Bring over the initial rewrite of the broadcom bus support found in their SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
2016-02-26 03:34:08 +00:00
};
bhnd(4): implement MIPS and PCI(e) interrupt support On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
#define BHNDB_PCI_LOCK_INIT(sc) \
mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
"bhndb_pc state", MTX_DEF)
#define BHNDB_PCI_LOCK(sc) mtx_lock(&(sc)->mtx)
#define BHNDB_PCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
#define BHNDB_PCI_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
#define BHNDB_PCI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
[bhnd] Add a common bhnd_pci driver shared by both bhnd_pcib and bhnd_pci_hostb This extracts common code from bhndb_pci, bhnd_pcib, and bhnd_pci_hostb into a simpler shared bhnd_pci base driver, and should enable SoC-side implementation of bhnd_pcib root complex support. Submitted by: Landon Fuller <landonf@landonf.org> Differential Revision: https://reviews.freebsd.org/D5763
2016-04-22 16:26:53 +00:00
#endif /* _BHND_BHNDB_PCIVAR_H_ */
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