66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
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//===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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namespace llvm {
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class SIRegisterInfo;
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class TargetRegisterInfo;
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namespace AMDGPU {
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enum {
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SGPRRegBankID = 0,
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VGPRRegBankID = 1,
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NumRegisterBanks
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};
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} // End AMDGPU namespace.
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/// This class provides the information for the target register banks.
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class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
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protected:
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#define GET_TARGET_REGBANK_CLASS
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#include "AMDGPUGenRegisterBank.inc"
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};
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class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
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const SIRegisterInfo *TRI;
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/// See RegisterBankInfo::applyMapping.
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void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
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RegisterBankInfo::InstructionMapping
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getInstrMappingForLoad(const MachineInstr &MI) const;
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public:
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AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
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unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
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unsigned Size) const override;
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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InstructionMappings
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getInstrAlternativeMappings(const MachineInstr &MI) const override;
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InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
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};
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} // End llvm namespace.
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#endif
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