270 lines
11 KiB
C
270 lines
11 KiB
C
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//===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariables analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using a sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEVARIABLES_H
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#define LLVM_CODEGEN_LIVEVARIABLES_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseBitVector.h"
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namespace llvm {
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class MachineRegisterInfo;
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class TargetRegisterInfo;
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class LiveVariables : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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LiveVariables() : MachineFunctionPass(&ID) {}
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/// VarInfo - This represents the regions where a virtual register is live in
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/// the program. We represent this with three different pieces of
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/// information: the set of blocks in which the instruction is live
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/// throughout, the set of blocks in which the instruction is actually used,
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/// and the set of non-phi instructions that are the last users of the value.
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///
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/// In the common case where a value is defined and killed in the same block,
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/// There is one killing instruction, and AliveBlocks is empty.
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///
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/// Otherwise, the value is live out of the block. If the value is live
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/// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
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/// where the liveness range ends are not included in AliveBlocks, instead
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/// being captured by the Kills set. In these blocks, the value is live into
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/// the block (unless the value is defined and killed in the same block) and
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/// lives until the specified instruction. Note that there cannot ever be a
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/// value whose Kills set contains two instructions from the same basic block.
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///
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/// PHI nodes complicate things a bit. If a PHI node is the last user of a
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/// value in one of its predecessor blocks, it is not listed in the kills set,
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/// but does include the predecessor block in the AliveBlocks set (unless that
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/// block also defines the value). This leads to the (perfectly sensical)
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/// situation where a value is defined in a block, and the last use is a phi
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/// node in the successor. In this case, AliveBlocks is empty (the value is
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/// not live across any blocks) and Kills is empty (phi nodes are not
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/// included). This is sensical because the value must be live to the end of
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/// the block, but is not live in any successor blocks.
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struct VarInfo {
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/// AliveBlocks - Set of blocks in which this value is alive completely
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/// through. This is a bit set which uses the basic block number as an
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/// index.
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///
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SparseBitVector<> AliveBlocks;
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/// NumUses - Number of uses of this register across the entire function.
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///
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unsigned NumUses;
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/// Kills - List of MachineInstruction's which are the last use of this
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/// virtual register (kill it) in their basic block.
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///
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std::vector<MachineInstr*> Kills;
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VarInfo() : NumUses(0) {}
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/// removeKill - Delete a kill corresponding to the specified
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/// machine instruction. Returns true if there was a kill
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/// corresponding to this instruction, false otherwise.
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bool removeKill(MachineInstr *MI) {
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std::vector<MachineInstr*>::iterator
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I = std::find(Kills.begin(), Kills.end(), MI);
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if (I == Kills.end())
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return false;
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Kills.erase(I);
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return true;
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}
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void dump() const;
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};
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private:
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/// VirtRegInfo - This list is a mapping from virtual register number to
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/// variable information. FirstVirtualRegister is subtracted from the virtual
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/// register number before indexing into this list.
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///
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std::vector<VarInfo> VirtRegInfo;
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/// ReservedRegisters - This vector keeps track of which registers
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/// are reserved register which are not allocatable by the target machine.
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/// We can not track liveness for values that are in this set.
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///
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BitVector ReservedRegisters;
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private: // Intermediate data structures
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MachineFunction *MF;
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MachineRegisterInfo* MRI;
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const TargetRegisterInfo *TRI;
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// PhysRegInfo - Keep track of which instruction was the last def of a
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// physical register. This is a purely local property, because all physical
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// register references are presumed dead across basic blocks.
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MachineInstr **PhysRegDef;
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// PhysRegInfo - Keep track of which instruction was the last use of a
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// physical register. This is a purely local property, because all physical
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// register references are presumed dead across basic blocks.
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MachineInstr **PhysRegUse;
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SmallVector<unsigned, 4> *PHIVarInfo;
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
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/// uses. Pay special attention to the sub-register uses which may come below
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/// the last use of the whole register.
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bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
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void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
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void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
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/// FindLastPartialDef - Return the last partial def of the specified register.
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/// Also returns the sub-register that's defined.
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MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
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/// hasRegisterUseBelow - Return true if the specified register is used after
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/// the current instruction and before it's next definition.
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bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
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MachineBasicBlock *MBB);
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/// analyzePHINodes - Gather information about the PHI nodes in here. In
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/// particular, we want to map the variable information of a virtual
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/// register which is used in a PHI node. We map that to the BB the vreg
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/// is coming from.
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void analyzePHINodes(const MachineFunction& Fn);
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public:
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virtual bool runOnMachineFunction(MachineFunction &MF);
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/// RegisterDefIsDead - Return true if the specified instruction defines the
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/// specified register, but that definition is dead.
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bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
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//===--------------------------------------------------------------------===//
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// API to update live variable information
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/// replaceKillInstruction - Update register kill info by replacing a kill
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/// instruction with a new one.
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void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
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MachineInstr *NewMI);
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/// addVirtualRegisterKilled - Add information about the fact that the
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/// specified register is killed after being used by the specified
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/// instruction. If AddIfNotFound is true, add a implicit operand if it's
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/// not found.
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void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
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bool AddIfNotFound = false) {
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if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
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getVarInfo(IncomingReg).Kills.push_back(MI);
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}
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/// removeVirtualRegisterKilled - Remove the specified kill of the virtual
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/// register from the live variable information. Returns true if the
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/// variable was marked as killed by the specified instruction,
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/// false otherwise.
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bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
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if (!getVarInfo(reg).removeKill(MI))
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return false;
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bool Removed = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
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MO.setIsKill(false);
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Removed = true;
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break;
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}
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}
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assert(Removed && "Register is not used by this instruction!");
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return true;
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}
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/// removeVirtualRegistersKilled - Remove all killed info for the specified
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/// instruction.
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void removeVirtualRegistersKilled(MachineInstr *MI);
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/// addVirtualRegisterDead - Add information about the fact that the specified
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/// register is dead after being used by the specified instruction. If
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/// AddIfNotFound is true, add a implicit operand if it's not found.
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void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
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bool AddIfNotFound = false) {
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if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
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getVarInfo(IncomingReg).Kills.push_back(MI);
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}
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/// removeVirtualRegisterDead - Remove the specified kill of the virtual
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/// register from the live variable information. Returns true if the
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/// variable was marked dead at the specified instruction, false
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/// otherwise.
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bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
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if (!getVarInfo(reg).removeKill(MI))
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return false;
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bool Removed = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
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MO.setIsDead(false);
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Removed = true;
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break;
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}
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}
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assert(Removed && "Register is not defined by this instruction!");
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return true;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory() {
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VirtRegInfo.clear();
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}
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/// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
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/// register.
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VarInfo &getVarInfo(unsigned RegIdx);
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void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
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MachineBasicBlock *BB);
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void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
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MachineBasicBlock *BB,
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std::vector<MachineBasicBlock*> &WorkList);
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void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
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void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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MachineInstr *MI);
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};
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} // End llvm namespace
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#endif
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