2012-07-26 08:01:25 +00:00
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/*-
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* Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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* Copyright (c) 2012 Andrew Turner. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef AT91SAM9G45REG_H_
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#define AT91SAM9G45REG_H_
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/* Chip Specific limits */
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#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
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#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
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#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
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#define SAM9G45_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
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#define SAM9G45_PLL_A_MUL_SHIFT 16
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#define SAM9G45_PLL_A_MUL_MASK 0xFF
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#define SAM9G45_PLL_A_DIV_SHIFT 0
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#define SAM9G45_PLL_A_DIV_MASK 0xFF
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/*
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* Memory map, from datasheet :
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* 0x00000000 - 0x0ffffffff : Internal Memories
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* 0x10000000 - 0x1ffffffff : Chip Select 0
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* 0x20000000 - 0x2ffffffff : Chip Select 1
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* 0x30000000 - 0x3ffffffff : Chip Select 2
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* 0x40000000 - 0x4ffffffff : Chip Select 3
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* 0x50000000 - 0x5ffffffff : Chip Select 4
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* 0x60000000 - 0x6ffffffff : Chip Select 5
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* 0x70000000 - 0x7ffffffff : DDR SDRC 0
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* 0x80000000 - 0xeffffffff : Undefined (Abort)
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* 0xf0000000 - 0xfffffffff : Peripherals
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*/
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#define AT91_CHIPSELECT_0 0x10000000
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#define AT91_CHIPSELECT_1 0x20000000
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#define AT91_CHIPSELECT_2 0x30000000
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#define AT91_CHIPSELECT_3 0x40000000
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#define AT91_CHIPSELECT_4 0x50000000
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#define AT91_CHIPSELECT_5 0x60000000
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#define AT91SAM9G45_EMAC_BASE 0xffbc000
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#define AT91SAM9G45_EMAC_SIZE 0x4000
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#define AT91SAM9G45_RSTC_BASE 0xffffd00
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#define AT91SAM9G45_RSTC_SIZE 0x10
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/* USART*/
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#define AT91SAM9G45_USART_SIZE 0x4000
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#define AT91SAM9G45_USART0_BASE 0xff8c000
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#define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE
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#define AT91SAM9G45_USART1_BASE 0xff90000
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#define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE
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#define AT91SAM9G45_USART2_BASE 0xff94000
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#define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE
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#define AT91SAM9G45_USART3_BASE 0xff98000
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#define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE
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/*TC*/
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#define AT91SAM9G45_TC0_BASE 0xff7c000
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#define AT91SAM9G45_TC0_SIZE 0x4000
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#define AT91SAM9G45_TC0C0_BASE 0xff7c000
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#define AT91SAM9G45_TC0C1_BASE 0xff7c040
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#define AT91SAM9G45_TC0C2_BASE 0xff7c080
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#define AT91SAM9G45_TC1_BASE 0xffd4000
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#define AT91SAM9G45_TC1_SIZE 0x4000
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#define AT91SAM9G45_TC1C0_BASE 0xffd4000
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#define AT91SAM9G45_TC1C1_BASE 0xffd4040
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#define AT91SAM9G45_TC1C2_BASE 0xffd4080
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/*SPI*/
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#define AT91SAM9G45_SPI0_BASE 0xffa48000
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#define AT91SAM9G45_SPI0_SIZE 0x4000
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#define AT91SAM9G45_SPI1_BASE 0xffa8000
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#define AT91SAM9G45_SPI1_SIZE 0x4000
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/* System Registers */
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#define AT91SAM9G45_SYS_BASE 0xffff000
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#define AT91SAM9G45_SYS_SIZE 0x1000
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#define AT91SAM9G45_MATRIX_BASE 0xfffea00
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#define AT91SAM9G45_MATRIX_SIZE 0x200
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#define AT91SAM9G45_DBGU_BASE 0xfffee00
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#define AT91SAM9G45_DBGU_SIZE 0x200
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/*
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* PIO
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*/
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#define AT91SAM9G45_PIOA_BASE 0xffff200
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#define AT91SAM9G45_PIOA_SIZE 0x200
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#define AT91SAM9G45_PIOB_BASE 0xffff400
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#define AT91SAM9G45_PIOB_SIZE 0x200
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#define AT91SAM9G45_PIOC_BASE 0xffff600
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#define AT91SAM9G45_PIOC_SIZE 0x200
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#define AT91SAM9G45_PIOD_BASE 0xffff800
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#define AT91SAM9G45_PIOD_SIZE 0x200
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#define AT91SAM9G45_PIOE_BASE 0xffffa00
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#define AT91SAM9G45_PIOE_SIZE 0x200
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#define AT91SAM9G45_PMC_BASE 0xffffc00
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#define AT91SAM9G45_PMC_SIZE 0x100
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/* IRQs : */
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/*
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* 0: AIC
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* 1: System peripheral (System timer, RTC, DBGU)
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* 2: PIO Controller A
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* 3: PIO Controller B
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* 4: PIO Controller C
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* 5: PIO Controller D/E
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* 6: TRNG
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* 7: USART 0
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* 8: USART 1
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* 9: USART 2
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* 10: USART 3
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* 11: Multimedia Card interface 0
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* 12: Two-wirte interface 0
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* 13: Two-wirte interface 1
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* 14: SPI 0
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* 15: SPI 1
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* 16: SSC 0
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* 17: SSC 0
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* 18: Timer Counter 0, 2, 3, 4, 5
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* 19: PWM
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* 20: Touch Screen ADC
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* 21: DMA
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* 22: USB Host port
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* 23: LCD
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* 24: AC97
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* 25: EMAC
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* 26: Image Sensor Interface
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* 27: USB Device High Speed
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* 28: -
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* 29: Multimedia Card interface 1
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* 30: Reserved
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* 31: AIC
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*/
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#define AT91SAM9G45_IRQ_SYSTEM 1
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#define AT91SAM9G45_IRQ_PIOA 2
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#define AT91SAM9G45_IRQ_PIOB 3
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#define AT91SAM9G45_IRQ_PIOC 4
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#define AT91SAM9G45_IRQ_PIOD 5
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#define AT91SAM9G45_IRQ_PIOE 6
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#define AT91SAM9G45_IRQ_USART0 7
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#define AT91SAM9G45_IRQ_USART1 8
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#define AT91SAM9G45_IRQ_USART2 9
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#define AT91SAM9G45_IRQ_USART3 10
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#define AT91SAM9G45_IRQ_HSMCI0 11
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#define AT91SAM9G45_IRQ_TWI0 12
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#define AT91SAM9G45_IRQ_TWI1 13
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#define AT91SAM9G45_IRQ_SPI0 14
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#define AT91SAM9G45_IRQ_SPI1 15
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#define AT91SAM9G45_IRQ_SSC0 16
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#define AT91SAM9G45_IRQ_SSC1 17
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#define AT91SAM9G45_IRQ_TC0_TC5 18
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#define AT91SAM9G45_IRQ_PWM 19
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#define AT91SAM9G45_IRQ_TSADCC 20
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#define AT91SAM9G45_IRQ_DMA 21
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#define AT91SAM9G45_IRQ_UHP 22
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#define AT91SAM9G45_IRQ_LCDC 23
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#define AT91SAM9G45_IRQ_AC97C 24
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#define AT91SAM9G45_IRQ_EMAC 25
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#define AT91SAM9G45_IRQ_ISI 26
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#define AT91SAM9G45_IRQ_UDPHS 27
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/* Reserved 28 */
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#define AT91SAM9G45_IRQ_HSMCI1 29
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/* Reserved 30 */
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#define AT91SAM9G45_IRQ_AICBASE 31
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/* Alias */
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#define AT91SAM9G45_IRQ_DBGU AT91SAM9G45_IRQ_SYSTEM
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#define AT91SAM9G45_IRQ_PMC AT91SAM9G45_IRQ_SYSTEM
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#define AT91SAM9G45_IRQ_WDT AT91SAM9G45_IRQ_SYSTEM
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#define AT91SAM9G45_IRQ_PIT AT91SAM9G45_IRQ_SYSTEM
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#define AT91SAM9G45_IRQ_RSTC AT91SAM9G45_IRQ_SYSTEM
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#define AT91SAM9G45_IRQ_OHCI AT91SAM9G45_IRQ_UHP
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#define AT91SAM9G45_IRQ_TC0 AT91SAM9G45_IRQ_TC0_TC5
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#define AT91SAM9G45_IRQ_TC1 AT91SAM9G45_IRQ_TC0_TC5
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#define AT91SAM9G45_IRQ_TC2 AT91SAM9G45_IRQ_TC0_TC5
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#define AT91SAM9G45_IRQ_TC3 AT91SAM9G45_IRQ_TC0_TC5
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#define AT91SAM9G45_IRQ_TC4 AT91SAM9G45_IRQ_TC0_TC5
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#define AT91SAM9G45_IRQ_TC5 AT91SAM9G45_IRQ_TC0_TC5
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#define AT91SAM9G45_IRQ_NAND (-1)
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#define AT91SAM9G45_AIC_BASE 0xffff000
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#define AT91SAM9G45_AIC_SIZE 0x200
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/* Timer */
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#define AT91SAM9G45_WDT_BASE 0xffffd40
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#define AT91SAM9G45_WDT_SIZE 0x10
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#define AT91SAM9G45_PIT_BASE 0xffffd30
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#define AT91SAM9G45_PIT_SIZE 0x10
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#define AT91SAM9G45_SMC_BASE 0xfffe800
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#define AT91SAM9G45_SMC_SIZE 0x200
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#define AT91SAM9G45_PMC_BASE 0xffffc00
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#define AT91SAM9G45_PMC_SIZE 0x100
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#define AT91SAM9G45_HSMCI0_BASE 0xff80000
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#define AT91SAM9G45_HSMCI0_SIZE 0x4000
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#define AT91SAM9G45_HSMCI1_BASE 0xffd0000
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#define AT91SAM9G45_HSMCI1_SIZE 0x4000
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#define AT91SAM9G45_TWI0_BASE 0xff84000
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#define AT91SAM9G45_TWI0_SIZE 0x4000
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#define AT91SAM9G45_TWI1_BASE 0xff88000
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#define AT91SAM9G45_TWI1_SIZE 0x4000
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/* XXX Needs to be carfully coordinated with
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* other * soc's so phyical and vm address
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* mapping are unique. XXX
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*/
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2014-01-31 15:38:05 +00:00
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#define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000
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#define AT91SAM9G45_OHCI_BASE 0x00700000
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#define AT91SAM9G45_OHCI_SIZE 0x00100000
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2012-07-26 08:01:25 +00:00
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2014-01-31 15:38:05 +00:00
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#define AT91SAM9G45_NAND_VA_BASE 0xe0000000
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#define AT91SAM9G45_NAND_BASE 0x40000000
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#define AT91SAM9G45_NAND_SIZE 0x10000000
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2012-07-26 08:01:25 +00:00
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/* DDRSDRC */
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#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00
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#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600
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#define AT91SAM9G45_DDRSDRC_MR 0x00
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#define AT91SAM9G45_DDRSDRC_TR 0x04
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#define AT91SAM9G45_DDRSDRC_CR 0x08
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#define AT91SAM9G45_DDRSDRC_CR_NC_8 0x0
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#define AT91SAM9G45_DDRSDRC_CR_NC_9 0x1
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#define AT91SAM9G45_DDRSDRC_CR_NC_10 0x2
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#define AT91SAM9G45_DDRSDRC_CR_NC_11 0x3
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#define AT91SAM9G45_DDRSDRC_CR_NC_MASK 0x00000003
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#define AT91SAM9G45_DDRSDRC_CR_NR_11 0x0
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#define AT91SAM9G45_DDRSDRC_CR_NR_12 0x4
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#define AT91SAM9G45_DDRSDRC_CR_NR_13 0x8
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#define AT91SAM9G45_DDRSDRC_CR_NR_14 0xc
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#define AT91SAM9G45_DDRSDRC_CR_NR_MASK 0x0000000c
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#define AT91SAM9G45_DDRSDRC_TPR0 0x0c
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#define AT91SAM9G45_DDRSDRC_TPR1 0x10
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#define AT91SAM9G45_DDRSDRC_TPR2 0x14
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/* Reserved 0x18 */
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#define AT91SAM9G45_DDRSDRC_LPR 0x1c
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#define AT91SAM9G45_DDRSDRC_MDR 0x20
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#define AT91SAM9G45_DDRSDRC_MDR_SDR 0x0
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#define AT91SAM9G45_DDRSDRC_MDR_LPSDR 0x1
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#define AT91SAM9G45_DDRSDRC_MDR_LPDDR1 0x3
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#define AT91SAM9G45_DDRSDRC_MDR_DDR2 0x6
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#define AT91SAM9G45_DDRSDRC_MDR_MASK 0x00000007
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#define AT91SAM9G45_DDRSDRC_MDR_DBW_16 0x10
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#define AT91SAM9G45_DDRSDRC_DLL 0x24
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#define AT91SAM9G45_DDRSDRC_HSR 0x2c
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#define AT91SAM9G45_DDRSDRC_DELAY1R 0x40
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#define AT91SAM9G45_DDRSDRC_DELAY2R 0x44
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#define AT91SAM9G45_DDRSDRC_DELAY3R 0x48
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#define AT91SAM9G45_DDRSDRC_DELAY4R 0x4c
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/* Reserved 0x50 - 0xe0 */
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#define AT91SAM9G45_DDRSDRC_WPMR 0xe4
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#define AT91SAM9G45_DDRSDRC_WPSR 0xe8
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#endif /* AT91SAM9G45REG_H_*/
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