2016-03-16 13:01:48 +00:00
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/*-
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* Copyright (c) 2015 Michal Meloun
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/nvidia/tegra_efuse.h>
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#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_sc)->fuse_begin + (_r))
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-efuse", 1},
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{NULL, 0}
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};
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struct tegra_efuse_softc {
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device_t dev;
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struct resource *mem_res;
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int fuse_begin;
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clk_t clk;
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hwreset_t reset;
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};
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struct tegra_efuse_softc *dev_sc;
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struct tegra_sku_info tegra_sku_info;
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static char *tegra_rev_name[] = {
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[TEGRA_REVISION_UNKNOWN] = "unknown",
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[TEGRA_REVISION_A01] = "A01",
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[TEGRA_REVISION_A02] = "A02",
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[TEGRA_REVISION_A03] = "A03",
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[TEGRA_REVISION_A03p] = "A03 prime",
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[TEGRA_REVISION_A04] = "A04",
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};
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/* Tegra30 and later */
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#define FUSE_VENDOR_CODE 0x100
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#define FUSE_FAB_CODE 0x104
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#define FUSE_LOT_CODE_0 0x108
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#define FUSE_LOT_CODE_1 0x10c
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#define FUSE_WAFER_ID 0x110
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#define FUSE_X_COORDINATE 0x114
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#define FUSE_Y_COORDINATE 0x118
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/* ---------------------- Tegra 124 specific code & data --------------- */
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#define TEGRA124_FUSE_BEGIN 0x100
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#define TEGRA124_CPU_PROCESS_CORNERS 2
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#define TEGRA124_GPU_PROCESS_CORNERS 2
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#define TEGRA124_SOC_PROCESS_CORNERS 2
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#define TEGRA124_FUSE_SKU_INFO 0x10
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#define TEGRA124_FUSE_CPU_SPEEDO_0 0x14
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#define TEGRA124_FUSE_CPU_IDDQ 0x18
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#define TEGRA124_FUSE_FT_REV 0x28
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#define TEGRA124_FUSE_CPU_SPEEDO_1 0x2c
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#define TEGRA124_FUSE_CPU_SPEEDO_2 0x30
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#define TEGRA124_FUSE_SOC_SPEEDO_0 0x34
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#define TEGRA124_FUSE_SOC_SPEEDO_1 0x38
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#define TEGRA124_FUSE_SOC_SPEEDO_2 0x3c
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#define TEGRA124_FUSE_SOC_IDDQ 0x40
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#define TEGRA124_FUSE_GPU_IDDQ 0x128
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enum {
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TEGRA124_THRESHOLD_INDEX_0,
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TEGRA124_THRESHOLD_INDEX_1,
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TEGRA124_THRESHOLD_INDEX_COUNT,
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};
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static uint32_t tegra124_cpu_process_speedos[][TEGRA124_CPU_PROCESS_CORNERS] =
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{
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{2190, UINT_MAX},
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{0, UINT_MAX},
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};
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static uint32_t tegra124_gpu_process_speedos[][TEGRA124_GPU_PROCESS_CORNERS] =
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{
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{1965, UINT_MAX},
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{0, UINT_MAX},
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};
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static uint32_t tegra124_soc_process_speedos[][TEGRA124_SOC_PROCESS_CORNERS] =
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{
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{2101, UINT_MAX},
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{0, UINT_MAX},
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};
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static void
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tegra124_rev_sku_to_speedo_ids(struct tegra_efuse_softc *sc,
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struct tegra_sku_info *sku, int *threshold)
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{
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/* Assign to default */
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sku->cpu_speedo_id = 0;
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sku->soc_speedo_id = 0;
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sku->gpu_speedo_id = 0;
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*threshold = TEGRA124_THRESHOLD_INDEX_0;
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switch (sku->sku_id) {
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case 0x00: /* Eng sku */
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case 0x0F:
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case 0x23:
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/* Using the default */
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break;
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case 0x83:
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sku->cpu_speedo_id = 2;
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break;
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case 0x1F:
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case 0x87:
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case 0x27:
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sku->cpu_speedo_id = 2;
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sku->soc_speedo_id = 0;
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sku->gpu_speedo_id = 1;
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*threshold = TEGRA124_THRESHOLD_INDEX_0;
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break;
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case 0x81:
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case 0x21:
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case 0x07:
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sku->cpu_speedo_id = 1;
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sku->soc_speedo_id = 1;
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sku->gpu_speedo_id = 1;
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*threshold = TEGRA124_THRESHOLD_INDEX_1;
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break;
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case 0x49:
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case 0x4A:
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case 0x48:
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sku->cpu_speedo_id = 4;
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sku->soc_speedo_id = 2;
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sku->gpu_speedo_id = 3;
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*threshold = TEGRA124_THRESHOLD_INDEX_1;
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break;
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default:
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device_printf(sc->dev, " Unknown SKU ID %d\n", sku->sku_id);
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break;
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}
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}
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static void
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tegra124_init_speedo(struct tegra_efuse_softc *sc, struct tegra_sku_info *sku)
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{
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int i, threshold;
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sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO);
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sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ);
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sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ);
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sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ);
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sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0);
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sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0);
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sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2);
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if (sku->cpu_speedo_value == 0) {
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device_printf(sc->dev, "CPU Speedo value is not fused.\n");
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return;
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}
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tegra124_rev_sku_to_speedo_ids(sc, sku, &threshold);
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for (i = 0; i < TEGRA124_SOC_PROCESS_CORNERS; i++) {
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if (sku->soc_speedo_value <
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tegra124_soc_process_speedos[threshold][i])
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break;
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}
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sku->soc_process_id = i;
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for (i = 0; i < TEGRA124_CPU_PROCESS_CORNERS; i++) {
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if (sku->cpu_speedo_value <
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tegra124_cpu_process_speedos[threshold][i])
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break;
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}
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sku->cpu_process_id = i;
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for (i = 0; i < TEGRA124_GPU_PROCESS_CORNERS; i++) {
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if (sku->gpu_speedo_value <
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tegra124_gpu_process_speedos[threshold][i])
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break;
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}
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sku->gpu_process_id = i;
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}
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/* ----------------- End of Tegra 124 specific code & data --------------- */
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uint32_t
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tegra_fuse_read_4(int addr) {
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if (dev_sc == NULL)
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panic("tegra_fuse_read_4 called too early");
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return (RD4(dev_sc, addr));
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}
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static void
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2016-12-13 13:43:22 +00:00
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tegra_efuse_dump_sku(void)
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2016-03-16 13:01:48 +00:00
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{
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printf(" TEGRA SKU Info:\n");
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printf(" chip_id: %u\n", tegra_sku_info.chip_id);
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printf(" sku_id: %u\n", tegra_sku_info.sku_id);
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printf(" cpu_process_id: %u\n", tegra_sku_info.cpu_process_id);
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printf(" cpu_speedo_id: %u\n", tegra_sku_info.cpu_speedo_id);
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printf(" cpu_speedo_value: %u\n", tegra_sku_info.cpu_speedo_value);
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printf(" cpu_iddq_value: %u\n", tegra_sku_info.cpu_iddq_value);
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printf(" soc_process_id: %u\n", tegra_sku_info.soc_process_id);
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printf(" soc_speedo_id: %u\n", tegra_sku_info.soc_speedo_id);
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printf(" soc_speedo_value: %u\n", tegra_sku_info.soc_speedo_value);
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printf(" soc_iddq_value: %u\n", tegra_sku_info.soc_iddq_value);
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printf(" gpu_process_id: %u\n", tegra_sku_info.gpu_process_id);
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printf(" gpu_speedo_id: %u\n", tegra_sku_info.gpu_speedo_id);
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printf(" gpu_speedo_value: %u\n", tegra_sku_info.gpu_speedo_value);
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printf(" gpu_iddq_value: %u\n", tegra_sku_info.gpu_iddq_value);
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printf(" revision: %s\n", tegra_rev_name[tegra_sku_info.revision]);
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}
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static int
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tegra_efuse_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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tegra_efuse_attach(device_t dev)
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{
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int rv, rid;
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phandle_t node;
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struct tegra_efuse_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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/* Get the memory resource for the register mapping. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot map registers.\n");
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rv = ENXIO;
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goto fail;
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}
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/* OFW resources. */
|
2016-07-10 18:28:15 +00:00
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rv = clk_get_by_ofw_name(dev, 0, "fuse", &sc->clk);
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2016-03-16 13:01:48 +00:00
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if (rv != 0) {
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device_printf(dev, "Cannot get fuse clock: %d\n", rv);
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goto fail;
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}
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rv = clk_enable(sc->clk);
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if (rv != 0) {
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device_printf(dev, "Cannot enable clock: %d\n", rv);
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goto fail;
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}
|
2016-07-10 18:28:15 +00:00
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rv = hwreset_get_by_ofw_name(sc->dev, 0, "fuse", &sc->reset);
|
2016-03-16 13:01:48 +00:00
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if (rv != 0) {
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device_printf(dev, "Cannot get fuse reset\n");
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goto fail;
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}
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rv = hwreset_deassert(sc->reset);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot clear reset\n");
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goto fail;
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}
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/* Tegra124 specific init. */
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sc->fuse_begin = TEGRA124_FUSE_BEGIN;
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tegra124_init_speedo(sc, &tegra_sku_info);
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dev_sc = sc;
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if (bootverbose)
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tegra_efuse_dump_sku();
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return (bus_generic_attach(dev));
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fail:
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dev_sc = NULL;
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if (sc->clk != NULL)
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clk_release(sc->clk);
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if (sc->reset != NULL)
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hwreset_release(sc->reset);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
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return (rv);
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}
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static int
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tegra_efuse_detach(device_t dev)
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{
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struct tegra_efuse_softc *sc;
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sc = device_get_softc(dev);
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dev_sc = NULL;
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if (sc->clk != NULL)
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clk_release(sc->clk);
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if (sc->reset != NULL)
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|
|
|
hwreset_release(sc->reset);
|
|
|
|
if (sc->mem_res != NULL)
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
|
|
|
|
|
|
|
|
return (bus_generic_detach(dev));
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t tegra_efuse_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, tegra_efuse_probe),
|
|
|
|
DEVMETHOD(device_attach, tegra_efuse_attach),
|
|
|
|
DEVMETHOD(device_detach, tegra_efuse_detach),
|
|
|
|
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t tegra_efuse_devclass;
|
2016-09-30 05:25:15 +00:00
|
|
|
static DEFINE_CLASS_0(efuse, tegra_efuse_driver, tegra_efuse_methods,
|
|
|
|
sizeof(struct tegra_efuse_softc));
|
2016-03-16 13:01:48 +00:00
|
|
|
EARLY_DRIVER_MODULE(tegra_efuse, simplebus, tegra_efuse_driver,
|
2016-09-30 05:25:15 +00:00
|
|
|
tegra_efuse_devclass, NULL, NULL, BUS_PASS_TIMER);
|