2012-03-01 21:23:26 +00:00
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.\" Copyright (c) 2012 Davide Italiano <davide@FreeBSD.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 12, 2012
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.Dt PMC.SANDYBRIDGEUC 3
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.Os
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.Sh NAME
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.Nm pmc.sandybridgeuc
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.Nd uncore measurement events for
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.Tn Intel
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.Tn Sandy Bridge
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Sandy Bridge"
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CPUs contain PMCs conforming to version 3 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs contain two classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_UCP"
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.It Li PMC_CLASS_UCF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_UCP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Sandy Bridge PMCs are documented in
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.Rs
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.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
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.%T "Volume 3B: System Programming Guide, Part 2"
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.%N "Order Number: 253669-039US"
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.%D May 2011
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.%Q "Intel Corporation"
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.Re
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.Ss SANDYBRIDGE UNCORE FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.ucf 3 .
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Not all CPUs in this family implement fixed-function counters.
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.Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta \&No
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta \&No
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta \&No
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.El
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.Ss Event Specifiers (Programmable PMCs)
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Sandy Bridge programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li CBO_XSNP_RESPONSE.RSPIHITI
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.Pq Event 22H, Umask 01H
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2012-03-02 05:55:45 +00:00
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Snoop responses received from processor cores to requests initiated by this
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2012-03-01 21:23:26 +00:00
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Cbox.
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Must combine with one of the umask values of 20H, 40H, 80H
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.It Li CBO_XSNP_RESPONSE.RSPIHITFSE
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.Pq Event 22H, Umask 02H
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Must combine with one of the umask values of 20H, 40H, 80H
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.It Li CBO_XSNP_RESPONSE.RSPSHITFSE
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.Pq Event 22H, Umask 04H
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Must combine with one of the umask values of 20H, 40H, 80H
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.It Li CBO_XSNP_RESPONSE.RSPSFWDM
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.Pq Event 22H, Umask 08H
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.It Li CBO_XSNP_RESPONSE.RSPIFWDM
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.Pq Event 22H, Umask 01H
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.It Li CBO_XSNP_RESPONSE.AND_EXTERNAL
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.Pq Event 22H, Umask 20H
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2012-03-02 05:55:45 +00:00
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Filter on cross-core snoops resulted in external snoop request.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H, 10H
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.It Li CBO_XSNP_RESPONSE.AND_XCORE
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.Pq Event 22H, Umask 40H
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2012-03-02 05:55:45 +00:00
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Filter on cross-core snoops resulted in core request.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H, 10H
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.It Li CBO_XSNP_RESPONSE.AND_XCORE
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.Pq Event 22H, Umask 80H
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2012-03-02 05:55:45 +00:00
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Filter on cross-core snoops resulted in LLC evictions.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H, 10H
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.It Li CBO_CACHE_LOOKUP.M
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.Pq Event 34H, Umask 01H
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LLC lookup request that access cache and found line in M-state.
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Must combine with one of the umask values of 10H, 20H, 40H, 80H
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.It Li CBO_CACHE_LOOKUP.E
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2012-03-02 05:55:45 +00:00
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.Pq Event 34H, Umask 02H
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2012-03-01 21:23:26 +00:00
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LLC lookup request that access cache and found line in E-state.
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Must combine with one of the umask values of 10H, 20H, 40H, 80H
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.It Li CBO_CACHE_LOOKUP.S
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2012-03-02 05:55:45 +00:00
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.Pq Event 34H, Umask 04H
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2012-03-01 21:23:26 +00:00
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LLC lookup request that access cache and found line in S-state.
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Must combine with one of the umask values of 10H, 20H, 40H, 80H
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.It Li CBO_CACHE_LOOKUP.I
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2012-03-02 05:55:45 +00:00
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.Pq Event 34H, Umask 08H
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2012-03-01 21:23:26 +00:00
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LLC lookup request that access cache and found line in I-state.
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Must combine with one of the umask values of 10H, 20H, 40H, 80H
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.It Li CBO_CACHE_LOOKUP.AND_READ
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.Pq Event 34H, Umask 10H
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2012-03-02 05:55:45 +00:00
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Filter on processor core initiated cacheable read requests.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H
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.It Li CBO_CACHE_LOOKUP_AND_READ2
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.Pq Event 34H, Umask 20H
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2012-03-02 05:55:45 +00:00
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Filter on processor core initiated cacheable write requests.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H
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.It Li CBO_CACHE_LOOKUP.AND_EXTSNP
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.Pq Event 34H, Umask 40H
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2012-03-02 05:55:45 +00:00
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Filter on external snoop requests.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H
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.It Li CBO_CACHE_LOOKUP.AND_ANY
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.Pq Event 34H, Umask 80H
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2012-03-02 05:55:45 +00:00
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Filter on any IRQ or IPQ initiated requests including uncacheable,
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noncoherent requests.
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2012-03-01 21:23:26 +00:00
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Must combine with at least one of 01H, 02H, 04H, 08H
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.It Li IMPH_CBO_TRK_OCCUPANCY.ALL
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.Pq Event 80H, Umask 01H
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2012-03-02 05:55:45 +00:00
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Counts cycles weighted by the number of core-outgoing valid entries.
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Valid entries are between allocation to the first of IDIO or DRSO messages.
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2012-03-01 21:23:26 +00:00
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Accounts for coherent and incoherent traffic.
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Counter 0 only
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.It Li IMPH_CBO_TRK_REQUEST.ALL
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.Pq Event 81H, Umask 01H
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2012-03-02 05:55:45 +00:00
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Counts the number of core-outgoing entries.
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2012-03-01 21:23:26 +00:00
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Accounts for coherent and incoherent traffic.
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.It Li IMPH_CBO_TRK_REQUEST.WRITES
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.Pq Event 81H, Umask 20H
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2012-03-02 05:55:45 +00:00
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Counts the number of allocated write entries, include full, partial, and
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2012-03-01 21:23:26 +00:00
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evictions.
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.It Li IMPH_CBO_TRK_REQUEST.EVICTIONS
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.Pq Event 81H, Umask 80H
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Counts the number of evictions allocated.
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.It Li IMPH_COH_TRK_OCCUPANCY.ALL
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.Pq Event 83H, Umask 01H
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Counts cycles weighted by the
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number of core-outgoing valid entries in the coherent tracker queue.
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Counter 0 only
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.It Li IMPH_COH_TRK_REQUEST.ALL
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.Pq Event 84H, Umask 01H
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Counts the number of core-outgoing entries in the coherent tracker queue.
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.atom 3 ,
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.Xr pmc.core 3 ,
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.Xr pmc.corei7 3 ,
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.Xr pmc.corei7uc 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc.ucf 3 ,
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.Xr pmc.westmere 3 ,
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.Xr pmc.westmereuc 3 ,
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.Xr pmc_cpuinfo 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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.Sh AUTHORS
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The
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.Lb libpmc
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library was written by
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.An "Joseph Koshy"
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.Aq jkoshy@FreeBSD.org .
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2012-03-02 05:55:45 +00:00
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The support for the Sandy Bridge
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2012-03-01 21:23:26 +00:00
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microarchitecture was added by
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.An "Davide Italiano"
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.Aq davide@FreeBSD.org .
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