213 lines
6.1 KiB
C
213 lines
6.1 KiB
C
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef IMX6_CCM_CLK_H
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#define IMX6_CCM_CLK_H
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_gate.h>
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#include <dev/extres/clk/clk_link.h>
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enum imx_clk_type {
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IMX_CLK_UNDEFINED = 0,
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IMX_CLK_FIXED,
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IMX_CLK_LINK,
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IMX_CLK_MUX,
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IMX_CLK_GATE,
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IMX_CLK_COMPOSITE,
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IMX_CLK_SSCG_PLL,
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IMX_CLK_FRAC_PLL,
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IMX_CLK_DIV,
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};
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struct imx_clk {
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enum imx_clk_type type;
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union {
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struct clk_fixed_def *fixed;
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struct clk_link_def *link;
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struct imx_clk_mux_def *mux;
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struct imx_clk_gate_def *gate;
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struct imx_clk_composite_def *composite;
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struct imx_clk_sscg_pll_def *sscg_pll;
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struct imx_clk_frac_pll_def *frac_pll;
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struct clk_div_def *div;
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} clk;
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};
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/* Linked clock. */
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#define LINK(_id, _name) \
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{ \
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.type = IMX_CLK_LINK, \
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.clk.link = &(struct clk_link_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = NULL, \
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.clkdef.parent_cnt = 0, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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}, \
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}
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/* Complex clock without divider (multiplexer only). */
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#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
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{ \
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.type = IMX_CLK_MUX, \
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.clk.mux = &(struct imx_clk_mux_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pn, \
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.clkdef.parent_cnt = nitems(_pn), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _mo, \
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.shift = _ms, \
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.width = _mw, \
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.mux_flags = _f, \
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}, \
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}
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/* Fixed frequency clock */
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#define FIXED(_id, _name, _freq) \
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{ \
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.type = IMX_CLK_FIXED, \
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.clk.fixed = &(struct clk_fixed_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.freq = _freq, \
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}, \
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}
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/* Fixed factor multipier/divider. */
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#define FFACT(_id, _name, _pname, _mult, _div) \
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{ \
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.type = IMX_CLK_FIXED, \
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.clk.fixed = &(struct clk_fixed_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.mult = _mult, \
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.div = _div, \
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}, \
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}
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/* Clock gate */
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#define GATE(_id, _name, _pname, _o, _shift) \
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{ \
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.type = IMX_CLK_GATE, \
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.clk.gate = &(struct imx_clk_gate_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _o, \
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.shift = _shift, \
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.mask = 1, \
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}, \
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}
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/* Root clock gate */
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#define ROOT_GATE(_id, _name, _pname, _reg) \
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{ \
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.type = IMX_CLK_GATE, \
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.clk.gate = &(struct imx_clk_gate_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _reg, \
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.shift = 0, \
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.mask = 3, \
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}, \
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}
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/* Composite clock with GATE, MUX, PRE_DIV, and POST_DIV */
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#define COMPOSITE(_id, _name, _pn, _o, _flags) \
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{ \
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.type = IMX_CLK_COMPOSITE, \
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.clk.composite = &(struct imx_clk_composite_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pn, \
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.clkdef.parent_cnt = nitems(_pn), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _o, \
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.flags = _flags, \
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}, \
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}
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/* SSCG PLL */
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#define SSCG_PLL(_id, _name, _pn, _o) \
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{ \
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.type = IMX_CLK_SSCG_PLL, \
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.clk.composite = &(struct imx_clk_composite_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pn, \
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.clkdef.parent_cnt = nitems(_pn), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _o, \
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}, \
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}
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/* Fractional PLL */
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#define FRAC_PLL(_id, _name, _pname, _o) \
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{ \
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.type = IMX_CLK_FRAC_PLL, \
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.clk.frac_pll = &(struct imx_clk_frac_pll_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _o, \
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}, \
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}
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#define DIV(_id, _name, _pname, _o, _shift, _width) \
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{ \
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.type = IMX_CLK_DIV, \
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.clk.div = &(struct clk_div_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = _o, \
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.i_shift = _shift, \
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.i_width = _width, \
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}, \
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}
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#endif
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