2015-03-23 11:54:56 +00:00
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/*-
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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2015-03-23 16:04:04 +00:00
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* 3. Neither the name of the University nor the names of its contributors
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2015-03-23 11:54:56 +00:00
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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#include <machine/pte.h>
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#ifndef LOCORE
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#include <sys/queue.h>
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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2022-10-07 17:14:03 +00:00
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#include <sys/_pv_entry.h>
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2015-03-23 11:54:56 +00:00
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2016-08-24 12:32:18 +00:00
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#include <vm/_vm_radix.h>
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2015-03-23 11:54:56 +00:00
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#ifdef _KERNEL
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#define vtophys(va) pmap_kextract((vm_offset_t)(va))
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#endif
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#define pmap_page_get_memattr(m) ((m)->md.pv_memattr)
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2019-12-10 18:14:50 +00:00
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#define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0)
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2015-03-23 11:54:56 +00:00
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void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
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/*
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* Pmap stuff
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*/
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struct md_page {
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TAILQ_HEAD(,pv_entry) pv_list;
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int pv_gen;
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vm_memattr_t pv_memattr;
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};
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/*
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* This structure is used to hold a virtual<->physical address
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* association and is used mostly by bootstrap code
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*/
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struct pv_addr {
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SLIST_ENTRY(pv_addr) pv_list;
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vm_offset_t pv_va;
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vm_paddr_t pv_pa;
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};
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2020-02-26 11:47:24 +00:00
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enum pmap_stage {
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PM_INVALID,
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PM_STAGE1,
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PM_STAGE2,
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};
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2015-03-23 11:54:56 +00:00
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struct pmap {
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struct mtx pm_mtx;
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Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
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struct pmap_statistics pm_stats; /* pmap statistics */
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2020-11-04 11:48:08 +00:00
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uint64_t pm_ttbr;
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Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
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vm_paddr_t pm_l0_paddr;
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2016-03-31 11:07:24 +00:00
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pd_entry_t *pm_l0;
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2015-03-23 11:54:56 +00:00
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TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
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2016-08-24 12:32:18 +00:00
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struct vm_radix pm_root; /* spare page table pages */
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Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
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long pm_cookie; /* encodes the pmap's ASID */
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2020-02-26 11:50:24 +00:00
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struct asid_set *pm_asid_set; /* The ASID/VMID set to use */
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2020-02-26 11:47:24 +00:00
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enum pmap_stage pm_stage;
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2020-11-04 11:48:08 +00:00
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int pm_levels;
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2015-03-23 11:54:56 +00:00
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};
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2018-07-18 17:58:17 +00:00
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typedef struct pmap *pmap_t;
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2015-03-23 11:54:56 +00:00
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2018-01-08 10:23:31 +00:00
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struct thread;
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2015-03-23 11:54:56 +00:00
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#ifdef _KERNEL
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extern struct pmap kernel_pmap_store;
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#define kernel_pmap (&kernel_pmap_store)
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#define pmap_kernel() kernel_pmap
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#define PMAP_ASSERT_LOCKED(pmap) \
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mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
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#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
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#define PMAP_LOCK_ASSERT(pmap, type) \
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mtx_assert(&(pmap)->pm_mtx, (type))
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#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
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#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
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NULL, MTX_DEF | MTX_DUPOK)
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#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx)
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#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
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#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
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#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
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Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
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#define ASID_RESERVED_FOR_PID_0 0
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#define ASID_RESERVED_FOR_EFI 1
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#define ASID_FIRST_AVAILABLE (ASID_RESERVED_FOR_EFI + 1)
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#define ASID_TO_OPERAND(asid) ({ \
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KASSERT((asid) != -1, ("invalid ASID")); \
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2022-01-05 14:30:40 +00:00
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(uint64_t)(asid) << TTBR_ASID_SHIFT; \
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Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
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})
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2015-03-23 11:54:56 +00:00
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extern vm_offset_t virtual_avail;
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extern vm_offset_t virtual_end;
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/*
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* Macros to test if a mapping is mappable with an L1 Section mapping
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* or an L2 Large Page mapping.
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*/
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#define L1_MAPPABLE_P(va, pa, size) \
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((((va) | (pa)) & L1_OFFSET) == 0 && (size) >= L1_SIZE)
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2021-07-10 19:53:41 +00:00
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#define pmap_vm_page_alloc_check(m)
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2020-05-27 08:00:38 +00:00
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void pmap_activate_vm(pmap_t);
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2022-09-26 14:26:40 +00:00
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void pmap_bootstrap(vm_paddr_t, vm_size_t);
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2019-08-16 18:21:31 +00:00
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int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
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2021-09-20 16:49:18 +00:00
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int pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot);
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2018-06-20 16:07:35 +00:00
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void pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode);
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2015-04-13 14:43:10 +00:00
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void pmap_kenter_device(vm_offset_t, vm_size_t, vm_paddr_t);
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2021-01-15 18:48:43 +00:00
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bool pmap_klookup(vm_offset_t va, vm_paddr_t *pa);
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2015-03-23 11:54:56 +00:00
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vm_paddr_t pmap_kextract(vm_offset_t va);
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void pmap_kremove(vm_offset_t);
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2015-04-13 14:43:10 +00:00
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void pmap_kremove_device(vm_offset_t, vm_size_t);
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2022-07-28 22:55:10 +00:00
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void *pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma);
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2019-09-27 23:37:01 +00:00
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bool pmap_page_is_mapped(vm_page_t m);
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2020-11-04 11:48:08 +00:00
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int pmap_pinit_stage(pmap_t, enum pmap_stage, int);
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2018-07-20 16:37:04 +00:00
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bool pmap_ps_enabled(pmap_t pmap);
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Utilize ASIDs to reduce both the direct and indirect costs of context
switching. The indirect costs being unnecessary TLB misses that are
incurred when ASIDs are not used. In fact, currently, when we perform a
context switch on one processor, we issue a broadcast TLB invalidation that
flushes the TLB contents on every processor.
Mark all user-space ("ttbr0") page table entries with the non-global flag so
that they are cached in the TLB under their ASID.
Correct an error in pmap_pinit0(). The pointer to the root of the page
table was being initialized to the root of the kernel-space page table
rather than a user-space page table. However, the root of the page table
that was being cached in process 0's md_l0addr field correctly pointed to a
user-space page table. As long as ASIDs weren't being used, this was
harmless, except that it led to some unnecessary page table switches in
pmap_switch(). Specifically, other kernel processes besides process 0 would
have their md_l0addr field set to the root of the kernel-space page table,
and so pmap_switch() would actually change page tables when switching
between process 0 and other kernel processes.
Implement a workaround for Cavium erratum 27456 affecting ThunderX machines.
(I would like to thank andrew@ for providing the code to detect the affected
machines.)
Address integer overflow in the definition of TCR_ASID_16.
Setup TCR according to the PARange and ASIDBits fields from
ID_AA64MMFR0_EL1. Previously, TCR_ASID_16 was unconditionally set.
Modify build_l1_block_pagetable so that lower attributes, such as ATTR_nG,
can be specified as a parameter.
Eliminate some unused code.
Earlier versions were tested to varying degrees by: andrew, emaste, markj
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D21922
2019-11-03 17:45:30 +00:00
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uint64_t pmap_to_ttbr0(pmap_t pmap);
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2022-04-29 09:30:38 +00:00
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void pmap_disable_promotion(vm_offset_t sva, vm_size_t size);
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2015-03-23 11:54:56 +00:00
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2022-07-28 22:55:10 +00:00
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void *pmap_mapdev(vm_paddr_t, vm_size_t);
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2015-04-29 15:00:43 +00:00
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void *pmap_mapbios(vm_paddr_t, vm_size_t);
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2022-09-22 22:08:52 +00:00
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void pmap_unmapdev(void *, vm_size_t);
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void pmap_unmapbios(void *, vm_size_t);
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2015-03-23 11:54:56 +00:00
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boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
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void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
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2015-08-20 12:05:42 +00:00
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bool pmap_get_tables(pmap_t, vm_offset_t, pd_entry_t **, pd_entry_t **,
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2016-03-31 11:07:24 +00:00
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pd_entry_t **, pt_entry_t **);
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2015-08-20 12:05:42 +00:00
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2016-08-12 10:29:34 +00:00
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int pmap_fault(pmap_t, uint64_t, uint64_t);
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2021-07-08 13:15:55 +00:00
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struct pcb *pmap_switch(struct thread *);
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2018-01-08 10:23:31 +00:00
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2020-05-27 08:00:38 +00:00
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extern void (*pmap_clean_stage2_tlbi)(void);
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extern void (*pmap_invalidate_vpipt_icache)(void);
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2022-11-03 16:01:37 +00:00
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extern void (*pmap_stage2_invalidate_range)(uint64_t, vm_offset_t, vm_offset_t,
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bool);
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extern void (*pmap_stage2_invalidate_all)(uint64_t);
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2020-05-27 08:00:38 +00:00
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2019-02-20 09:51:13 +00:00
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static inline int
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pmap_vmspace_copy(pmap_t dst_pmap __unused, pmap_t src_pmap __unused)
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{
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return (0);
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}
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arm64: add KASAN support
This entails:
- Marking some obvious candidates for __nosanitizeaddress
- Similar trap frame markings as amd64, for similar reasons
- Shadow map implementation
The shadow map implementation is roughly similar to what was done on
amd64, with some exceptions. Attempting to use available space at
preinit_map_va + PMAP_PREINIT_MAPPING_SIZE (up to the end of that range,
as depicted in the physmap) results in odd failures, so we instead
search the physmap for free regions that we can carve out, fragmenting
the shadow map as necessary to try and fit as much as we need for the
initial kernel map. pmap_bootstrap_san() is thus after
pmap_bootstrap(), which still included some technically reserved areas
of the memory map that needed to be included in the DMAP.
The odd failure noted above may be a bug, but I haven't investigated it
all that much.
Initial work by mhorne with additional fixes from kevans and markj.
Reviewed by: andrew, markj
Sponsored by: Juniper Networks, Inc.
Sponsored by: Klara, Inc.
Differential Revision: https://reviews.freebsd.org/D36701
2023-03-23 21:26:06 +00:00
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#if defined(KASAN) || defined(KMSAN)
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struct arm64_bootparams;
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void pmap_bootstrap_san(vm_paddr_t);
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void pmap_san_enter(vm_offset_t);
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void pmap_san_bootstrap(struct arm64_bootparams *);
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#endif
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2015-03-23 11:54:56 +00:00
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#endif /* _KERNEL */
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PMAP_H_ */
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