27 lines
1.1 KiB
Plaintext
27 lines
1.1 KiB
Plaintext
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This directory contains mpn functions optimized for Intel Pentium
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processors.
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RELEVANT OPTIMIZATION ISSUES
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1. Pentium doesn't allocate cache lines on writes, unlike most other modern
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processors. Since the functions in the mpn class do array writes, we have to
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handle allocating the destination cache lines by reading a word from it in the
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loops, to achieve the best performance.
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2. Pairing of memory operations requires that the two issued operations refer
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to different cache banks. The simplest way to insure this is to read/write
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two words from the same object. If we make operations on different objects,
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they might or might not be to the same cache bank.
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STATUS
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1. mpn_lshift and mpn_rshift run at about 6 cycles/limb, but the Pentium
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documentation indicates that they should take only 43/8 = 5.375 cycles/limb,
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or 5 cycles/limb asymptotically.
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2. mpn_add_n and mpn_sub_n run at asymptotically 2 cycles/limb. Due to loop
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overhead and other delays (cache refill?), they run at or near 2.5 cycles/limb.
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3. mpn_mul_1, mpn_addmul_1, mpn_submul_1 all run 1 cycle faster than they
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should...
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