freebsd-dev/sys/arm/at91/at91_spireg.h

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/*-
* Copyright (c) 2006 M. Warner Losh. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef ARM_AT91_AT91_SPIREG_H
#define ARM_AT91_AT91_SPIREG_H
#define SPI_CR 0x00 /* CR: Control Register */
#define SPI_CR_SPIEN 0x1
#define SPI_CR_SPIDIS 0x2
#define SPI_CR_SWRST 0x8
#define SPI_MR 0x04 /* MR: Mode Register */
#define SPI_MR_MSTR 0x01
#define SPI_MR_PS 0x02
#define SPI_MR_PCSDEC 0x04
#define SPI_MR_DIV32 0x08
#define SPI_MR_MODFDIS 0x10
#define SPI_MR_LLB 0x80
#define SPI_MR_PSC_CS0 0xe0000
#define SPI_MR_PSC_CS1 0xd0000
#define SPI_MR_PSC_CS2 0xb0000
#define SPI_MR_PSC_CS3 0x70000
#define SPI_RDR 0x08 /* RDR: Receive Data Register */
#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
#define SPI_SR 0x10 /* SR: Status Register */
#define SPI_SR_RDRF 0x00001
#define SPI_SR_TDRE 0x00002
#define SPI_SR_MODF 0x00004
#define SPI_SR_OVRES 0x00008
#define SPI_SR_ENDRX 0x00010
#define SPI_SR_ENDTX 0x00020
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#define SPI_SR_RXBUFF 0x00040
#define SPI_SR_TXBUFE 0x00080
- Prepend the device description with "AT91" to reflect its nature. [1] - Move DMA tag and map creature to at91_spi_activate() where the other resource allocation also lives. [1] - Flesh out at91_spi_deactivate(). [1] - Work around the "Software Reset must be Written Twice" erratum. - For now, run the bus at the slowest speed possible in order to work around data corruption on transit even seen with 9 MHz on ETHERNUT5 (15 MHz maximum) and AT45DB321D (20 MHz maximum). This also serves as a poor man's work-around for the "NPCSx rises if no data data is to be transmitted" erratum of RM9200. Being able to use the appropriate bus speed would require: 1) Adding a proper work-around for the RM9200 bug consisting of taking the chip select control away from the SPI peripheral and managing it directly as a GPIO line. 2) Taking the maximum frequencies supported by the actual board and the slave devices into account and basing the whole thing on the master clock instead of hardcoding a divisor as previously done. 3) Fixing the above mentioned data corruption. - KASSERT that TX/RX command and data sizes match on transfers. - Introduce a mutex ensuring that only one child device is running a SPI transfer at a time. [1] - Add preliminary, #ifdef'ed out support for setting the chip select. [1] - Use the RX instead of the TX commando size when setting up the RX side of a transfer. - For controllers having SPI_SR_TXEMPTY, i.e. !RM9200, also wait for the completion of the TX part of transfers before stopping the whole thing again. - Use DEVMETHOD_END. [1] - Use NULL instead of 0 for pointers. [1, partially] Additional testing by: Ian Lepore Submitted by: Ian Lepore [1] MFC after: 1 week
2012-06-03 00:54:10 +00:00
#define SPI_SR_NSSR 0x00100
#define SPI_SR_TXEMPTY 0x00200
#define SPI_SR_SPIENS 0x10000
#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
#define SPI_CSR_CPOL 0x01
#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
#endif /* ARM_AT91_AT91_SPIREG_H */