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freebsd-dev/sys/dev/aic7xxx/aic79xx.reg

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Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Aic79xx register and scratch ram definitions.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
* Copyright (c) 2000-2002 Adaptec Inc.
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#45 $"
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* This file is processed by the aic7xxx_asm utility for use in assembling
* firmware for the aic79xx family of SCSI host adapters as well as to generate
* a C header file for use in the kernel portion of the Aic79xx driver.
*/
/* Register window Modes */
#define M_DFF0 0
#define M_DFF1 1
#define M_CCHAN 2
#define M_SCSI 3
#define M_CFG 4
#define M_DST_SHIFT 4
#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
#define SET_MODE(src, dst) \
SET_SRC_MODE src; \
SET_DST_MODE dst; \
if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
mvi MK_MODE(src, dst) call set_mode_work_around; \
} else { \
mvi MODE_PTR, MK_MODE(src, dst); \
}
#define TOGGLE_DFF_MODE \
if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
call toggle_dff_mode_work_around; \
} else { \
xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Mode Pointer
* Controls which of the 5, 512byte, address spaces should be used
* as the source and destination of any register accesses in our
* register window.
*/
register MODE_PTR {
address 0x000
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DST_MODE 0x70
field SRC_MODE 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
mode_pointer
}
const SRC_MODE_SHIFT 0
const DST_MODE_SHIFT 4
/*
* Host Interrupt Status
*/
register INTSTAT {
address 0x001
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field HWERRINT 0x80
field BRKADRINT 0x40
field SWTMINT 0x20
field PCIINT 0x10
field SCSIINT 0x08
field SEQINT 0x04
field CMDCMPLT 0x02
field SPLTINT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
mask INT_PEND 0xFF
}
/*
* Sequencer Interrupt Code
*/
register SEQINTCODE {
address 0x002
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field {
BAD_PHASE 1, /* unknown scsi bus phase */
SEND_REJECT, /* sending a message reject */
PROTO_VIOLATION, /* Protocol Violation */
NO_MATCH, /* no cmd match for reconnect */
IGN_WIDE_RES, /* Complex IGN Wide Res Msg */
PDATA_REINIT, /*
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* Returned to data phase
* that requires data
* transfer pointers to be
* recalculated from the
* transfer residual.
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
HOST_MSG_LOOP, /*
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* The bus is ready for the
* host to perform another
* message transaction. This
* mechanism is used for things
* like sync/wide negotiation
* that require a kernel based
* message state engine.
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
BAD_STATUS, /* Bad status from target */
DATA_OVERRUN, /*
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* Target attempted to write
* beyond the bounds of its
* command.
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
MKMSG_FAILED, /*
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* Target completed command
* without honoring our ATN
* request to issue a message.
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
MISSED_BUSFREE, /*
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
* The sequencer never saw
* the bus go free after
* either a command complete
* or disconnect message.
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
DUMP_CARD_STATE,
ILLEGAL_PHASE,
INVALID_SEQINT,
CFG4ISTAT_INTR,
STATUS_OVERRUN,
CFG4OVERRUN,
ENTERING_NONPACK
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear Host Interrupt
*/
register CLRINT {
address 0x003
access_mode WO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRHWERRINT 0x80 /* Rev B or greater */
field CLRBRKADRINT 0x40
field CLRSWTMINT 0x20
field CLRSCSIINT 0x08
field CLRSEQINT 0x04
field CLRCMDINT 0x02
field CLRSPLTINT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Error Register
*/
register ERROR {
address 0x004
access_mode RO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CIOPARERR 0x80
field CIOACCESFAIL 0x40 /* Rev B or greater */
field MPARERR 0x20
field DPARERR 0x10
field SQPARERR 0x08
field ILLOPCODE 0x04
field DSCTMOUT 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear Error
*/
register CLRERR {
address 0x004
access_mode WO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRCIOPARERR 0x80
field CLRCIOACCESFAIL 0x40 /* Rev B or greater */
field CLRMPARERR 0x20
field CLRDPARERR 0x10
field CLRSQPARERR 0x08
field CLRILLOPCODE 0x04
field CLRDSCTMOUT 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Host Control Register
* Overall host control of the device.
*/
register HCNTRL {
address 0x005
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SEQ_RESET 0x80 /* Rev B or greater */
field POWRDN 0x40
field SWINT 0x10
field SWTIMER_START_B 0x08 /* Rev B or greater */
field PAUSE 0x04
field INTEN 0x02
field CHIPRST 0x01
field CHIPRSTACK 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Host New SCB Queue Offset
*/
register HNSCB_QOFF {
address 0x006
access_mode RW
size 2
}
/*
* Host Empty SCB Queue Offset
*/
register HESCB_QOFF {
address 0x008
access_mode RW
}
/*
* Host Mailbox
*/
register HS_MAILBOX {
address 0x0B
access_mode RW
mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
}
/*
* Sequencer Interupt Status
*/
register SEQINTSTAT {
address 0x0C
access_mode RO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SEQ_SWTMRTO 0x10
field SEQ_SEQINT 0x08
field SEQ_SCSIINT 0x04
field SEQ_PCIINT 0x02
field SEQ_SPLTINT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear SEQ Interrupt
*/
register CLRSEQINTSTAT {
address 0x0C0
access_mode WO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRSEQ_SWTMRTO 0x10
field CLRSEQ_SEQINT 0x08
field CLRSEQ_SCSIINT 0x04
field CLRSEQ_PCIINT 0x02
field CLRSEQ_SPLTINT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Software Timer
*/
register SWTIMER {
address 0x0E0
access_mode RW
size 2
}
/*
* SEQ New SCB Queue Offset
*/
register SNSCB_QOFF {
address 0x010
access_mode RW
size 2
modes M_CCHAN
}
/*
* SEQ Empty SCB Queue Offset
*/
register SESCB_QOFF {
address 0x012
access_mode RW
modes M_CCHAN
}
/*
* SEQ Done SCB Queue Offset
*/
register SDSCB_QOFF {
address 0x014
access_mode RW
modes M_CCHAN
size 2
}
/*
* Queue Offset Control & Status
*/
register QOFF_CTLSTA {
address 0x016
access_mode RW
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field EMPTY_SCB_AVAIL 0x80
field NEW_SCB_AVAIL 0x40
field SDSCB_ROLLOVR 0x20
field HS_MAILBOX_ACT 0x10
field SCB_QSIZE 0x0F {
SCB_QSIZE_4,
SCB_QSIZE_8,
SCB_QSIZE_16,
SCB_QSIZE_32,
SCB_QSIZE_64,
SCB_QSIZE_128,
SCB_QSIZE_256,
SCB_QSIZE_512,
SCB_QSIZE_1024,
SCB_QSIZE_2048,
SCB_QSIZE_4096,
SCB_QSIZE_8192,
SCB_QSIZE_16384
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Interrupt Control
*/
register INTCTL {
address 0x018
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SWTMINTMASK 0x80
field SWTMINTEN 0x40
field SWTIMER_START 0x20
field AUTOCLRCMDINT 0x10
field PCIINTEN 0x08
field SCSIINTEN 0x04
field SEQINTEN 0x02
field SPLTINTEN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO Control
*/
register DFCNTRL {
address 0x019
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PRELOADEN 0x80
field SCSIEN 0x20
field SCSIENACK 0x20
field HDMAEN 0x08
field HDMAENACK 0x08
field DIRECTION 0x04
field DIRECTIONACK 0x04
field FIFOFLUSH 0x02
field FIFOFLUSHACK 0x02
field DIRECTIONEN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Device Space Command 0
*/
register DSCOMMAND0 {
address 0x019
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CACHETHEN 0x80 /* Cache Threshold enable */
field DPARCKEN 0x40 /* Data Parity Check Enable */
field MPARCKEN 0x20 /* Memory Parity Check Enable */
field EXTREQLCK 0x10 /* External Request Lock */
field DISABLE_TWATE 0x02 /* Rev B or greater */
field CIOPARCKEN 0x01 /* Internal bus parity error enable */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO Status
*/
register DFSTATUS {
address 0x01A
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PRELOAD_AVAIL 0x80
field PKT_PRELOAD_AVAIL 0x40
field MREQPEND 0x10
field HDONE 0x08
field DFTHRESH 0x04
field FIFOFULL 0x02
field FIFOEMP 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Cache Pointer
*/
register SG_CACHE_PRE {
address 0x01B
access_mode WO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SG_ADDR_MASK 0xf8
field ODD_SEG 0x04
field LAST_SEG 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
register SG_CACHE_SHADOW {
address 0x01B
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SG_ADDR_MASK 0xf8
field ODD_SEG 0x04
field LAST_SEG 0x02
field LAST_SEG_DONE 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Arbiter Control
*/
register ARBCTL {
address 0x01B
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field RESET_HARB 0x80
field RETRY_SWEN 0x08
field USE_TIME 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data Channel Host Address
*/
register HADDR {
address 0x070
access_mode RW
size 8
modes M_DFF0, M_DFF1
}
/*
* Host Overlay DMA Address
*/
register HODMAADR {
address 0x070
access_mode RW
size 8
modes M_SCSI
}
/*
* Data Channel Host Count
*/
register HCNT {
address 0x078
access_mode RW
size 3
modes M_DFF0, M_DFF1
}
/*
* Host Overlay DMA Count
*/
register HODMACNT {
address 0x078
access_mode RW
size 2
modes M_SCSI
}
/*
* Host Overlay DMA Enable
*/
register HODMAEN {
address 0x07A
access_mode RW
modes M_SCSI
}
/*
* Scatter/Gather Host Address
*/
register SGHADDR {
address 0x07C
access_mode RW
size 8
modes M_DFF0, M_DFF1
}
/*
* SCB Host Address
*/
register SCBHADDR {
address 0x07C
access_mode RW
size 8
modes M_CCHAN
}
/*
* Scatter/Gather Host Count
*/
register SGHCNT {
address 0x084
access_mode RW
modes M_DFF0, M_DFF1
}
/*
* SCB Host Count
*/
register SCBHCNT {
address 0x084
access_mode RW
modes M_CCHAN
}
/*
* Data FIFO Threshold
*/
register DFF_THRSH {
address 0x088
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field WR_DFTHRSH 0x70 {
WR_DFTHRSH_MIN,
WR_DFTHRSH_25,
WR_DFTHRSH_50,
WR_DFTHRSH_63,
WR_DFTHRSH_75,
WR_DFTHRSH_85,
WR_DFTHRSH_90,
WR_DFTHRSH_MAX
}
field RD_DFTHRSH 0x07 {
RD_DFTHRSH_MIN,
RD_DFTHRSH_25,
RD_DFTHRSH_50,
RD_DFTHRSH_63,
RD_DFTHRSH_75,
RD_DFTHRSH_85,
RD_DFTHRSH_90,
RD_DFTHRSH_MAX
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* ROM Address
*/
register ROMADDR {
address 0x08A
access_mode RW
size 3
}
/*
* ROM Control
*/
register ROMCNTRL {
address 0x08D
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ROMOP 0xE0
field ROMSPD 0x18
field REPEAT 0x02
field RDY 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* ROM Data
*/
register ROMDATA {
address 0x08E
access_mode RW
}
/*
* Data Channel Receive Message 0
*/
register DCHRXMSG0 {
address 0x090
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDNUM 0xF8
field CFNUM 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Recieve Message 0
*/
register CMCRXMSG0 {
address 0x090
access_mode RO
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDNUM 0xF8
field CFNUM 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay Recieve Message 0
*/
register OVLYRXMSG0 {
address 0x090
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDNUM 0xF8
field CFNUM 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Relaxed Order Enable
*/
register ROENABLE {
address 0x090
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MSIROEN 0x20
field OVLYROEN 0x10
field CMCROEN 0x08
field SGROEN 0x04
field DCH1ROEN 0x02
field DCH0ROEN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data Channel Receive Message 1
*/
register DCHRXMSG1 {
address 0x091
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CBNUM 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Recieve Message 1
*/
register CMCRXMSG1 {
address 0x091
access_mode RO
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CBNUM 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay Recieve Message 1
*/
register OVLYRXMSG1 {
address 0x091
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CBNUM 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* No Snoop Enable
*/
register NSENABLE {
address 0x091
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MSINSEN 0x20
field OVLYNSEN 0x10
field CMCNSEN 0x08
field SGNSEN 0x04
field DCH1NSEN 0x02
field DCH0NSEN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data Channel Receive Message 2
*/
register DCHRXMSG2 {
address 0x092
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MINDEX 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Recieve Message 2
*/
register CMCRXMSG2 {
address 0x092
access_mode RO
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MINDEX 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay Recieve Message 2
*/
register OVLYRXMSG2 {
address 0x092
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MINDEX 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Outstanding Split Transactions
*/
register OST {
address 0x092
access_mode RW
modes M_CFG
}
/*
* Data Channel Receive Message 3
*/
register DCHRXMSG3 {
address 0x093
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MCLASS 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Recieve Message 3
*/
register CMCRXMSG3 {
address 0x093
access_mode RO
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MCLASS 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay Recieve Message 3
*/
register OVLYRXMSG3 {
address 0x093
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MCLASS 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* PCI-X Control
*/
register PCIXCTL {
address 0x093
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SERRPULSE 0x80
field UNEXPSCIEN 0x20
field SPLTSMADIS 0x10
field SPLTSTADIS 0x08
field SRSPDPEEN 0x04
field TSCSERREN 0x02
field CMPABCDIS 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Sequencer Byte Count
*/
register CMCSEQBCNT {
address 0x094
access_mode RO
modes M_CCHAN
}
/*
* Overlay Sequencer Byte Count
*/
register OVLYSEQBCNT {
address 0x094
access_mode RO
modes M_SCSI
}
/*
* Data Channel Sequencer Byte Count
*/
register DCHSEQBCNT {
address 0x094
access_mode RO
size 2
modes M_DFF0, M_DFF1
}
/*
* Data Channel Split Status 0
*/
register DCHSPLTSTAT0 {
address 0x096
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field STAETERM 0x80
field SCBCERR 0x40
field SCADERR 0x20
field SCDATBUCKET 0x10
field CNTNOTCMPLT 0x08
field RXOVRUN 0x04
field RXSCEMSG 0x02
field RXSPLTRSP 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Split Status 0
*/
register CMCSPLTSTAT0 {
address 0x096
access_mode RW
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field STAETERM 0x80
field SCBCERR 0x40
field SCADERR 0x20
field SCDATBUCKET 0x10
field CNTNOTCMPLT 0x08
field RXOVRUN 0x04
field RXSCEMSG 0x02
field RXSPLTRSP 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay Split Status 0
*/
register OVLYSPLTSTAT0 {
address 0x096
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field STAETERM 0x80
field SCBCERR 0x40
field SCADERR 0x20
field SCDATBUCKET 0x10
field CNTNOTCMPLT 0x08
field RXOVRUN 0x04
field RXSCEMSG 0x02
field RXSPLTRSP 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data Channel Split Status 1
*/
register DCHSPLTSTAT1 {
address 0x097
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field RXDATABUCKET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Split Status 1
*/
register CMCSPLTSTAT1 {
address 0x097
access_mode RW
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field RXDATABUCKET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay Split Status 1
*/
register OVLYSPLTSTAT1 {
address 0x097
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field RXDATABUCKET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Receive Message 0
*/
register SGRXMSG0 {
address 0x098
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDNUM 0xF8
field CFNUM 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Receive Message 1
*/
register SGRXMSG1 {
address 0x099
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CBNUM 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Receive Message 2
*/
register SGRXMSG2 {
address 0x09A
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MINDEX 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Receive Message 3
*/
register SGRXMSG3 {
address 0x09B
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MCLASS 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Slave Split Out Address 0
*/
register SLVSPLTOUTADR0 {
address 0x098
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LOWER_ADDR 0x7F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Slave Split Out Address 1
*/
register SLVSPLTOUTADR1 {
address 0x099
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field REQ_DNUM 0xF8
field REQ_FNUM 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Slave Split Out Address 2
*/
register SLVSPLTOUTADR2 {
address 0x09A
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field REQ_BNUM 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Slave Split Out Address 3
*/
register SLVSPLTOUTADR3 {
address 0x09B
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field RLXORD 020
field TAG_NUM 0x1F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SG Sequencer Byte Count
*/
register SGSEQBCNT {
address 0x09C
access_mode RO
modes M_DFF0, M_DFF1
}
/*
* Slave Split Out Attribute 0
*/
register SLVSPLTOUTATTR0 {
address 0x09C
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LOWER_BCNT 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Slave Split Out Attribute 1
*/
register SLVSPLTOUTATTR1 {
address 0x09D
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CMPLT_DNUM 0xF8
field CMPLT_FNUM 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Slave Split Out Attribute 2
*/
register SLVSPLTOUTATTR2 {
address 0x09E
access_mode RO
size 2
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CMPLT_BNUM 0xFF
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Split Status 0
*/
register SGSPLTSTAT0 {
address 0x09E
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field STAETERM 0x80
field SCBCERR 0x40
field SCADERR 0x20
field SCDATBUCKET 0x10
field CNTNOTCMPLT 0x08
field RXOVRUN 0x04
field RXSCEMSG 0x02
field RXSPLTRSP 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G Split Status 1
*/
register SGSPLTSTAT1 {
address 0x09F
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field RXDATABUCKET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Special Function
*/
register SFUNCT {
address 0x09f
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TEST_GROUP 0xF0
field TEST_NUM 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO 0 PCI Status
*/
register DF0PCISTAT {
address 0x0A0
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPE 0x80
field SSE 0x40
field RMA 0x20
field RTA 0x10
field SCAAPERR 0x08
field RDPERR 0x04
field TWATERR 0x02
field DPR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO 1 PCI Status
*/
register DF1PCISTAT {
address 0x0A1
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPE 0x80
field SSE 0x40
field RMA 0x20
field RTA 0x10
field SCAAPERR 0x08
field RDPERR 0x04
field TWATERR 0x02
field DPR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* S/G PCI Status
*/
register SGPCISTAT {
address 0x0A2
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPE 0x80
field SSE 0x40
field RMA 0x20
field RTA 0x10
field SCAAPERR 0x08
field RDPERR 0x04
field DPR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC PCI Status
*/
register CMCPCISTAT {
address 0x0A3
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPE 0x80
field SSE 0x40
field RMA 0x20
field RTA 0x10
field SCAAPERR 0x08
field RDPERR 0x04
field TWATERR 0x02
field DPR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Overlay PCI Status
*/
register OVLYPCISTAT {
address 0x0A4
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPE 0x80
field SSE 0x40
field RMA 0x20
field RTA 0x10
field SCAAPERR 0x08
field RDPERR 0x04
field DPR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* PCI Status for MSI Master DMA Transfer
*/
register MSIPCISTAT {
address 0x0A6
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SSE 0x40
field RMA 0x20
field RTA 0x10
field CLRPENDMSI 0x08
field TWATERR 0x02
field DPR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* PCI Status for Target
*/
register TARGPCISTAT {
address 0x0A6
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPE 0x80
field SSE 0x40
field STA 0x08
field TWATERR 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQ Packet In
* The last LQ Packet recieved
*/
register LQIN {
address 0x020
access_mode RW
size 20
modes M_DFF0, M_DFF1, M_SCSI
}
/*
* SCB Type Pointer
* SCB offset for Target Mode SCB type information
*/
register TYPEPTR {
address 0x020
access_mode RW
modes M_CFG
}
/*
* Queue Tag Pointer
* SCB offset to the Two Byte tag identifier used for target mode.
*/
register TAGPTR {
address 0x021
access_mode RW
modes M_CFG
}
/*
* Logical Unit Number Pointer
* SCB offset to the LSB (little endian) of the lun field.
*/
register LUNPTR {
address 0x022
access_mode RW
modes M_CFG
}
/*
* Data Length Pointer
* SCB offset for the 4 byte data length field in target mode.
*/
register DATALENPTR {
address 0x023
access_mode RW
modes M_CFG
}
/*
* Status Length Pointer
* SCB offset to the two byte status field in target SCBs.
*/
register STATLENPTR {
address 0x024
access_mode RW
modes M_CFG
}
/*
* Command Length Pointer
* Scb offset for the CDB length field in initiator SCBs.
*/
register CMDLENPTR {
address 0x025
access_mode RW
modes M_CFG
}
/*
* Task Attribute Pointer
* Scb offset for the byte field specifying the attribute byte
* to be used in command packets.
*/
register ATTRPTR {
address 0x026
access_mode RW
modes M_CFG
}
/*
* Task Management Flags Pointer
* Scb offset for the byte field specifying the attribute flags
* byte to be used in command packets.
*/
register FLAGPTR {
address 0x027
access_mode RW
modes M_CFG
}
/*
* Command Pointer
* Scb offset for the first byte in the CDB for initiator SCBs.
*/
register CMDPTR {
address 0x028
access_mode RW
modes M_CFG
}
/*
* Queue Next Pointer
* Scb offset for the 2 byte "next scb link".
*/
register QNEXTPTR {
address 0x029
access_mode RW
modes M_CFG
}
/*
* SCSI ID Pointer
* Scb offset to the value to place in the SCSIID register
* during target mode connections.
*/
register IDPTR {
address 0x02A
access_mode RW
modes M_CFG
}
/*
* Command Aborted Byte Pointer
* Offset to the SCB flags field that includes the
* "SCB aborted" status bit.
*/
register ABRTBYTEPTR {
address 0x02B
access_mode RW
modes M_CFG
}
/*
* Command Aborted Bit Pointer
* Bit offset in the SCB flags field for "SCB aborted" status.
*/
register ABRTBITPTR {
address 0x02C
access_mode RW
modes M_CFG
}
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
/*
* Rev B or greater.
*/
register MAXCMDBYTES {
address 0x02D
access_mode RW
modes M_CFG
}
/*
* Rev B or greater.
*/
register MAXCMD2RCV {
address 0x02E
access_mode RW
modes M_CFG
}
/*
* Rev B or greater.
*/
register SHORTTHRESH {
address 0x02F
access_mode RW
modes M_CFG
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Logical Unit Number Length
* The length, in bytes, of the SCB lun field.
*/
register LUNLEN {
address 0x030
access_mode RW
modes M_CFG
}
/*
* CDB Limit
* The size, in bytes, of the embedded CDB field in initator SCBs.
*/
register CDBLIMIT {
address 0x031
access_mode RW
modes M_CFG
}
/*
* Maximum Commands
* The maximum number of commands to issue during a
* single packetized connection.
*/
register MAXCMD {
address 0x032
access_mode RW
modes M_CFG
}
/*
* Maximum Command Counter
* The number of commands already sent during this connection
*/
register MAXCMDCNT {
address 0x033
access_mode RW
modes M_CFG
}
/*
* LQ Packet Reserved Bytes
* The bytes to be sent in the currently reserved fileds
* of all LQ packets.
*/
register LQRSVD01 {
address 0x034
access_mode RW
modes M_SCSI
}
register LQRSVD16 {
address 0x035
access_mode RW
modes M_SCSI
}
register LQRSVD17 {
address 0x036
access_mode RW
modes M_SCSI
}
/*
* Command Reserved 0
* The byte to be sent for the reserved byte 0 of
* outgoing command packets.
*/
register CMDRSVD0 {
address 0x037
access_mode RW
modes M_CFG
}
/*
* LQ Manager Control 0
*/
register LQCTL0 {
address 0x038
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQITARGCLT 0xC0
field LQIINITGCLT 0x30
field LQ0TARGCLT 0x0C
field LQ0INITGCLT 0x03
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQ Manager Control 1
*/
register LQCTL1 {
address 0x038
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PCI2PCI 0x04
field SINGLECMD 0x02
field ABORTPENDING 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQ Manager Control 2
*/
register LQCTL2 {
address 0x039
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQIRETRY 0x80
field LQICONTINUE 0x40
field LQITOIDLE 0x20
field LQIPAUSE 0x10
field LQORETRY 0x08
field LQOCONTINUE 0x04
field LQOTOIDLE 0x02
field LQOPAUSE 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI RAM BIST0
*/
register SCSBIST0 {
address 0x039
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field GSBISTERR 0x40
field GSBISTDONE 0x20
field GSBISTRUN 0x10
field OSBISTERR 0x04
field OSBISTDONE 0x02
field OSBISTRUN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Sequence Control0
*/
register SCSISEQ0 {
address 0x03A
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TEMODEO 0x80
field ENSELO 0x40
field ENARBO 0x20
field FORCEBUSFREE 0x10
field SCSIRSTO 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI RAM BIST 1
*/
register SCSBIST1 {
address 0x03A
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field NTBISTERR 0x04
field NTBISTDONE 0x02
field NTBISTRUN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Sequence Control 1
*/
register SCSISEQ1 {
address 0x03B
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MANUALCTL 0x40
field ENSELI 0x20
field ENRSELI 0x10
field MANUALP 0x0C
field ENAUTOATNP 0x02
field ALTSTIM 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Transfer Control 0
*/
register SXFRCTL0 {
address 0x03C
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DFON 0x80
field DFPEXP 0x40
field BIOSCANCELEN 0x10
field SPIOEN 0x08
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Transfer Control 1
*/
register SXFRCTL1 {
address 0x03D
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field BITBUCKET 0x80
field ENSACHK 0x40
field ENSPCHK 0x20
field STIMESEL 0x18
field ENSTIMER 0x04
field ACTNEGEN 0x02
field STPWEN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Transfer Control 2
*/
register SXFRCTL2 {
address 0x03E
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field AUTORSTDIS 0x10
field CMDDMAEN 0x08
field ASU 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Bus Initiator IDs
* Bitmask of observed initiators on the bus.
*/
register BUSINITID {
address 0x03C
access_mode RW
modes M_CFG
size 2
}
/*
* Data Length Counters
* Packet byte counter.
*/
register DLCOUNT {
address 0x03C
access_mode RW
modes M_DFF0, M_DFF1
size 3
}
/*
* Data FIFO Status
*/
register DFFSTAT {
address 0x03F
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field FIFO1FREE 0x20
field FIFO0FREE 0x10
field CURRFIFO 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Bus Target IDs
* Bitmask of observed targets on the bus.
*/
register BUSTARGID {
address 0x03E
access_mode RW
modes M_CFG
size 2
}
/*
* SCSI Control Signal Out
*/
register SCSISIGO {
address 0x040
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDO 0x80
field IOO 0x40
field MSGO 0x20
field ATNO 0x10
field SELO 0x08
field BSYO 0x04
field REQO 0x02
field ACKO 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Possible phases to write into SCSISIG0
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
enum PHASE_MASK CDO|IOO|MSGO {
P_DATAOUT 0x0,
P_DATAIN IOO,
P_DATAOUT_DT P_DATAOUT|MSGO,
P_DATAIN_DT P_DATAIN|MSGO,
P_COMMAND CDO,
P_MESGOUT CDO|MSGO,
P_STATUS CDO|IOO,
P_MESGIN CDO|IOO|MSGO
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
register SCSISIGI {
address 0x041
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDI 0x80
field IOI 0x40
field MSGI 0x20
field ATNI 0x10
field SELI 0x08
field BSYI 0x04
field REQI 0x02
field ACKI 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Possible phases in SCSISIGI
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
enum PHASE_MASK CDO|IOO|MSGO {
P_DATAOUT 0x0,
P_DATAIN IOO,
P_DATAOUT_DT P_DATAOUT|MSGO,
P_DATAIN_DT P_DATAIN|MSGO,
P_COMMAND CDO,
P_MESGOUT CDO|MSGO,
P_STATUS CDO|IOO,
P_MESGIN CDO|IOO|MSGO
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Multiple Target IDs
* Bitmask of ids to respond as a target.
*/
register MULTARGID {
address 0x040
access_mode RW
modes M_CFG
size 2
}
/*
* SCSI Phase
*/
register SCSIPHASE {
address 0x042
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field STATUS_PHASE 0x20
field COMMAND_PHASE 0x10
field MSG_IN_PHASE 0x08
field MSG_OUT_PHASE 0x04
field DATA_PHASE_MASK 0x03 {
DATA_OUT_PHASE 0x01,
DATA_IN_PHASE 0x02
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Data 0 Image
*/
register SCSIDAT0_IMG {
address 0x043
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
}
/*
* SCSI Latched Data
*/
register SCSIDAT {
address 0x044
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
size 2
}
/*
* SCSI Data Bus
*/
register SCSIBUS {
address 0x046
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
size 2
}
/*
* Target ID In
*/
register TARGIDIN {
address 0x048
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLKOUT 0x80
field TARGID 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Selection/Reselection ID
* Upper four bits are the device id. The ONEBIT is set when the re/selecting
* device did not set its own ID.
*/
register SELID {
address 0x049
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SELID_MASK 0xf0
field ONEBIT 0x08
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Block Control
* Controls Bus type and channel selection. SELWIDE allows for the
* coexistence of 8bit and 16bit devices on a wide bus.
*/
register SBLKCTL {
address 0x04A
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DIAGLEDEN 0x80
field DIAGLEDON 0x40
field ENAB40 0x08 /* LVD transceiver active */
field ENAB20 0x04 /* SE/HVD transceiver active */
field SELWIDE 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Option Mode
*/
register OPTIONMODE {
address 0x04A
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field BIOSCANCTL 0x80
field AUTOACKEN 0x40
field BIASCANCTL 0x20
field BUSFREEREV 0x10
field ENDGFORMCHK 0x04
field AUTO_MSGOUT_DE 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
}
/*
* SCSI Status 0
*/
register SSTAT0 {
address 0x04B
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TARGET 0x80 /* Board acting as target */
field SELDO 0x40 /* Selection Done */
field SELDI 0x20 /* Board has been selected */
field SELINGO 0x10 /* Selection In Progress */
field IOERR 0x08 /* LVD Tranceiver mode changed */
field OVERRUN 0x04 /* SCSI Offset overrun detected */
field SPIORDY 0x02 /* SCSI PIO Ready */
field ARBDO 0x01 /* Arbitration Done Out */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear SCSI Interrupt 0
* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
*/
register CLRSINT0 {
address 0x04B
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRSELDO 0x40
field CLRSELDI 0x20
field CLRSELINGO 0x10
field CLRIOERR 0x08
field CLROVERRUN 0x04
field CLRSPIORDY 0x02
field CLRARBDO 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Interrupt Mode 0
* Setting any bit will enable the corresponding function
* in SIMODE0 to interrupt via the IRQ pin.
*/
register SIMODE0 {
address 0x04B
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENSELDO 0x40
field ENSELDI 0x20
field ENSELINGO 0x10
field ENIOERR 0x08
field ENOVERRUN 0x04
field ENSPIORDY 0x02
field ENARBDO 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Status 1
*/
register SSTAT1 {
address 0x04C
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SELTO 0x80
field ATNTARG 0x40
field SCSIRSTI 0x20
field PHASEMIS 0x10
field BUSFREE 0x08
field SCSIPERR 0x04
field STRB2FAST 0x02
field REQINIT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear SCSI Interrupt 1
* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
*/
register CLRSINT1 {
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
address 0x04C
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRSELTIMEO 0x80
field CLRATNO 0x40
field CLRSCSIRSTI 0x20
field CLRBUSFREE 0x08
field CLRSCSIPERR 0x04
field CLRSTRB2FAST 0x02
field CLRREQINIT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Status 2
*/
register SSTAT2 {
address 0x04d
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field BUSFREETIME 0xc0 {
BUSFREE_LQO 0x40,
BUSFREE_DFF0 0x80,
BUSFREE_DFF1 0xC0
}
field NONPACKREQ 0x20
field EXP_ACTIVE 0x10 /* SCSI Expander Active */
field BSYX 0x08 /* Busy Expander */
field WIDE_RES 0x04 /* Modes 0 and 1 only */
field SDONE 0x02 /* Modes 0 and 1 only */
field DMADONE 0x01 /* Modes 0 and 1 only */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear SCSI Interrupt 2
*/
register CLRSINT2 {
address 0x04D
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRNONPACKREQ 0x20
field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
field CLRSDONE 0x02 /* Modes 0 and 1 only */
field CLRDMADONE 0x01 /* Modes 0 and 1 only */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Interrupt Mode 2
*/
register SIMODE2 {
address 0x04D
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENWIDE_RES 0x04
field ENSDONE 0x02
field ENDMADONE 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Physical Error Diagnosis
*/
register PERRDIAG {
address 0x04E
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field HIZERO 0x80
field HIPERR 0x40
field PREVPHASE 0x20
field PARITYERR 0x10
field AIPERR 0x08
field CRCERR 0x04
field DGFORMERR 0x02
field DTERR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQI Manager Current State
*/
register LQISTATE {
address 0x04E
access_mode RO
modes M_CFG
}
/*
* SCSI Offset Count
*/
register SOFFCNT {
address 0x04F
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
}
/*
* LQO Manager Current State
*/
register LQOSTATE {
address 0x04F
access_mode RO
modes M_CFG
}
/*
* LQI Manager Status
*/
register LQISTAT0 {
address 0x050
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQIATNQAS 0x20
field LQICRCT1 0x10
field LQICRCT2 0x08
field LQIBADLQT 0x04
field LQIATNLQ 0x02
field LQIATNCMD 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear LQI Interrupts 0
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
register CLRLQIINT0 {
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
address 0x050
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRLQIATNQAS 0x20
field CLRLQICRCT1 0x10
field CLRLQICRCT2 0x08
field CLRLQIBADLQT 0x04
field CLRLQIATNLQ 0x02
field CLRLQIATNCMD 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQI Manager Interrupt Mode 0
*/
register LQIMODE0 {
address 0x050
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENLQIATNQASK 0x20
field ENLQICRCT1 0x10
field ENLQICRCT2 0x08
field ENLQIBADLQT 0x04
field ENLQIATNLQ 0x02
field ENLQIATNCMD 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQI Manager Status 1
*/
register LQISTAT1 {
address 0x051
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQIPHASE_LQ 0x80
field LQIPHASE_NLQ 0x40
field LQIABORT 0x20
field LQICRCI_LQ 0x10
field LQICRCI_NLQ 0x08
field LQIBADLQI 0x04
field LQIOVERI_LQ 0x02
field LQIOVERI_NLQ 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear LQI Manager Interrupts1
*/
register CLRLQIINT1 {
address 0x051
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRLQIPHASE_LQ 0x80
field CLRLQIPHASE_NLQ 0x40
field CLRLIQABORT 0x20
field CLRLQICRCI_LQ 0x10
field CLRLQICRCI_NLQ 0x08
field CLRLQIBADLQI 0x04
field CLRLQIOVERI_LQ 0x02
field CLRLQIOVERI_NLQ 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQI Manager Interrupt Mode 1
*/
register LQIMODE1 {
address 0x051
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENLQIPHASE_LQ 0x80
field ENLQIPHASE_NLQ 0x40
field ENLIQABORT 0x20
field ENLQICRCI_LQ 0x10
field ENLQICRCI_NLQ 0x08
field ENLQIBADLQI 0x04
field ENLQIOVERI_LQ 0x02
field ENLQIOVERI_NLQ 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQI Manager Status 2
*/
register LQISTAT2 {
address 0x052
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PACKETIZED 0x80
field LQIPHASE_OUTPKT 0x40
field LQIWORKONLQ 0x20
field LQIWAITFIFO 0x10
field LQISTOPPKT 0x08
field LQISTOPLQ 0x04
field LQISTOPCMD 0x02
field LQIGSAVAIL 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Status 3
*/
register SSTAT3 {
address 0x053
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field NTRAMPERR 0x02
field OSRAMPERR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear SCSI Status 3
*/
register CLRSINT3 {
address 0x053
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRNTRAMPERR 0x02
field CLROSRAMPERR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Interrupt Mode 3
*/
register SIMODE3 {
address 0x053
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENNTRAMPERR 0x02
field ENOSRAMPERR 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQO Manager Status 0
*/
register LQOSTAT0 {
address 0x054
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQOTARGSCBPERR 0x10
field LQOSTOPT2 0x08
field LQOATNLQ 0x04
field LQOATNPKT 0x02
field LQOTCRC 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear LQO Manager interrupt 0
*/
register CLRLQOINT0 {
address 0x054
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRLQOTARGSCBPERR 0x10
field CLRLQOSTOPT2 0x08
field CLRLQOATNLQ 0x04
field CLRLQOATNPKT 0x02
field CLRLQOTCRC 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQO Manager Interrupt Mode 0
*/
register LQOMODE0 {
address 0x054
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENLQOTARGSCBPERR 0x10
field ENLQOSTOPT2 0x08
field ENLQOATNLQ 0x04
field ENLQOATNPKT 0x02
field ENLQOTCRC 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQO Manager Status 1
*/
register LQOSTAT1 {
address 0x055
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQOINITSCBPERR 0x10
field LQOSTOPI2 0x08
field LQOBADQAS 0x04
field LQOBUSFREE 0x02
field LQOPHACHGINPKT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear LOQ Interrupt 1
*/
register CLRLQOINT1 {
address 0x055
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRLQOINITSCBPERR 0x10
field CLRLQOSTOPI2 0x08
field CLRLQOBADQAS 0x04
field CLRLQOBUSFREE 0x02
field CLRLQOPHACHGINPKT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQO Manager Interrupt Mode 1
*/
register LQOMODE1 {
address 0x055
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENLQOINITSCBPERR 0x10
field ENLQOSTOPI2 0x08
field ENLQOBADQAS 0x04
field ENLQOBUSFREE 0x02
field ENLQOPHACHGINPKT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* LQO Manager Status 2
*/
register LQOSTAT2 {
address 0x056
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LQOPKT 0xE0
field LQOWAITFIFO 0x10
field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */
field LQOSTOP0 0x01 /* Stopped after sending all packets */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Output Synchronizer Space Count
*/
register OS_SPACE_CNT {
address 0x056
access_mode RO
modes M_CFG
}
/*
* SCSI Interrupt Mode 1
* Setting any bit will enable the corresponding function
* in SIMODE1 to interrupt via the IRQ pin.
*/
register SIMODE1 {
address 0x057
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENSELTIMO 0x80
field ENATNTARG 0x40
field ENSCSIRST 0x20
field ENPHASEMIS 0x10
field ENBUSFREE 0x08
field ENSCSIPERR 0x04
field ENSTRB2FAST 0x02
field ENREQINIT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Good Status FIFO
*/
register GSFIFO {
address 0x058
access_mode RO
size 2
modes M_DFF0, M_DFF1, M_SCSI
}
/*
* Data FIFO SCSI Transfer Control
*/
register DFFSXFRCTL {
address 0x05A
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRSHCNT 0x04
field CLRCHN 0x02
field RSTCHN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Next SCSI Control Block
*/
register NEXTSCB {
address 0x05A
access_mode RW
size 2
modes M_SCSI
}
/*
* SEQ Interrupts
*/
register SEQINTSRC {
address 0x05B
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CTXTDONE 0x40
field SAVEPTRS 0x20
field CFG4DATA 0x10
field CFG4ISTAT 0x08
field CFG4TSTAT 0x04
field CFG4ICMD 0x02
field CFG4TCMD 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Clear Arp Interrupts
*/
register CLRSEQINTSRC {
address 0x05B
access_mode WO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CLRCTXTDONE 0x40
field CLRSAVEPTRS 0x20
field CLRCFG4DATA 0x10
field CLRCFG4ISTAT 0x08
field CLRCFG4TSTAT 0x04
field CLRCFG4ICMD 0x02
field CLRCFG4TCMD 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SEQ Interrupt Enabled (Shared)
*/
register SEQIMODE {
address 0x05C
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENCTXTDONE 0x40
field ENSAVEPTRS 0x20
field ENCFG4DATA 0x10
field ENCFG4ISTAT 0x08
field ENCFG4TSTAT 0x04
field ENCFG4ICMD 0x02
field ENCFG4TCMD 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Current SCSI Control Block
*/
register CURRSCB {
address 0x05C
access_mode RW
size 2
modes M_SCSI
}
/*
* Data FIFO Status
*/
register MDFFSTAT {
address 0x05D
access_mode RO
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SHCNTNEGATIVE 0x40 /* Rev B or higher */
field SHCNTMINUS1 0x20 /* Rev B or higher */
field LASTSDONE 0x10
field SHVALID 0x08
field DLZERO 0x04 /* FIFO data ends on packet boundary. */
field DATAINFIFO 0x02
field FIFOFREE 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CRC Control
*/
register CRCCONTROL {
address 0x05d
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CRCVALCHKEN 0x40
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* SCSI Test Control
*/
register SCSITEST {
address 0x05E
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CNTRTEST 0x08
field SEL_TXPLL_DEBUG 0x04
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO Queue Tag
*/
register DFFTAG {
address 0x05E
access_mode RW
size 2
modes M_DFF0, M_DFF1
}
/*
* Last SCSI Control Block
*/
register LASTSCB {
address 0x05E
access_mode RW
size 2
modes M_SCSI
}
/*
* SCSI I/O Cell Power-down Control
*/
register IOPDNCTL {
address 0x05F
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DISABLE_OE 0x80
field PDN_IDIST 0x04
field PDN_DIFFSENSE 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Shaddow Host Address.
*/
register SHADDR {
address 0x060
access_mode RO
size 8
modes M_DFF0, M_DFF1
}
/*
* Data Group CRC Interval.
*/
register DGRPCRCI {
address 0x060
access_mode RW
size 2
modes M_CFG
}
/*
* Data Transfer Negotiation Address
*/
register NEGOADDR {
address 0x060
access_mode RW
modes M_SCSI
}
/*
* Data Transfer Negotiation Data - Period Byte
*/
register NEGPERIOD {
address 0x061
access_mode RW
modes M_SCSI
}
/*
* Packetized CRC Interval
*/
register PACKCRCI {
address 0x062
access_mode RW
size 2
modes M_CFG
}
/*
* Data Transfer Negotiation Data - Offset Byte
*/
register NEGOFFSET {
address 0x062
access_mode RW
modes M_SCSI
}
/*
* Data Transfer Negotiation Data - PPR Options
*/
register NEGPPROPTS {
address 0x063
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PPROPT_PACE 0x08
field PPROPT_QAS 0x04
field PPROPT_DT 0x02
field PPROPT_IUT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data Transfer Negotiation Data - Connection Options
*/
register NEGCONOPTS {
address 0x064
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ENAIP 0x08
field ENAUTOATNI 0x04
field ENAUTOATNO 0x02
field WIDEXFER 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Negotiation Table Annex Column Index.
*/
register ANNEXCOL {
address 0x065
access_mode RW
modes M_SCSI
}
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
register SCSCHKN {
address 0x066
access_mode RW
modes M_CFG
field STSELSKIDDIS 0x40
field CURFIFODEF 0x20
field WIDERESEN 0x10
field SDONEMSKDIS 0x08
field DFFACTCLR 0x04
field SHVALIDSTDIS 0x02
field LSTSGCLRDIS 0x01
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
const AHD_ANNEXCOL_PRECOMP 4
const AHD_PRECOMP_MASK 0x07
const AHD_PRECOMP_CUTBACK_17 0x04
const AHD_PRECOMP_CUTBACK_29 0x06
const AHD_PRECOMP_CUTBACK_37 0x07
const AHD_PRECOMP_FASTSLEW 0x40
const AHD_NUM_ANNEXCOLS 4
/*
* Negotiation Table Annex Data Port.
*/
register ANNEXDAT {
address 0x066
access_mode RW
modes M_SCSI
}
/*
* Initiator's Own Id.
* The SCSI ID to use for Selection Out and seen during a reselection..
*/
register IOWNID {
address 0x067
access_mode RW
modes M_SCSI
}
/*
* 960MHz Phase-Locked Loop Control 0
*/
register PLL960CTL0 {
address 0x068
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PLL_VCOSEL 0x80
field PLL_PWDN 0x40
field PLL_NS 0x30
field PLL_ENLUD 0x08
field PLL_ENLPF 0x04
field PLL_DLPF 0x02
field PLL_ENFBM 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Target Own Id
*/
register TOWNID {
address 0x069
access_mode RW
modes M_SCSI
}
/*
* 960MHz Phase-Locked Loop Control 1
*/
register PLL960CTL1 {
address 0x069
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PLL_CNTEN 0x80
field PLL_CNTCLR 0x40
field PLL_RST 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Expander Signature
*/
register XSIG {
address 0x06A
access_mode RW
modes M_SCSI
}
/*
* Shadow Byte Count
*/
register SHCNT {
address 0x068
access_mode RW
size 3
modes M_DFF0, M_DFF1
}
/*
* Selection Out ID
*/
register SELOID {
address 0x06B
access_mode RW
modes M_SCSI
}
/*
* 960-MHz Phase-Locked Loop Test Count
*/
register PLL960CNT0 {
address 0x06A
access_mode RO
size 2
modes M_CFG
}
/*
* 400-MHz Phase-Locked Loop Control 0
*/
register PLL400CTL0 {
address 0x06C
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PLL_VCOSEL 0x80
field PLL_PWDN 0x40
field PLL_NS 0x30
field PLL_ENLUD 0x08
field PLL_ENLPF 0x04
field PLL_DLPF 0x02
field PLL_ENFBM 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Arbitration Fairness
*/
register FAIRNESS {
address 0x06C
access_mode RW
size 2
modes M_SCSI
}
/*
* 400-MHz Phase-Locked Loop Control 1
*/
register PLL400CTL1 {
address 0x06D
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PLL_CNTEN 0x80
field PLL_CNTCLR 0x40
field PLL_RST 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Arbitration Unfairness
*/
register UNFAIRNESS {
address 0x06E
access_mode RW
size 2
modes M_SCSI
}
/*
* 400-MHz Phase-Locked Loop Test Count
*/
register PLL400CNT0 {
address 0x06E
access_mode RO
size 2
modes M_CFG
}
/*
* SCB Page Pointer
*/
register SCBPTR {
address 0x0A8
access_mode RW
size 2
modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI
}
/*
* CMC SCB Array Count
* Number of bytes to transfer between CMC SCB memory and SCBRAM.
* Transfers must be 8byte aligned and sized.
*/
register CCSCBACNT {
address 0x0AB
access_mode RW
modes M_CCHAN
}
/*
* SCB Autopointer
* SCB-Next Address Snooping logic. When an SCB is transferred to
* the card, the next SCB address to be used by the CMC array can
* be autoloaded from that transfer.
*/
register SCBAUTOPTR {
address 0x0AB
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field AUSCBPTR_EN 0x80
field SCBPTR_ADDR 0x38
field SCBPTR_OFF 0x07
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC SG Ram Address Pointer
*/
register CCSGADDR {
address 0x0AC
access_mode RW
modes M_DFF0, M_DFF1
}
/*
* CMC SCB RAM Address Pointer
*/
register CCSCBADDR {
address 0x0AC
access_mode RW
modes M_CCHAN
}
/*
* CMC SCB Ram Back-up Address Pointer
* Indicates the true stop location of transfers halted prior
* to SCBHCNT going to 0.
*/
register CCSCBADR_BK {
address 0x0AC
access_mode RO
modes M_CFG
}
/*
* CMC SG Control
*/
register CCSGCTL {
address 0x0AD
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CCSGDONE 0x80
field SG_CACHE_AVAIL 0x10
field CCSGEN 0x08
field SG_FETCH_REQ 0x02
field CCSGRESET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMD SCB Control
*/
register CCSCBCTL {
address 0x0AD
access_mode RW
modes M_CCHAN
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CCSCBDONE 0x80
field ARRDONE 0x40
field CCARREN 0x10
field CCSCBEN 0x08
field CCSCBDIR 0x04
field CCSCBRESET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC Ram BIST
*/
register CMC_RAMBIST {
address 0x0AD
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SG_ELEMENT_SIZE 0x80
field SCBRAMBIST_FAIL 0x40
field SG_BIST_FAIL 0x20
field SG_BIST_EN 0x10
field CMC_BUFFER_BIST_FAIL 0x02
field CMC_BUFFER_BIST_EN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* CMC SG RAM Data Port
*/
register CCSGRAM {
address 0x0B0
access_mode RW
modes M_DFF0, M_DFF1
}
/*
* CMC SCB RAM Data Port
*/
register CCSCBRAM {
address 0x0B0
access_mode RW
modes M_CCHAN
}
/*
* Flex DMA Address.
*/
register FLEXADR {
address 0x0B0
access_mode RW
size 3
modes M_SCSI
}
/*
* Flex DMA Byte Count
*/
register FLEXCNT {
address 0x0B3
access_mode RW
size 2
modes M_SCSI
}
/*
* Flex DMA Status
*/
register FLEXDMASTAT {
address 0x0B5
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field FLEXDMAERR 0x02
field FLEXDMADONE 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Flex DMA Data Port
*/
register FLEXDATA {
address 0x0B6
access_mode RW
modes M_SCSI
}
/*
* Board Data
*/
register BRDDAT {
address 0x0B8
access_mode RW
modes M_SCSI
}
/*
* Board Control
*/
register BRDCTL {
address 0x0B9
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field FLXARBACK 0x80
field FLXARBREQ 0x40
field BRDADDR 0x38
field BRDEN 0x04
field BRDRW 0x02
field BRDSTB 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Serial EEPROM Address
*/
register SEEADR {
address 0x0BA
access_mode RW
modes M_SCSI
}
/*
* Serial EEPROM Data
*/
register SEEDAT {
address 0x0BC
access_mode RW
size 2
modes M_SCSI
}
/*
* Serial EEPROM Status
*/
register SEESTAT {
address 0x0BE
access_mode RO
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field INIT_DONE 0x80
field SEEOPCODE 0x70
field LDALTID_L 0x08
field SEEARBACK 0x04
field SEEBUSY 0x02
field SEESTART 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Serial EEPROM Control
*/
register SEECTL {
address 0x0BE
access_mode RW
modes M_SCSI
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SEEOPCODE 0x70 {
SEEOP_ERASE 0x70,
SEEOP_READ 0x60,
SEEOP_WRITE 0x50,
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* The following four commands use special
* addresses for differentiation.
*/
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
SEEOP_ERAL 0x40
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
mask SEEOP_EWEN 0x40
mask SEEOP_WALL 0x40
mask SEEOP_EWDS 0x40
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SEERST 0x02
field SEESTART 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
const SEEOP_ERAL_ADDR 0x80
const SEEOP_EWEN_ADDR 0xC0
const SEEOP_WRAL_ADDR 0x40
const SEEOP_EWDS_ADDR 0x00
/*
* SCB Counter
*/
register SCBCNT {
address 0x0BF
access_mode RW
modes M_SCSI
}
/*
* Data FIFO Write Address
* Pointer to the next QWD location to be written to the data FIFO.
*/
register DFWADDR {
address 0x0C0
access_mode RW
size 2
modes M_DFF0, M_DFF1
}
/*
* DSP Filter Control
*/
register DSPFLTRCTL {
address 0x0C0
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field FLTRDISABLE 0x20
field EDGESENSE 0x10
field DSPFCNTSEL 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* DSP Data Channel Control
*/
register DSPDATACTL {
address 0x0C1
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field BYPASSENAB 0x80
field DESQDIS 0x10
field RCVROFFSTDIS 0x04
field XMITOFFSTDIS 0x02
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO Read Address
* Pointer to the next QWD location to be read from the data FIFO.
*/
register DFRADDR {
address 0x0C2
access_mode RW
size 2
modes M_DFF0, M_DFF1
}
/*
* DSP REQ Control
*/
register DSPREQCTL {
address 0x0C2
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MANREQCTL 0xC0
field MANREQDLY 0x3F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* DSP ACK Control
*/
register DSPACKCTL {
address 0x0C3
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MANACKCTL 0xC0
field MANACKDLY 0x3F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO Data
* Read/Write byte port into the data FIFO. The read and write
* FIFO pointers increment with each read and write respectively
* to this port.
*/
register DFDAT {
address 0x0C4
access_mode RW
modes M_DFF0, M_DFF1
}
/*
* DSP Channel Select
*/
register DSPSELECT {
address 0x0C4
access_mode RW
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field AUTOINCEN 0x80
field DSPSEL 0x1F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
const NUMDSPS 0x14
/*
* Write Bias Control
*/
register WRTBIASCTL {
address 0x0C5
access_mode WO
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field AUTOXBCDIS 0x80
field XMITMANVAL 0x3F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
const WRTBIASCTL_CPQ_DEFAULT 0x97
/*
* Receiver Bias Control
*/
register RCVRBIOSCTL {
address 0x0C6
access_mode WO
modes M_CFG
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field AUTORBCDIS 0x80
field RCVRMANVAL 0x3F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Write Bias Calculator
*/
register WRTBIASCALC {
address 0x0C7
access_mode RO
modes M_CFG
}
/*
* Data FIFO Pointers
* Contains the byte offset from DFWADDR and DWRADDR to the current
* FIFO write/read locations.
*/
register DFPTRS {
address 0x0C8
access_mode RW
modes M_DFF0, M_DFF1
}
/*
* Receiver Bias Calculator
*/
register RCVRBIASCALC {
address 0x0C8
access_mode RO
modes M_CFG
}
/*
* Data FIFO Debug Control
*/
register DFDBCTL {
address 0x0C8
access_mode RW
modes M_DFF0, M_DFF1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DFF_CIO_WR_RDY 0x20
field DFF_CIO_RD_RDY 0x10
field DFF_DIR_ERR 0x08
field DFF_RAMBIST_FAIL 0x04
field DFF_RAMBIST_DONE 0x02
field DFF_RAMBIST_EN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Data FIFO Backup Read Pointer
* Contains the data FIFO address to be restored if the last
* data accessed from the data FIFO was not transferred successfully.
*/
register DFBKPTR {
address 0x0C9
access_mode RW
size 2
modes M_DFF0, M_DFF1
}
/*
* Skew Calculator
*/
register SKEWCALC {
address 0x0C9
access_mode RO
modes M_CFG
}
/*
* Data FIFO Space Count
* Number of FIFO locations that are free.
*/
register DFSCNT {
address 0x0CC
access_mode RO
size 2
modes M_DFF0, M_DFF1
}
/*
* Data FIFO Byte Count
* Number of filled FIFO locations.
*/
register DFBCNT {
address 0x0CE
access_mode RO
size 2
modes M_DFF0, M_DFF1
}
/*
* Sequencer Program Overlay Address.
* Low address must be written prior to high address.
*/
register OVLYADDR {
address 0x0D4
modes M_SCSI
size 2
access_mode RW
}
/*
* Sequencer Control 0
* Error detection mode, speed configuration,
* single step, breakpoints and program load.
*/
register SEQCTL0 {
address 0x0D6
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PERRORDIS 0x80
field PAUSEDIS 0x40
field FAILDIS 0x20
field FASTMODE 0x10
field BRKADRINTEN 0x08
field STEP 0x04
field SEQRESET 0x02
field LOADRAM 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Sequencer Control 1
* Instruction RAM Diagnostics
*/
register SEQCTL1 {
address 0x0D7
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field OVRLAY_DATA_CHK 0x08
field RAMBIST_DONE 0x04
field RAMBIST_FAIL 0x02
field RAMBIST_EN 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Sequencer Flags
* Zero and Carry state of the ALU.
*/
register FLAGS {
address 0x0D8
access_mode RO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field ZERO 0x02
field CARRY 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Sequencer Interrupt Control
*/
register SEQINTCTL {
address 0x0D9
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field INTVEC1DSL 0x80
field INT1_CONTEXT 0x20
field SCS_SEQ_INT1M1 0x10
field SCS_SEQ_INT1M0 0x08
field INTMASK 0x06
field IRET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Sequencer RAM Data Port
* Single byte window into the Sequencer Instruction Ram area starting
* at the address specified by OVLYADDR. To write a full instruction word,
* simply write four bytes in succession. OVLYADDR will increment after the
* most significant instrution byte (the byte with the parity bit) is written.
*/
register SEQRAM {
address 0x0DA
access_mode RW
}
/*
* Sequencer Program Counter
* Low byte must be written prior to high byte.
*/
register PRGMCNT {
address 0x0DE
access_mode RW
size 2
}
/*
* Accumulator
*/
register ACCUM {
address 0x0E0
access_mode RW
accumulator
}
/*
* Source Index Register
* Incrementing index for reads of SINDIR and the destination (low byte only)
* for any immediate operands passed in jmp, jc, jnc, call instructions.
* Example:
* mvi 0xFF call some_routine;
*
* Will set SINDEX[0] to 0xFF and call the routine "some_routine.
*/
register SINDEX {
address 0x0E2
access_mode RW
size 2
sindex
}
/*
* Destination Index Register
* Incrementing index for writes to DINDIR. Can be used as a scratch register.
*/
register DINDEX {
address 0x0E4
access_mode RW
size 2
}
/*
* Break Address
* Sequencer instruction breakpoint address address.
*/
register BRKADDR0 {
address 0x0E6
access_mode RW
}
register BRKADDR1 {
address 0x0E6
access_mode RW
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field BRKDIS 0x80 /* Disable Breakpoint */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* All Ones
* All reads to this register return the value 0xFF.
*/
register ALLONES {
address 0x0E8
access_mode RO
allones
}
/*
* All Zeros
* All reads to this register return the value 0.
*/
register ALLZEROS {
address 0x0EA
access_mode RO
allzeros
}
/*
* No Destination
* Writes to this register have no effect.
*/
register NONE {
address 0x0EA
access_mode WO
none
}
/*
* Source Index Indirect
* Reading this register is equivalent to reading (register_base + SINDEX) and
* incrementing SINDEX by 1.
*/
register SINDIR {
address 0x0EC
access_mode RO
}
/*
* Destination Index Indirect
* Writing this register is equivalent to writing to (register_base + DINDEX)
* and incrementing DINDEX by 1.
*/
register DINDIR {
address 0x0ED
access_mode WO
}
/*
* Function One
* 2's complement to bit value conversion. Write the 2's complement value
* (0-7 only) to the top nibble and retrieve the bit indexed by that value
* on the next read of this register.
* Example:
* Write 0x60
* Read 0x40
*/
register FUNCTION1 {
address 0x0F0
access_mode RW
}
/*
* Stack
* Window into the stack. Each stack location is 10 bits wide reported
* low byte followed by high byte. There are 8 stack locations.
*/
register STACK {
address 0x0F2
access_mode RW
}
/*
* Interrupt Vector 1 Address
* Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
*/
register INTVEC1_ADDR {
address 0x0F4
access_mode RW
size 2
modes M_CFG
}
/*
* Current Address
* Address of the SEQRAM instruction currently executing instruction.
*/
register CURADDR {
address 0x0F4
access_mode RW
size 2
modes M_SCSI
}
/*
* Interrupt Vector 2 Address
* Interrupt branch address for HST_SEQ_INT2 interrupts.
*/
register INTVEC2_ADDR {
address 0x0F6
access_mode RW
size 2
modes M_CFG
}
/*
* Last Address
* Address of the SEQRAM instruction executed prior to the current instruction.
*/
register LASTADDR {
address 0x0F6
access_mode RW
size 2
modes M_SCSI
}
register AHD_PCI_CONFIG_BASE {
address 0x100
access_mode RW
size 256
modes M_CFG
}
/* ---------------------- Scratch RAM Offsets ------------------------- */
scratch_ram {
/* Mode Specific */
address 0x0A0
size 8
modes 0, 1, 2, 3
REG0 {
size 2
}
REG1 {
size 2
}
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
REG_ISR {
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
size 2
}
SG_STATE {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SEGS_AVAIL 0x01
field LOADING_NEEDED 0x02
field FETCH_INPROG 0x04
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Track whether the transfer byte count for
* the current data phase is odd.
*/
DATA_COUNT_ODD {
size 1
}
}
scratch_ram {
/* Mode Specific */
address 0x0F8
size 8
modes 0, 1, 2, 3
LONGJMP_ADDR {
size 2
}
LONGJMP_SCB {
size 2
}
ACCUM_SAVE {
size 1
}
}
scratch_ram {
address 0x100
size 128
modes 0, 1, 2, 3
/*
* Per "other-id" execution queues. We use an array of
* tail pointers into lists of SCBs sorted by "other-id".
* The execution head pointer threads the head SCBs for
* each list.
*/
WAITING_SCB_TAILS {
size 32
}
WAITING_TID_HEAD {
size 2
}
WAITING_TID_TAIL {
size 2
}
/*
* SCBID of the next SCB in the new SCB queue.
*/
NEXT_QUEUED_SCB_ADDR {
size 4
}
/*
* head of list of SCBs that have
* completed but have not been
* put into the qoutfifo.
*/
COMPLETE_SCB_HEAD {
size 2
}
/*
* The list of completed SCBs in
* the active DMA.
*/
COMPLETE_SCB_DMAINPROG_HEAD {
size 2
}
/*
* head of list of SCBs that have
* completed but need to be uploaded
* to the host prior to being completed.
*/
COMPLETE_DMA_SCB_HEAD {
size 2
}
/* Counting semaphore to prevent new select-outs */
QFREEZE_COUNT {
size 2
}
/*
* Mode to restore on idle_loop exit.
*/
SAVED_MODE {
size 1
}
/*
* Single byte buffer used to designate the type or message
* to send to a target.
*/
MSG_OUT {
size 1
}
/* Parameters for DMA Logic */
DMAPARAMS {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field PRELOADEN 0x80
field WIDEODD 0x40
field SCSIEN 0x20
field SDMAEN 0x10
field SDMAENACK 0x10
field HDMAEN 0x08
field HDMAENACK 0x08
field DIRECTION 0x04 /* Set indicates PCI->SCSI */
field FIFOFLUSH 0x02
field FIFORESET 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SEQ_FLAGS {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field NOT_IDENTIFIED 0x80
field NO_CDB_SENT 0x40
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
field TARGET_CMD_IS_TAGGED 0x40
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field DPHASE 0x20
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/* Target flags */
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TARG_CMD_PENDING 0x10
field CMDPHASE_PENDING 0x08
field DPHASE_PENDING 0x04
field SPHASE_PENDING 0x02
field NO_DISCONNECT 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Temporary storage for the
* target/channel/lun of a
* reconnecting target
*/
SAVED_SCSIID {
size 1
}
SAVED_LUN {
size 1
}
/*
* The last bus phase as seen by the sequencer.
*/
LASTPHASE {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field CDI 0x80
field IOI 0x40
field MSGI 0x20
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
field P_BUSFREE 0x01
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
enum PHASE_MASK CDO|IOO|MSGO {
P_DATAOUT 0x0,
P_DATAIN IOO,
P_DATAOUT_DT P_DATAOUT|MSGO,
P_DATAIN_DT P_DATAIN|MSGO,
P_COMMAND CDO,
P_MESGOUT CDO|MSGO,
P_STATUS CDO|IOO,
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
P_MESGIN CDO|IOO|MSGO
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* Base address of our shared data with the kernel driver in host
* memory. This includes the qoutfifo and target mode
* incoming command queue.
*/
SHARED_DATA_ADDR {
size 4
}
/*
* Pointer to location in host memory for next
* position in the qoutfifo.
*/
QOUTFIFO_NEXT_ADDR {
size 4
}
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
/*
* Value to "or" into the SCBPTR[1] value to
* indicate that an entry in the QINFIFO is valid.
*/
QOUTFIFO_ENTRY_VALID_TAG {
size 1
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Kernel and sequencer offsets into the queue of
* incoming target mode command descriptors. The
* queue is full when the KERNEL_TQINPOS == TQINPOS.
*/
KERNEL_TQINPOS {
size 1
}
TQINPOS {
size 1
}
ARG_1 {
size 1
mask SEND_MSG 0x80
mask SEND_SENSE 0x40
mask SEND_REJ 0x20
mask MSGOUT_PHASEMIS 0x10
mask EXIT_MSG_LOOP 0x08
mask CONT_MSG_LOOP_WRITE 0x04
mask CONT_MSG_LOOP_READ 0x03
mask CONT_MSG_LOOP_TARG 0x02
alias RETURN_1
}
ARG_2 {
size 1
alias RETURN_2
}
/*
* Snapshot of MSG_OUT taken after each message is sent.
*/
LAST_MSG {
size 1
}
/*
* Sequences the kernel driver has okayed for us. This allows
* the driver to do things like prevent initiator or target
* operations.
*/
SCSISEQ_TEMPLATE {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field MANUALCTL 0x40
field ENSELI 0x20
field ENRSELI 0x10
field MANUALP 0x0C
field ENAUTOATNP 0x02
field ALTSTIM 0x01
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
/*
* The initiator specified tag for this target mode transaction.
*/
INITIATOR_TAG {
size 1
}
SEQ_FLAGS2 {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TARGET_MSG_PENDING 0x02
field SELECTOUT_QFROZEN 0x04
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
ALLOCFIFO_SCBPTR {
size 2
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* Target-mode CDB type to CDB length table used
* in non-packetized operation.
*/
CMDSIZE_TABLE {
size 8
}
}
/************************* Hardware SCB Definition ****************************/
scb {
address 0x180
size 64
modes 0, 1, 2, 3
SCB_RESIDUAL_DATACNT {
size 4
alias SCB_CDB_STORE
}
SCB_RESIDUAL_SGPTR {
size 4
alias SCB_CDB_PTR
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SG_ADDR_MASK 0xf8 /* In the last byte */
field SG_OVERRUN_RESID 0x02 /* In the first byte */
field SG_LIST_NULL 0x01 /* In the first byte */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_SCSI_STATUS {
size 1
}
SCB_TARGET_PHASES {
size 1
}
SCB_TARGET_DATA_DIR {
size 1
}
SCB_TARGET_ITAG {
size 1
}
SCB_SENSE_BUSADDR {
/*
* Only valid if CDB length is less than 13 bytes or
* we are using a CDB pointer. Otherwise contains
* the last 4 bytes of embedded cdb information.
*/
size 4
alias SCB_NEXT_COMPLETE
}
Upgrade to version 1.1 of the aic79xx U320 driver. aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips.
2002-09-26 22:54:00 +00:00
SCB_TAG {
size 2
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
SCB_CDB_LEN {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_TASK_MANAGEMENT {
size 1
}
SCB_NEXT {
alias SCB_NEXT_SCB_BUSADDR
size 2
}
SCB_NEXT2 {
size 2
}
SCB_DATAPTR {
size 8
}
SCB_DATACNT {
/*
* The last byte is really the high address bits for
* the data address.
*/
size 4
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SG_LAST_SEG 0x80 /* In the fourth byte */
field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_SGPTR {
size 4
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field SG_STATUS_VALID 0x04 /* In the first byte */
field SG_FULL_RESID 0x02 /* In the first byte */
field SG_LIST_NULL 0x01 /* In the first byte */
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_CONTROL {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TARGET_SCB 0x80
field DISCENB 0x40
field TAG_ENB 0x20
field MK_MESSAGE 0x10
field STATUS_RCVD 0x08
field DISCONNECTED 0x04
field SCB_TAG_TYPE 0x03
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_SCSIID {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field TID 0xF0
field OID 0x0F
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_LUN {
size 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
field LID 0xff
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
SCB_TASK_ATTRIBUTE {
size 1
}
SCB_BUSADDR {
size 4
}
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
SCB_SPARE {
size 8
alias SCB_PKT_LUN
}
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
SCB_DISCONNECTED_LISTS {
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
size 8
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
}
}
/*********************************** Constants ********************************/
const SEQ_STACK_SIZE 8
const MK_MESSAGE_BIT_OFFSET 4
const TID_SHIFT 4
const TARGET_CMD_CMPLT 0xfe
const INVALID_ADDR 0x80
#define SCB_LIST_NULL 0xff
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
const CCSGADDR_MAX 0x80
const CCSCBADDR_MAX 0x80
const CCSGRAM_MAXSEGS 16
/* Selection Timeout Timer Constants */
const STIMESEL_SHIFT 3
const STIMESEL_MIN 0x18
const STIMESEL_BUG_ADJ 0x8
/* WDTR Message values */
const BUS_8_BIT 0x00
const BUS_16_BIT 0x01
const BUS_32_BIT 0x02
/* Offset maximums */
const MAX_OFFSET 0xfe
const MAX_OFFSET_PACED 0x7f
const HOST_MSG 0xff
/*
* The size of our sense buffers.
* Sense buffer mapping can be handled in either of two ways.
* The first is to allocate a dmamap for each transaction.
* Depending on the architecture, dmamaps can be costly. The
* alternative is to statically map the buffers in much the same
* way we handle our scatter gather lists. The driver implements
* the later.
*/
const AHD_SENSE_BUFSIZE 256
/* Target mode command processing constants */
const CMD_GROUP_CODE_SHIFT 0x05
const STATUS_BUSY 0x08
const STATUS_QUEUE_FULL 0x28
const STATUS_PKT_SENSE 0xFF
const TARGET_DATA_IN 1
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
const SCB_TRANSFER_SIZE_FULL_LUN 56
const SCB_TRANSFER_SIZE_1BYTE_LUN 48
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
const PKT_OVERRUN_BUFSIZE 512
/*
* Downloaded (kernel inserted) constants
*/
const SG_PREFETCH_CNT download
const SG_PREFETCH_CNT_LIMIT download
const SG_PREFETCH_ALIGN_MASK download
const SG_PREFETCH_ADDR_MASK download
const SG_SIZEOF download
const PKT_OVERRUN_BUFOFFSET download
Convert to new assembler field syntax. Add preliminary Rev B definitions. Add QOUTFIFO_ENTRY_VALID_TAG for new qoufifo scheme. Reserve SCB space for large luns.
2002-08-31 06:49:11 +00:00
const SCB_TRANSFER_SIZE download
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X SCSI Controller chip.
2002-06-05 19:52:45 +00:00
/*
* BIOS SCB offsets
*/
const NVRAM_SCB_OFFSET 0x2C
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