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freebsd-dev/sys/conf/options.arm

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Add config magic for arm.
2004-05-14 11:49:40 +00:00
#$FreeBSD$
Add a new option, ARM32_NEW_VM_LAYOUT. When set, we try to put up to 4 L2 tables in one page, instead of the old 1 L2 table <=> 1 page behavior. While I'm there, add ARM9_CACHE_WRITE_THROUGH, which I forgot last time.
2004-11-10 22:08:27 +00:00
ARM9_CACHE_WRITE_THROUGH opt_global.h
Add a new option, ARM_CACHE_LOCK_ENABLE (I forgot it in my last commit).
2005-02-26 22:41:07 +00:00
ARM_CACHE_LOCK_ENABLE opt_global.h
Add new options : PHYSADDR : Address of the physical memory KERNPHYSADDR : Physical address where the kernel starts KERNVIRTADDR : Virtual address of the kernel STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap + Xscale specific options
2004-09-23 22:52:25 +00:00
ARMFPE opt_global.h
Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it maps whole the physical memory, cached, using 1MB section mappings. This reduces the address space available for user processes a bit, but given the amount of memory a typical arm machine has, it is not (yet) a big issue. It then provides a uma_small_alloc() that works as it does for architectures which have a direct mapping.
2006-08-08 20:59:38 +00:00
ARM_KERN_DIRECTMAP opt_vm.h
Add ARM_USE_SMALL_ALLOC.
2005-06-07 23:05:04 +00:00
ARM_USE_SMALL_ALLOC opt_global.h
Add an option to be able to override the value of the AT91 master clock frequency. It'd be better to be able to calculate it at runtime, but we need the information very early, to setup the uart.
2007-10-25 23:02:42 +00:00
AT91C_MASTER_CLOCK opt_global.h
- Obtain main clock frequency dynamically based on CKGR_MCFR register contents. - It is possible to override the dynamic configuration by using AT91C_MAIN_CLOCK option in kernel config. PR: arm/128961 (based on) Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de> Reviewed by: imp Approved by: kib (mentor, implicit)
2008-11-30 22:33:03 +00:00
AT91C_MAIN_CLOCK opt_at91.h
The IQ80321 clock is 200MHz, but the IQ80321 is 198MHz, so add a kernel option to override the frequency
2005-12-09 23:52:51 +00:00
COUNTS_PER_SEC opt_timer.h
Add new options : PHYSADDR : Address of the physical memory KERNPHYSADDR : Physical address where the kernel starts KERNVIRTADDR : Virtual address of the kernel STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap + Xscale specific options
2004-09-23 22:52:25 +00:00
CPU_SA1100 opt_global.h
CPU_SA1110 opt_global.h
CPU_ARM9 opt_global.h
Add CPU_ARM9E
2007-10-31 07:28:45 +00:00
CPU_ARM9E opt_global.h
Finally bring it support for the i80219 XScale processor. Submitted by: Max M. Boyarov <m.boyarov bsd by>
2006-08-24 23:51:28 +00:00
CPU_XSCALE_80219 opt_global.h
Add CPU_XSCALE_81342 before I forget again.
2007-06-11 21:31:13 +00:00
CPU_XSCALE_80321 opt_global.h
CPU_XSCALE_81342 opt_global.h
add CPU_XSCALE_IXP425 Reviewed by: cognet, imp MFC after: 1 month
2006-11-19 23:56:44 +00:00
CPU_XSCALE_IXP425 opt_global.h
Merge WIP from p4: o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
2008-12-13 01:21:37 +00:00
CPU_XSCALE_IXP435 opt_global.h
Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connex boards. This is enough to net-boot to multiuser. Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC add-on boards. I'll be putting some instructions on how to boot this on the Gumstix boards online soon. This is still fairly rough and will be refined over time but I felt it was better to get this out there where other people can help out.
2008-06-06 05:08:09 +00:00
CPU_XSCALE_PXA2X0 opt_global.h
Add two new options, FLASHADDR, which defines the address the flash is mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at at the time the kernel is booted. They are used to detect if the kernel is booted from the onboard flash. Define those for the IQ31244
2007-02-19 01:03:08 +00:00
FLASHADDR opt_global.h
add IXP4XX_FLASH_SIZE config knob that can be used to override the default flash size; this is necessary at the moment because we map all of flash at boot, eventually we'll do this on the fly
2009-03-10 21:49:22 +00:00
IXP4XX_FLASH_SIZE opt_global.h
Add new options : PHYSADDR : Address of the physical memory KERNPHYSADDR : Physical address where the kernel starts KERNVIRTADDR : Virtual address of the kernel STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap + Xscale specific options
2004-09-23 22:52:25 +00:00
KERNPHYSADDR opt_global.h
KERNVIRTADDR opt_global.h
Add two new options, FLASHADDR, which defines the address the flash is mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at at the time the kernel is booted. They are used to detect if the kernel is booted from the onboard flash. Define those for the IQ31244
2007-02-19 01:03:08 +00:00
LOADERRAMADDR opt_global.h
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
PHYSADDR opt_global.h
Introduce basic support for Marvell families of system-on-chip ARM devices: * Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
2008-10-13 20:07:13 +00:00
PHYSMEM_SIZE opt_global.h
Introduce MII_ADDR_BASE option on ARM, which allows to override the default per platform requirements. Notes: - Only used by mge(4) at the moment. - This is very simplified approach and should be replaced by some long-term solution for managing the board/platform configuration (among others the MAC-PHY binding info). Submitted by: Michal Hajduk Obtained from: Semihalf
2009-08-25 09:47:12 +00:00
MII_ADDR_BASE opt_global.h
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
SKYEYE_WORKAROUNDS opt_global.h
Introduce basic support for Marvell families of system-on-chip ARM devices: * Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
2008-10-13 20:07:13 +00:00
SOC_MV_DISCOVERY opt_global.h
SOC_MV_KIRKWOOD opt_global.h
SOC_MV_ORION opt_global.h
Add new options : PHYSADDR : Address of the physical memory KERNPHYSADDR : Physical address where the kernel starts KERNVIRTADDR : Virtual address of the kernel STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap + Xscale specific options
2004-09-23 22:52:25 +00:00
STARTUP_PAGETABLE_ADDR opt_global.h
XSCALE_CACHE_READ_WRITE_ALLOCATE opt_global.h
Add a new option, XSCALE_DISABLE_CCNT, to not use the xscale ccnt as a timecounter (because gxemul doesn't emule it yet).
2006-04-06 17:11:08 +00:00
XSACLE_DISABLE_CCNT opt_timer.h
Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add it as an option. Submitted by: Max N. Boyarov <m.boyarov at bsd dot by>
2006-06-06 01:14:12 +00:00
VERBOSE_INIT_ARM opt_global.h
MFp4: add BWCT kernel configuration
2007-01-05 02:08:35 +00:00
AT91_BWCT opt_at91.h
For the moment, make board configuration a compile time option. This saves space in the final kernel, but at the expense of flexibility to boot the same kernel accross a family of boards.
2006-07-14 21:59:54 +00:00
AT91_TSC opt_at91.h
AT91_KWIKBYTE opt_at91.h
Add support for Cavium Econa CNS11XX ARM boards. These boards were previously know by StarSemi STR9104. Tested by the submitter on an Emprex NSD-100 board. Submitted by: Yohanes Nugroho <yohanes at gmail.com> Reviewed by: freebsd-arm, stas Obtained from: //depot/projects/str91xx/...
2010-01-04 03:35:45 +00:00
CPU_FA526 opt_global.h
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