1999-08-28 01:08:13 +00:00
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/* $FreeBSD$ */
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1998-08-20 08:27:11 +00:00
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/* $NetBSD: tcreg.h,v 1.1 1995/12/20 00:48:36 cgd Exp $ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#ifndef __DEV_TC_TCREG_H__
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#define __DEV_TC_TCREG_H__
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/*
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* TurboChannel bus and register definitions.
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*/
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#define TC_ROM_LLEN 8
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#define TC_ROM_SLEN 4
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#define TC_ROM_TEST_SIZE 16
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#define TC_SLOT_ROM 0x000003e0
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#define TC_SLOT_PROTOROM 0x003c03e0
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typedef struct tc_padchar {
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u_int8_t v;
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u_int8_t pad[3];
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} tc_padchar_t;
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struct tc_rommap {
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tc_padchar_t tcr_width;
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tc_padchar_t tcr_stride;
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tc_padchar_t tcr_rsize;
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tc_padchar_t tcr_ssize;
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u_int8_t tcr_test[TC_ROM_TEST_SIZE];
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tc_padchar_t tcr_rev[TC_ROM_LLEN];
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tc_padchar_t tcr_vendname[TC_ROM_LLEN];
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tc_padchar_t tcr_modname[TC_ROM_LLEN];
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tc_padchar_t tcr_firmtype[TC_ROM_SLEN];
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};
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/*
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* TurboChannel-specific functions and structures for 3000_300.
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*/
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#define TC_3000_300_IR KV(0x00000001e0000000) /* Dense */
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#define TC_3000_300_CSR KV(0x00000001e0000008) /* Dense */
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#define TC_3000_300_MCR KV(0x00000001e0000010) /* Dense */
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#define TC_3000_300_LED KV(0x00000001e0000018) /* Dense */
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/* Interrupt bits. */
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#define TC_3000_300_IR_CXTURBO 0x00000004 /* TC CXTURBO */
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#define TC_3000_300_IR_TCDS 0x00000008 /* TC Dual SCSI */
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#define TC_3000_300_IR_IOASIC 0x00000010 /* TC IOASIC */
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#define TC_3000_300_IR_BCTAGPARITY 0x08000000 /* BC tag par. err. */
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#define TC_3000_300_IR_TCOVERRUN 0x10000000 /* TC overrun */
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#define TC_3000_300_IR_TCTIMEOUT 0x20000000 /* TC timeout on I/O */
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#define TC_3000_300_IR_BCACHEPARITY 0x40000000 /* Bcache par. err. */
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#define TC_3000_300_IR_MEMPARITY 0x80000000 /* Memory par. err. */
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/* Device number "cookies." */
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#define TC_3000_300_DEV_OPT0 0
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#define TC_3000_300_DEV_OPT1 1
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#define TC_3000_300_DEV_TCDS 2
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#define TC_3000_300_DEV_IOASIC 3
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#define TC_3000_300_DEV_CXTURBO 4
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#define TC_3000_300_DEV_BOGUS -1
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#define TC_3000_300_NCOOKIES 5
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#define TC_3000_500_IOSLOT KV(0x00000001c2000000) /* Dense */
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#define TC_3000_500_TCCONFIG KV(0x00000001c2000008) /* Dense */
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#define TC_3000_500_FADR KV(0x00000001c2000010) /* Dense */
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#define TC_3000_500_TCEREG KV(0x00000001c2000018) /* Dense */
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#define TC_3000_500_MEMCONF KV(0x00000001c2200000) /* Dense */
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#define TC_3000_500_IMR_READ KV(0x00000001c2400000) /* Dense */
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#define TC_3000_500_IMR_WRITE KV(0x00000001c281fffc) /* Dense */
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#define TC_3000_500_TCRESET KV(0x00000001c2a00000) /* Dense */
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#define TC_3000_500_IR KV(0x00000001d4800000) /* Sparse */
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#define TC_3000_500_IR_CLEAR KV(0x00000001d4c00000) /* Sparse */
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#define TC_3000_500_SCMAP KV(0x00000001d5000000) /* Sparse */
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/* Interrupt bits. */
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#define TC_3000_500_IR_OPT0 0x00000001 /* TC Option 0 */
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#define TC_3000_500_IR_OPT1 0x00000002 /* TC Option 1 */
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#define TC_3000_500_IR_OPT2 0x00000004 /* TC Option 2 */
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#define TC_3000_500_IR_OPT3 0x00000008 /* TC Option 3 */
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#define TC_3000_500_IR_OPT4 0x00000010 /* TC Option 4 */
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#define TC_3000_500_IR_OPT5 0x00000020 /* TC Option 5 */
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#define TC_3000_500_IR_TCDS 0x00000040 /* TC Dual SCSI */
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#define TC_3000_500_IR_IOASIC 0x00000080 /* TC IOASIC */
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#define TC_3000_500_IR_CXTURBO 0x00000100 /* TC CXTURBO */
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#define TC_3000_500_IR_ERR2 0x00080000 /* Second error */
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#define TC_3000_500_IR_DMABE 0x00100000 /* DMA buffer error */
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#define TC_3000_500_IR_DMA2K 0x00200000 /* DMA 2K boundary */
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#define TC_3000_500_IR_TCRESET 0x00400000 /* TC reset in prog. */
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#define TC_3000_500_IR_TCPAR 0x00800000 /* TC parity error */
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#define TC_3000_500_IR_DMATAG 0x01000000 /* DMA tag error */
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#define TC_3000_500_IR_DMASBE 0x02000000 /* Single-bit error */
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#define TC_3000_500_IR_DMADBE 0x04000000 /* Double-bit error */
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#define TC_3000_500_IR_TCTIMEOUT 0x08000000 /* TC timeout on I/O */
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#define TC_3000_500_IR_DMABLOCK 0x10000000 /* DMA block too long */
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#define TC_3000_500_IR_IOADDR 0x20000000 /* Invalid I/O addr */
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#define TC_3000_500_IR_DMASG 0x40000000 /* SG invalid */
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#define TC_3000_500_IR_SGPAR 0x80000000 /* SG parity error */
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/* I/O Slot Configuration (IOSLOT) bits. */
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#define IOSLOT_P 0x04 /* Parity enable. */
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#define IOSLOT_B 0x02 /* Block-mode write. */
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#define IOSLOT_S 0x01 /* DMA scatter/gather mode. */
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/* I/O Slot Configuration (IOSLOT) offsets. */
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#define TC_IOSLOT_OPT0 0 /* Option 0 PBS offset. */
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#define TC_IOSLOT_OPT1 1 /* Option 1 PBS offset. */
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#define TC_IOSLOT_OPT2 2 /* Option 2 PBS offset. */
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#define TC_IOSLOT_OPT3 3 /* Option 3 PBS offset. */
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#define TC_IOSLOT_OPT4 4 /* Option 4 PBS offset. */
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#define TC_IOSLOT_OPT5 5 /* Option 5 PBS offset. */
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#define TC_IOSLOT_SCSI 6 /* Option SCSI PBS offset. */
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#define TC_IOSLOT_IOASIC 7 /* Option IOASIC PBS offset. */
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#define TC_IOSLOT_CXTURBO 8 /* Option CXTURBO PBS offset. */
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/* Device number "cookies." */
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#define TC_3000_500_DEV_OPT0 0
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#define TC_3000_500_DEV_OPT1 1
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#define TC_3000_500_DEV_OPT2 2
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#define TC_3000_500_DEV_OPT3 3
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#define TC_3000_500_DEV_OPT4 4
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#define TC_3000_500_DEV_OPT5 5
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#define TC_3000_500_DEV_TCDS 6
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#define TC_3000_500_DEV_IOASIC 7
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#define TC_3000_500_DEV_CXTURBO 8
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#define TC_3000_500_DEV_BOGUS -1
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#define TC_3000_500_NCOOKIES 9
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#endif /* __DEV_TC_TCREG_H__ */
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