41 lines
1.2 KiB
Makefile
41 lines
1.2 KiB
Makefile
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# $NetBSD: cmdline-undefined.mk,v 1.2 2020/11/04 04:49:33 rillig Exp $
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#
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# Tests for undefined variable expressions in the command line.
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all:
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# When the command line is parsed, variable assignments using the
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# '=' assignment operator do get their variable name expanded
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# (which probably occurs rarely in practice, if at all), but their
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# variable value is not expanded, as usual.
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#
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@echo 'The = assignment operator'
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@${.MAKE} -f ${MAKEFILE} print-undefined \
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CMDLINE='Undefined is $${UNDEFINED}.'
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@echo
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# The interesting case is using the ':=' assignment operator, which
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# expands its right-hand side. But only those variables that are
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# defined.
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@echo 'The := assignment operator'
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@${.MAKE} -f ${MAKEFILE} print-undefined \
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CMDLINE:='Undefined is $${UNDEFINED}.'
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@echo
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.if make(print-undefined)
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.MAKEFLAGS: MAKEFLAGS_ASSIGN='Undefined is $${UNDEFINED}.'
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.MAKEFLAGS: MAKEFLAGS_SUBST:='Undefined is $${UNDEFINED}.'
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.info From the command line: ${CMDLINE}
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.info From .MAKEFLAGS '=': ${MAKEFLAGS_ASSIGN}
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.info From .MAKEFLAGS ':=': ${MAKEFLAGS_SUBST}
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UNDEFINED?= now defined
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.info From the command line: ${CMDLINE}
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.info From .MAKEFLAGS '=': ${MAKEFLAGS_ASSIGN}
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.info From .MAKEFLAGS ':=': ${MAKEFLAGS_SUBST}
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print-undefined:
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.endif
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