2013-10-23 12:29:39 +00:00
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/*-
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2017-11-27 15:04:10 +00:00
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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2013-10-23 12:29:39 +00:00
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* Copyright (c) 2001 Tsubai Masanari.
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
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2017-10-01 16:48:36 +00:00
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* Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
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2013-10-23 12:29:39 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2017-10-01 16:48:36 +00:00
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/*
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* Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC.
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*
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* This controller can only perform complete transfers, it does not provide
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* low-level control over sending start/repeat-start/stop sequences on the bus.
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* In addition, bugs in the silicon make it somewhat difficult to perform a
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* repeat-start, and limit the repeat-start to a read following a write on
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* the same slave device. (The i2c protocol allows a repeat start to change
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* direction or not, and change slave address or not at any time.)
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*
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* The repeat-start bug and workaround are described in a problem report at
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* https://github.com/raspberrypi/linux/issues/254 with the crucial part being
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* in a comment block from a fragment of a GPU i2c driver, containing this:
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*
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* -----------------------------------------------------------------------------
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* - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count
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* - in the IDLE state if start is set.
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* -
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* - We want to generate a ReSTART not a STOP at the end of the TX phase. In
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* - order to do that we must ensure the state machine goes RACK1 -> RACK2 ->
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* - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1).
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* -
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* - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have
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* - already set, ready to be sampled:
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* - READ ; rw_bit <= I2CC bit 0 -- must be "read"
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* - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP
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* - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount
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* -
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* - The plan to do this is:
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* - 1. Start the sub-address write, but don't let it finish
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* - (keep xfer_count > 0)
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* - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence
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* - 3. Let TX finish (write the rest of the data)
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* - 4. Read back data as it arrives
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* -----------------------------------------------------------------------------
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*
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* The transfer function below scans the list of messages passed to it, looking
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* for a read following a write to the same slave. When it finds that, it
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* starts the write without prefilling the tx fifo, which holds xfer_count>0,
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* then presets the direction, length, and start command for the following read,
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* as described above. Then the tx fifo is filled and the rest of the transfer
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* proceeds as normal, with the controller automatically supplying a
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* repeat-start on the bus when the write operation finishes.
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*
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* XXX I suspect the controller may be able to do a repeat-start on any
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* write->read or write->write transition, even when the slave addresses differ.
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* It's unclear whether the slave address can be prestaged along with the
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* direction and length while the write xfer_count is being held at zero. In
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* fact, if it can't do this, then it couldn't be used to read EDID data.
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*/
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2013-10-23 12:29:39 +00:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
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#include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
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#include "iicbus_if.h"
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2016-10-12 03:00:42 +00:00
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static struct ofw_compat_data compat_data[] = {
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{"broadcom,bcm2835-bsc", 1},
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{"brcm,bcm2708-i2c", 1},
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2017-03-25 22:58:37 +00:00
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{"brcm,bcm2835-i2c", 1},
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2016-10-12 03:00:42 +00:00
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{NULL, 0}
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};
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2017-10-01 16:48:36 +00:00
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#define DEVICE_DEBUGF(sc, lvl, fmt, args...) \
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if ((lvl) <= (sc)->sc_debug) \
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device_printf((sc)->sc_dev, fmt, ##args)
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#define DEBUGF(sc, lvl, fmt, args...) \
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if ((lvl) <= (sc)->sc_debug) \
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printf(fmt, ##args)
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2013-10-23 12:29:39 +00:00
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static void bcm_bsc_intr(void *);
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2014-12-27 18:54:39 +00:00
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static int bcm_bsc_detach(device_t);
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2013-10-23 12:29:39 +00:00
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static void
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bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
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uint32_t value)
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{
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uint32_t reg;
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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reg = BCM_BSC_READ(sc, off);
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reg &= ~mask;
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reg |= value;
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BCM_BSC_WRITE(sc, off, reg);
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}
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static int
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bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_bsc_softc *sc;
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uint32_t clk;
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sc = (struct bcm_bsc_softc *)arg1;
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BCM_BSC_LOCK(sc);
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clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
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BCM_BSC_UNLOCK(sc);
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clk &= 0xffff;
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if (clk == 0)
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clk = 32768;
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clk = BCM_BSC_CORE_CLK / clk;
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2014-12-27 18:54:39 +00:00
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return (sysctl_handle_int(oidp, &clk, 0, req));
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2013-10-23 12:29:39 +00:00
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}
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static int
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bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_bsc_softc *sc;
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uint32_t clkt;
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int error;
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sc = (struct bcm_bsc_softc *)arg1;
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BCM_BSC_LOCK(sc);
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clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
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BCM_BSC_UNLOCK(sc);
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clkt &= 0xffff;
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error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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BCM_BSC_LOCK(sc);
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BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
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BCM_BSC_UNLOCK(sc);
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return (0);
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}
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static int
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bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_bsc_softc *sc;
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uint32_t clk, reg;
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int error;
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sc = (struct bcm_bsc_softc *)arg1;
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BCM_BSC_LOCK(sc);
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reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
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BCM_BSC_UNLOCK(sc);
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reg >>= 16;
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error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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BCM_BSC_LOCK(sc);
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clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
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clk = BCM_BSC_CORE_CLK / clk;
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if (reg > clk / 2)
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reg = clk / 2 - 1;
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bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
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BCM_BSC_UNLOCK(sc);
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return (0);
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}
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static int
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bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_bsc_softc *sc;
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uint32_t clk, reg;
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int error;
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sc = (struct bcm_bsc_softc *)arg1;
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BCM_BSC_LOCK(sc);
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reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
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BCM_BSC_UNLOCK(sc);
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reg &= 0xffff;
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error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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BCM_BSC_LOCK(sc);
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clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
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clk = BCM_BSC_CORE_CLK / clk;
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if (reg > clk / 2)
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reg = clk / 2 - 1;
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bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
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BCM_BSC_UNLOCK(sc);
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return (0);
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}
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static void
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bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
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{
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid *tree_node;
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struct sysctl_oid_list *tree;
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/*
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* Add system sysctl tree/handlers.
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*/
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ctx = device_get_sysctl_ctx(sc->sc_dev);
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tree_node = device_get_sysctl_tree(sc->sc_dev);
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tree = SYSCTL_CHILDREN(tree_node);
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2014-12-27 18:54:39 +00:00
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
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2020-02-26 14:26:36 +00:00
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CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
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sc, sizeof(*sc),
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2013-10-23 12:29:39 +00:00
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bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
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2020-02-26 14:26:36 +00:00
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CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
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sc, sizeof(*sc),
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2013-10-23 12:29:39 +00:00
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bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
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2020-02-26 14:26:36 +00:00
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CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
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sc, sizeof(*sc),
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2013-10-23 12:29:39 +00:00
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bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
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2020-02-26 14:26:36 +00:00
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CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
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sc, sizeof(*sc),
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2013-10-23 12:29:39 +00:00
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bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
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2017-10-01 16:48:36 +00:00
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SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug",
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CTLFLAG_RWTUN, &sc->sc_debug, 0,
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"Enable debug; 1=reads/writes, 2=add starts/stops");
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2013-10-23 12:29:39 +00:00
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}
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static void
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bcm_bsc_reset(struct bcm_bsc_softc *sc)
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{
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2014-10-24 22:06:21 +00:00
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/* Enable the BSC Controller, disable interrupts. */
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BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
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2013-10-23 12:29:39 +00:00
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/* Clear pending interrupts. */
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BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
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BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
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/* Clear the FIFO. */
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bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
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BCM_BSC_CTRL_CLEAR0);
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}
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static int
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bcm_bsc_probe(device_t dev)
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{
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2014-02-02 19:17:28 +00:00
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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2016-10-12 03:00:42 +00:00
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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2013-10-23 12:29:39 +00:00
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return (ENXIO);
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device_set_desc(dev, "BCM2708/2835 BSC controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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bcm_bsc_attach(device_t dev)
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{
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struct bcm_bsc_softc *sc;
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2018-04-08 00:56:19 +00:00
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int rid;
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2013-10-23 12:29:39 +00:00
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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|
|
sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
|
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
|
|
if (!sc->sc_irq_res) {
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
|
|
device_printf(dev, "cannot allocate interrupt\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Hook up our interrupt handler. */
|
|
|
|
if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
|
|
NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
|
|
device_printf(dev, "cannot setup the interrupt handler\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
|
|
|
|
|
|
|
|
bcm_bsc_sysctl_init(sc);
|
|
|
|
|
|
|
|
/* Enable the BSC controller. Flush the FIFO. */
|
|
|
|
BCM_BSC_LOCK(sc);
|
|
|
|
bcm_bsc_reset(sc);
|
|
|
|
BCM_BSC_UNLOCK(sc);
|
|
|
|
|
2014-12-27 18:54:39 +00:00
|
|
|
sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
|
|
|
|
if (sc->sc_iicbus == NULL) {
|
|
|
|
bcm_bsc_detach(dev);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2013-10-23 12:29:39 +00:00
|
|
|
|
2017-09-13 16:54:27 +00:00
|
|
|
/* Probe and attach the iicbus when interrupts are available. */
|
2019-12-13 21:39:20 +00:00
|
|
|
return (bus_delayed_attach_children(dev));
|
2013-10-23 12:29:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bcm_bsc_detach(device_t dev)
|
|
|
|
{
|
|
|
|
struct bcm_bsc_softc *sc;
|
|
|
|
|
|
|
|
bus_generic_detach(dev);
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2017-10-01 16:48:36 +00:00
|
|
|
if (sc->sc_iicbus != NULL)
|
|
|
|
device_delete_child(dev, sc->sc_iicbus);
|
2013-10-23 12:29:39 +00:00
|
|
|
mtx_destroy(&sc->sc_mtx);
|
|
|
|
if (sc->sc_intrhand)
|
|
|
|
bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
|
|
|
|
if (sc->sc_irq_res)
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
|
|
|
|
if (sc->sc_mem_res)
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
static void
|
|
|
|
bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc)
|
|
|
|
{
|
|
|
|
uint32_t status;
|
|
|
|
|
|
|
|
/* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */
|
|
|
|
do {
|
|
|
|
if (sc->sc_resid == 0) {
|
|
|
|
sc->sc_data = sc->sc_curmsg->buf;
|
|
|
|
sc->sc_dlen = sc->sc_curmsg->len;
|
|
|
|
sc->sc_resid = sc->sc_dlen;
|
|
|
|
++sc->sc_curmsg;
|
|
|
|
}
|
|
|
|
do {
|
|
|
|
*sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA);
|
|
|
|
DEBUGF(sc, 1, "0x%02x ", *sc->sc_data);
|
|
|
|
++sc->sc_data;
|
|
|
|
--sc->sc_resid;
|
|
|
|
--sc->sc_totlen;
|
|
|
|
status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
|
|
|
|
} while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD));
|
|
|
|
} while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc)
|
|
|
|
{
|
|
|
|
uint32_t status;
|
|
|
|
|
|
|
|
/* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */
|
|
|
|
do {
|
|
|
|
if (sc->sc_resid == 0) {
|
|
|
|
sc->sc_data = sc->sc_curmsg->buf;
|
|
|
|
sc->sc_dlen = sc->sc_curmsg->len;
|
|
|
|
sc->sc_resid = sc->sc_dlen;
|
|
|
|
++sc->sc_curmsg;
|
|
|
|
}
|
|
|
|
do {
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
|
|
|
|
DEBUGF(sc, 1, "0x%02x ", *sc->sc_data);
|
|
|
|
++sc->sc_data;
|
|
|
|
--sc->sc_resid;
|
|
|
|
--sc->sc_totlen;
|
|
|
|
status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
|
|
|
|
} while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD));
|
|
|
|
/*
|
|
|
|
* If a repeat-start was pending and we just hit the end of a tx
|
|
|
|
* buffer, see if it's also the end of the writes that preceeded
|
|
|
|
* the repeat-start. If so, log the repeat-start and the start
|
|
|
|
* of the following read, and return because we're not writing
|
|
|
|
* anymore (and TXD will be true because there's room to write
|
|
|
|
* in the fifo).
|
|
|
|
*/
|
|
|
|
if (sc->sc_replen > 0 && sc->sc_resid == 0) {
|
|
|
|
sc->sc_replen -= sc->sc_dlen;
|
|
|
|
if (sc->sc_replen == 0) {
|
|
|
|
DEBUGF(sc, 1, " err=0\n");
|
|
|
|
DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n",
|
|
|
|
sc->sc_curmsg->slave | 0x01);
|
|
|
|
DEVICE_DEBUGF(sc, 1,
|
|
|
|
"read 0x%02x len %d: ",
|
|
|
|
sc->sc_curmsg->slave | 0x01,
|
|
|
|
sc->sc_totlen);
|
|
|
|
sc->sc_flags |= BCM_I2C_READ;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD));
|
|
|
|
}
|
|
|
|
|
2013-10-23 12:29:39 +00:00
|
|
|
static void
|
|
|
|
bcm_bsc_intr(void *arg)
|
|
|
|
{
|
|
|
|
struct bcm_bsc_softc *sc;
|
|
|
|
uint32_t status;
|
|
|
|
|
|
|
|
sc = (struct bcm_bsc_softc *)arg;
|
|
|
|
|
|
|
|
BCM_BSC_LOCK(sc);
|
|
|
|
|
|
|
|
/* The I2C interrupt is shared among all the BSC controllers. */
|
|
|
|
if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
|
|
|
|
BCM_BSC_UNLOCK(sc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
|
2017-10-01 16:48:36 +00:00
|
|
|
DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status);
|
2013-10-23 12:29:39 +00:00
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/* RXD and DONE can assert together, empty fifo before checking done. */
|
|
|
|
if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD))
|
|
|
|
bcm_bsc_empty_rx_fifo(sc);
|
2013-10-23 12:29:39 +00:00
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/* Check for completion. */
|
|
|
|
if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) {
|
|
|
|
sc->sc_flags |= BCM_I2C_DONE;
|
|
|
|
if (status & BCM_BSC_STATUS_ERRBITS)
|
|
|
|
sc->sc_flags |= BCM_I2C_ERROR;
|
2013-10-23 12:29:39 +00:00
|
|
|
/* Disable interrupts. */
|
|
|
|
bcm_bsc_reset(sc);
|
2017-10-01 16:48:36 +00:00
|
|
|
wakeup(sc);
|
|
|
|
} else if (!(sc->sc_flags & BCM_I2C_READ)) {
|
|
|
|
/*
|
|
|
|
* Don't check for TXD until after determining whether the
|
|
|
|
* transfer is complete; TXD will be asserted along with ERR or
|
|
|
|
* DONE if there is room in the fifo.
|
|
|
|
*/
|
2017-12-18 02:34:37 +00:00
|
|
|
if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0)
|
2017-10-01 16:48:36 +00:00
|
|
|
bcm_bsc_fill_tx_fifo(sc);
|
2013-10-23 12:29:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
BCM_BSC_UNLOCK(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
|
|
|
|
{
|
|
|
|
struct bcm_bsc_softc *sc;
|
2017-10-01 16:48:36 +00:00
|
|
|
struct iic_msg *endmsgs, *nxtmsg;
|
|
|
|
uint32_t readctl, status;
|
|
|
|
int err;
|
|
|
|
uint16_t curlen;
|
|
|
|
uint8_t curisread, curslave, nxtisread, nxtslave;
|
2013-10-23 12:29:39 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
BCM_BSC_LOCK(sc);
|
|
|
|
|
|
|
|
/* If the controller is busy wait until it is available. */
|
|
|
|
while (sc->sc_flags & BCM_I2C_BUSY)
|
2014-10-20 13:36:52 +00:00
|
|
|
mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0);
|
2013-10-23 12:29:39 +00:00
|
|
|
|
|
|
|
/* Now we have control over the BSC controller. */
|
|
|
|
sc->sc_flags = BCM_I2C_BUSY;
|
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs);
|
|
|
|
|
2013-10-23 12:29:39 +00:00
|
|
|
/* Clear the FIFO and the pending interrupts. */
|
|
|
|
bcm_bsc_reset(sc);
|
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/*
|
|
|
|
* Perform all the transfers requested in the array of msgs. Note that
|
|
|
|
* it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance
|
|
|
|
* sc->sc_curmsg through the array of messages, as the data from each
|
|
|
|
* message is fully consumed, but it is this loop that notices when we
|
|
|
|
* have no more messages to process.
|
|
|
|
*/
|
2013-10-23 12:29:39 +00:00
|
|
|
err = 0;
|
2017-10-01 16:48:36 +00:00
|
|
|
sc->sc_resid = 0;
|
|
|
|
sc->sc_curmsg = msgs;
|
|
|
|
endmsgs = &msgs[nmsgs];
|
|
|
|
while (sc->sc_curmsg < endmsgs) {
|
|
|
|
readctl = 0;
|
|
|
|
curslave = sc->sc_curmsg->slave >> 1;
|
|
|
|
curisread = sc->sc_curmsg->flags & IIC_M_RD;
|
|
|
|
sc->sc_replen = 0;
|
|
|
|
sc->sc_totlen = sc->sc_curmsg->len;
|
|
|
|
/*
|
|
|
|
* Scan for scatter/gather IO (same slave and direction) or
|
|
|
|
* repeat-start (read following write for the same slave).
|
|
|
|
*/
|
|
|
|
for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) {
|
|
|
|
nxtslave = nxtmsg->slave >> 1;
|
|
|
|
if (curslave == nxtslave) {
|
|
|
|
nxtisread = nxtmsg->flags & IIC_M_RD;
|
|
|
|
if (curisread == nxtisread) {
|
|
|
|
/*
|
|
|
|
* Same slave and direction, this
|
|
|
|
* message will be part of the same
|
|
|
|
* transfer as the previous one.
|
|
|
|
*/
|
|
|
|
sc->sc_totlen += nxtmsg->len;
|
|
|
|
continue;
|
|
|
|
} else if (curisread == IIC_M_WR) {
|
|
|
|
/*
|
|
|
|
* Read after write to same slave means
|
|
|
|
* repeat-start, remember how many bytes
|
|
|
|
* come before the repeat-start, switch
|
|
|
|
* the direction to IIC_M_RD, and gather
|
|
|
|
* up following reads to the same slave.
|
|
|
|
*/
|
|
|
|
curisread = IIC_M_RD;
|
|
|
|
sc->sc_replen = sc->sc_totlen;
|
|
|
|
sc->sc_totlen += nxtmsg->len;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2013-10-23 12:29:39 +00:00
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/*
|
|
|
|
* curslave and curisread temporaries from above may refer to
|
|
|
|
* the after-repstart msg, reset them to reflect sc_curmsg.
|
|
|
|
*/
|
|
|
|
curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0;
|
|
|
|
curslave = sc->sc_curmsg->slave | curisread;
|
2013-10-23 12:29:39 +00:00
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/* Write the slave address. */
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1);
|
|
|
|
|
|
|
|
DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Either set up read length and direction variables for a
|
|
|
|
* simple transfer or get the hardware started on the first
|
|
|
|
* piece of a transfer that involves a repeat-start and set up
|
|
|
|
* the read length and direction vars for the second piece.
|
|
|
|
*/
|
|
|
|
if (sc->sc_replen == 0) {
|
|
|
|
DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ",
|
2017-12-18 00:15:53 +00:00
|
|
|
(curisread) ? "read" : "write", curslave,
|
2017-10-01 16:48:36 +00:00
|
|
|
sc->sc_totlen);
|
|
|
|
curlen = sc->sc_totlen;
|
|
|
|
if (curisread) {
|
|
|
|
readctl = BCM_BSC_CTRL_READ;
|
|
|
|
sc->sc_flags |= BCM_I2C_READ;
|
|
|
|
} else {
|
|
|
|
readctl = 0;
|
|
|
|
sc->sc_flags &= ~BCM_I2C_READ;
|
2013-10-23 12:29:39 +00:00
|
|
|
}
|
|
|
|
} else {
|
2017-10-01 16:48:36 +00:00
|
|
|
DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ",
|
2017-12-18 00:15:53 +00:00
|
|
|
(curisread) ? "read" : "write", curslave,
|
2017-10-01 16:48:36 +00:00
|
|
|
sc->sc_replen);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start the write transfer with an empty fifo and wait
|
|
|
|
* for the 'transfer active' status bit to light up;
|
|
|
|
* that indicates that the hardware has latched the
|
|
|
|
* direction and length for the write, and we can safely
|
|
|
|
* reload those registers and issue the start for the
|
|
|
|
* following read; interrupts are not enabled here.
|
|
|
|
*/
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen);
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
|
|
|
|
BCM_BSC_CTRL_ST);
|
|
|
|
do {
|
|
|
|
status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
|
|
|
|
if (status & BCM_BSC_STATUS_ERR) {
|
|
|
|
/* no ACK on slave addr */
|
|
|
|
err = EIO;
|
|
|
|
goto xfer_done;
|
|
|
|
}
|
|
|
|
} while ((status & BCM_BSC_STATUS_TA) == 0);
|
|
|
|
/*
|
|
|
|
* Set curlen and readctl for the repeat-start read that
|
|
|
|
* we need to set up below, but set sc_flags to write,
|
|
|
|
* because that is the operation in progress right now.
|
|
|
|
*/
|
|
|
|
curlen = sc->sc_totlen - sc->sc_replen;
|
|
|
|
readctl = BCM_BSC_CTRL_READ;
|
|
|
|
sc->sc_flags &= ~BCM_I2C_READ;
|
2013-10-23 12:29:39 +00:00
|
|
|
}
|
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/*
|
|
|
|
* Start the transfer with interrupts enabled, then if doing a
|
|
|
|
* write, fill the tx fifo. Not prefilling the fifo until after
|
|
|
|
* this start command is the key workaround for making
|
|
|
|
* repeat-start work, and it's harmless to do it in this order
|
|
|
|
* for a regular write too.
|
|
|
|
*/
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen);
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN |
|
|
|
|
BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL);
|
|
|
|
|
|
|
|
if (!(sc->sc_curmsg->flags & IIC_M_RD)) {
|
|
|
|
bcm_bsc_fill_tx_fifo(sc);
|
|
|
|
}
|
2013-10-23 12:29:39 +00:00
|
|
|
|
|
|
|
/* Wait for the transaction to complete. */
|
2017-10-01 16:48:36 +00:00
|
|
|
while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) {
|
|
|
|
err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz);
|
|
|
|
}
|
2014-10-20 18:04:20 +00:00
|
|
|
/* Check for errors. */
|
2014-11-12 03:07:46 +00:00
|
|
|
if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR))
|
2013-10-23 12:29:39 +00:00
|
|
|
err = EIO;
|
2017-10-01 16:48:36 +00:00
|
|
|
xfer_done:
|
|
|
|
DEBUGF(sc, 1, " err=%d\n", err);
|
|
|
|
DEVICE_DEBUGF(sc, 2, "stop\n");
|
2014-10-20 18:04:20 +00:00
|
|
|
if (err != 0)
|
2013-10-23 12:29:39 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-10-01 16:48:36 +00:00
|
|
|
/* Disable interrupts, clean fifo, etc. */
|
|
|
|
bcm_bsc_reset(sc);
|
|
|
|
|
2013-10-23 12:29:39 +00:00
|
|
|
/* Clean the controller flags. */
|
|
|
|
sc->sc_flags = 0;
|
|
|
|
|
2014-10-20 13:36:52 +00:00
|
|
|
/* Wake up the threads waiting for bus. */
|
|
|
|
wakeup(dev);
|
|
|
|
|
2013-10-23 12:29:39 +00:00
|
|
|
BCM_BSC_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
2014-10-24 22:06:21 +00:00
|
|
|
static int
|
|
|
|
bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
|
|
|
|
{
|
|
|
|
struct bcm_bsc_softc *sc;
|
2014-12-27 18:54:39 +00:00
|
|
|
uint32_t busfreq;
|
|
|
|
|
2014-10-24 22:06:21 +00:00
|
|
|
sc = device_get_softc(dev);
|
|
|
|
BCM_BSC_LOCK(sc);
|
|
|
|
bcm_bsc_reset(sc);
|
2014-12-27 18:54:39 +00:00
|
|
|
if (sc->sc_iicbus == NULL)
|
|
|
|
busfreq = 100000;
|
|
|
|
else
|
|
|
|
busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
|
|
|
|
BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
|
2014-10-24 22:06:21 +00:00
|
|
|
BCM_BSC_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (IIC_ENOADDR);
|
|
|
|
}
|
|
|
|
|
2013-10-23 12:29:39 +00:00
|
|
|
static phandle_t
|
|
|
|
bcm_bsc_get_node(device_t bus, device_t dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
/* We only have one child, the I2C bus, which needs our own node. */
|
|
|
|
return (ofw_bus_get_node(bus));
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t bcm_bsc_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, bcm_bsc_probe),
|
|
|
|
DEVMETHOD(device_attach, bcm_bsc_attach),
|
|
|
|
DEVMETHOD(device_detach, bcm_bsc_detach),
|
|
|
|
|
|
|
|
/* iicbus interface */
|
2014-10-24 22:06:21 +00:00
|
|
|
DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset),
|
2013-10-23 12:29:39 +00:00
|
|
|
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
|
|
|
DEVMETHOD(iicbus_transfer, bcm_bsc_transfer),
|
|
|
|
|
|
|
|
/* ofw_bus interface */
|
|
|
|
DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node),
|
|
|
|
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t bcm_bsc_driver = {
|
|
|
|
"iichb",
|
|
|
|
bcm_bsc_methods,
|
|
|
|
sizeof(struct bcm_bsc_softc),
|
|
|
|
};
|
|
|
|
|
2022-04-20 16:19:37 +00:00
|
|
|
DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, 0, 0);
|
2022-05-09 21:26:44 +00:00
|
|
|
DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, 0, 0);
|