2018-12-12 22:08:43 +00:00
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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2021-02-17 15:28:46 +00:00
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#include <sys/bitset.h>
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2018-12-12 22:08:43 +00:00
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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2021-02-17 15:28:46 +00:00
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#include <arm/arm/gic_common.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "msi_if.h"
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2018-12-12 22:08:43 +00:00
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#include "pic_if.h"
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#define MV_AP806_GICP_MAX_NIRQS 207
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2021-02-17 15:28:46 +00:00
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MALLOC_DECLARE(M_GICP);
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MALLOC_DEFINE(M_GICP, "gicp", "Marvell gicp driver");
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2018-12-12 22:08:43 +00:00
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struct mv_ap806_gicp_softc {
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device_t dev;
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device_t parent;
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struct resource *res;
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ssize_t spi_ranges_cnt;
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uint32_t *spi_ranges;
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2019-10-20 10:48:27 +00:00
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struct intr_map_data_fdt *parent_map_data;
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2021-02-17 15:28:46 +00:00
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ssize_t msi_bitmap_size; /* Nr of bits in the bitmap. */
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BITSET_DEFINE_VAR() *msi_bitmap;
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2018-12-12 22:08:43 +00:00
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};
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static struct ofw_compat_data compat_data[] = {
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{"marvell,ap806-gicp", 1},
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{NULL, 0}
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};
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#define RD4(sc, reg) bus_read_4((sc)->res, (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
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2021-02-17 15:28:46 +00:00
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static msi_alloc_msi_t mv_ap806_gicp_alloc_msi;
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static msi_release_msi_t mv_ap806_gicp_release_msi;
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static msi_map_msi_t mv_ap806_gicp_map_msi;
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2018-12-12 22:08:43 +00:00
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static int
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mv_ap806_gicp_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell GICP");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mv_ap806_gicp_attach(device_t dev)
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{
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struct mv_ap806_gicp_softc *sc;
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phandle_t node, xref, intr_parent;
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2021-02-17 15:28:46 +00:00
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int i, rid;
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2018-12-12 22:08:43 +00:00
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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/* Look for our parent */
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if ((intr_parent = ofw_bus_find_iparent(node)) == 0) {
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2019-10-20 10:48:27 +00:00
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device_printf(dev,
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"Cannot find our parent interrupt controller\n");
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2018-12-12 22:08:43 +00:00
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return (ENXIO);
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}
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if ((sc->parent = OF_device_from_xref(intr_parent)) == NULL) {
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2019-10-20 10:48:27 +00:00
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device_printf(dev,
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"cannot find parent interrupt controller device\n");
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2018-12-12 22:08:43 +00:00
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return (ENXIO);
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}
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2021-02-17 15:28:46 +00:00
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rid = 0;
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->res == NULL) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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2021-02-19 14:31:45 +00:00
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sc->spi_ranges_cnt = OF_getencprop_alloc_multi(node, "marvell,spi-ranges",
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sizeof(*sc->spi_ranges), (void **)&sc->spi_ranges);
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2018-12-12 22:08:43 +00:00
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2021-02-17 15:28:46 +00:00
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sc->msi_bitmap_size = 0;
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for (i = 0; i < sc->spi_ranges_cnt; i += 2)
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sc->msi_bitmap_size += sc->spi_ranges[i + 1];
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/*
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* Create a bitmap of all MSIs that we have.
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* Each has a correspoding SPI in the GIC.
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* It will be used to dynamically allocate IRQs when requested.
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*/
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sc->msi_bitmap = BITSET_ALLOC(sc->msi_bitmap_size, M_GICP, M_WAITOK);
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BIT_FILL(sc->msi_bitmap_size, sc->msi_bitmap); /* 1 - available, 0 - used. */
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2018-12-12 22:08:43 +00:00
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xref = OF_xref_from_node(node);
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if (intr_pic_register(dev, xref) == NULL) {
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device_printf(dev, "Cannot register GICP\n");
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return (ENXIO);
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}
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2019-10-20 10:48:27 +00:00
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/* Allocate GIC compatible mapping entry (3 cells) */
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sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data(
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INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) +
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+ 3 * sizeof(phandle_t), M_WAITOK | M_ZERO);
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2018-12-12 22:08:43 +00:00
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OF_device_register_xref(xref, dev);
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return (0);
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}
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static int
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mv_ap806_gicp_detach(device_t dev)
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{
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return (EBUSY);
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}
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2021-02-17 15:28:46 +00:00
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static uint32_t
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mv_ap806_gicp_msi_to_spi(struct mv_ap806_gicp_softc *sc, int irq)
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{
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int i;
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for (i = 0; i < sc->spi_ranges_cnt; i += 2) {
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if (irq < sc->spi_ranges[i + 1]) {
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irq += sc->spi_ranges[i];
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break;
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}
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irq -= sc->spi_ranges[i + 1];
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}
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return (irq - GIC_FIRST_SPI);
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}
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static uint32_t
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mv_ap806_gicp_irq_to_msi(struct mv_ap806_gicp_softc *sc, int irq)
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{
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int i;
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for (i = 0; i < sc->spi_ranges_cnt; i += 2) {
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if (irq >= sc->spi_ranges[i] &&
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irq - sc->spi_ranges[i] < sc->spi_ranges[i + 1]) {
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irq -= sc->spi_ranges[i];
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break;
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}
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}
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return (irq);
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}
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2019-10-20 10:48:27 +00:00
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static struct intr_map_data *
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mv_ap806_gicp_convert_map_data(struct mv_ap806_gicp_softc *sc,
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struct intr_map_data *data)
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{
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struct intr_map_data_fdt *daf;
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2021-02-17 15:28:46 +00:00
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uint32_t irq_num;
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2019-10-20 10:48:27 +00:00
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daf = (struct intr_map_data_fdt *)data;
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if (daf->ncells != 2)
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return (NULL);
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irq_num = daf->cells[0];
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if (irq_num >= MV_AP806_GICP_MAX_NIRQS)
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return (NULL);
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/* Construct GIC compatible mapping. */
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sc->parent_map_data->ncells = 3;
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sc->parent_map_data->cells[0] = 0; /* SPI */
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2021-02-17 15:28:46 +00:00
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sc->parent_map_data->cells[1] = mv_ap806_gicp_msi_to_spi(sc, irq_num);
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sc->parent_map_data->cells[2] = IRQ_TYPE_LEVEL_HIGH;
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2019-10-20 10:48:27 +00:00
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return ((struct intr_map_data *)sc->parent_map_data);
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}
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2018-12-12 22:08:43 +00:00
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static int
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mv_ap806_gicp_activate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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2019-10-20 10:48:27 +00:00
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data = mv_ap806_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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2018-12-12 22:08:43 +00:00
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return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static void
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mv_ap806_gicp_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_ENABLE_INTR(sc->parent, isrc);
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}
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static void
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mv_ap806_gicp_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_DISABLE_INTR(sc->parent, isrc);
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}
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static int
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mv_ap806_gicp_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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2021-02-17 15:28:46 +00:00
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panic("%s: MSI interface has to be used to map an interrupt.\n",
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__func__);
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2018-12-12 22:08:43 +00:00
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}
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static int
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mv_ap806_gicp_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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2019-10-20 10:48:27 +00:00
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data = mv_ap806_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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2018-12-12 22:08:43 +00:00
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return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static int
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mv_ap806_gicp_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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2019-10-20 10:48:27 +00:00
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data = mv_ap806_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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2018-12-12 22:08:43 +00:00
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return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
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}
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static int
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mv_ap806_gicp_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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2019-10-20 10:48:27 +00:00
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data = mv_ap806_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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2018-12-12 22:08:43 +00:00
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return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
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}
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static void
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mv_ap806_gicp_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_PRE_ITHREAD(sc->parent, isrc);
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}
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static void
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mv_ap806_gicp_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_POST_ITHREAD(sc->parent, isrc);
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}
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static void
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mv_ap806_gicp_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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|
struct mv_ap806_gicp_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
PIC_POST_FILTER(sc->parent, isrc);
|
|
|
|
}
|
|
|
|
|
2021-02-17 15:28:46 +00:00
|
|
|
static int
|
|
|
|
mv_ap806_gicp_alloc_msi(device_t dev, device_t child, int count, int maxcount,
|
|
|
|
device_t *pic, struct intr_irqsrc **srcs)
|
|
|
|
{
|
|
|
|
struct mv_ap806_gicp_softc *sc;
|
|
|
|
int i, ret, vector;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
/*
|
|
|
|
* Find first available vector represented by first set bit
|
|
|
|
* in the bitmap. BIT_FFS starts the count from 1, 0 means
|
|
|
|
* that nothing was found.
|
|
|
|
*/
|
|
|
|
vector = BIT_FFS(sc->msi_bitmap_size, sc->msi_bitmap);
|
|
|
|
if (vector == 0) {
|
|
|
|
ret = ENOMEM;
|
|
|
|
i--;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
vector--;
|
|
|
|
BIT_CLR(sc->msi_bitmap_size, vector, sc->msi_bitmap);
|
|
|
|
|
|
|
|
/* Create GIC compatible SPI interrupt description. */
|
|
|
|
sc->parent_map_data->ncells = 3;
|
|
|
|
sc->parent_map_data->cells[0] = 0; /* SPI */
|
|
|
|
sc->parent_map_data->cells[1] = mv_ap806_gicp_msi_to_spi(sc, vector);
|
|
|
|
sc->parent_map_data->cells[2] = IRQ_TYPE_LEVEL_HIGH;
|
|
|
|
|
|
|
|
ret = PIC_MAP_INTR(sc->parent,
|
|
|
|
(struct intr_map_data *)sc->parent_map_data,
|
|
|
|
&srcs[i]);
|
|
|
|
if (ret != 0)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
srcs[i]->isrc_dev = dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
fail:
|
|
|
|
mv_ap806_gicp_release_msi(dev, child, i + 1, srcs);
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mv_ap806_gicp_release_msi(device_t dev, device_t child, int count,
|
|
|
|
struct intr_irqsrc **srcs)
|
|
|
|
{
|
|
|
|
struct mv_ap806_gicp_softc *sc;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
BIT_SET(sc->msi_bitmap_size,
|
|
|
|
mv_ap806_gicp_irq_to_msi(sc, srcs[i]->isrc_irq),
|
|
|
|
sc->msi_bitmap);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mv_ap806_gicp_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
|
|
|
|
uint64_t *addr, uint32_t *data)
|
|
|
|
{
|
|
|
|
struct mv_ap806_gicp_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
*addr = rman_get_start(sc->res);
|
|
|
|
*data = mv_ap806_gicp_irq_to_msi(sc, isrc->isrc_irq);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2018-12-12 22:08:43 +00:00
|
|
|
static device_method_t mv_ap806_gicp_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, mv_ap806_gicp_probe),
|
|
|
|
DEVMETHOD(device_attach, mv_ap806_gicp_attach),
|
|
|
|
DEVMETHOD(device_detach, mv_ap806_gicp_detach),
|
|
|
|
|
|
|
|
/* Interrupt controller interface */
|
|
|
|
DEVMETHOD(pic_activate_intr, mv_ap806_gicp_activate_intr),
|
|
|
|
DEVMETHOD(pic_disable_intr, mv_ap806_gicp_disable_intr),
|
|
|
|
DEVMETHOD(pic_enable_intr, mv_ap806_gicp_enable_intr),
|
|
|
|
DEVMETHOD(pic_map_intr, mv_ap806_gicp_map_intr),
|
|
|
|
DEVMETHOD(pic_deactivate_intr, mv_ap806_gicp_deactivate_intr),
|
|
|
|
DEVMETHOD(pic_setup_intr, mv_ap806_gicp_setup_intr),
|
|
|
|
DEVMETHOD(pic_teardown_intr, mv_ap806_gicp_teardown_intr),
|
|
|
|
DEVMETHOD(pic_post_filter, mv_ap806_gicp_post_filter),
|
|
|
|
DEVMETHOD(pic_post_ithread, mv_ap806_gicp_post_ithread),
|
|
|
|
DEVMETHOD(pic_pre_ithread, mv_ap806_gicp_pre_ithread),
|
|
|
|
|
2021-02-17 15:28:46 +00:00
|
|
|
/* MSI interface */
|
|
|
|
DEVMETHOD(msi_alloc_msi, mv_ap806_gicp_alloc_msi),
|
|
|
|
DEVMETHOD(msi_release_msi, mv_ap806_gicp_release_msi),
|
|
|
|
DEVMETHOD(msi_map_msi, mv_ap806_gicp_map_msi),
|
|
|
|
|
2018-12-12 22:08:43 +00:00
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t mv_ap806_gicp_driver = {
|
|
|
|
"mv_ap806_gicp",
|
|
|
|
mv_ap806_gicp_methods,
|
|
|
|
sizeof(struct mv_ap806_gicp_softc),
|
|
|
|
};
|
|
|
|
|
2022-05-09 21:26:45 +00:00
|
|
|
EARLY_DRIVER_MODULE(mv_ap806_gicp, simplebus, mv_ap806_gicp_driver, 0, 0,
|
|
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|