2019-10-20 10:48:27 +00:00
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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2021-02-17 15:28:46 +00:00
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#include <sys/bitset.h>
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2019-10-20 10:48:27 +00:00
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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2021-02-17 15:28:46 +00:00
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#include "msi_if.h"
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2019-10-20 10:48:27 +00:00
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#include "pic_if.h"
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#define MV_AP806_SEI_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define MV_AP806_SEI_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define MV_AP806_SEI_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \
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device_get_nameunit(_sc->dev), "mv_ap806_sei", MTX_DEF)
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#define MV_AP806_SEI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
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#define MV_AP806_SEI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
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#define MV_AP806_SEI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
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#define GICP_SECR0 0x00
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#define GICP_SECR1 0x04
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#define GICP_SECR(i) (0x00 + (((i)/32) * 0x4))
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#define GICP_SECR_BIT(i) ((i) % 32)
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#define GICP_SEMR0 0x20
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#define GICP_SEMR1 0x24
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#define GICP_SEMR(i) (0x20 + (((i)/32) * 0x4))
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#define GICP_SEMR_BIT(i) ((i) % 32)
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2021-02-17 15:28:46 +00:00
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#define MV_AP806_SEI_AP_FIRST 0
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#define MV_AP806_SEI_AP_SIZE 21
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#define MV_AP806_SEI_CP_FIRST 21
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#define MV_AP806_SEI_CP_SIZE 43
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#define MV_AP806_SEI_MAX_NIRQS (MV_AP806_SEI_AP_SIZE + MV_AP806_SEI_CP_SIZE)
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#define MV_AP806_SEI_SETSPI_OFFSET 0x30
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BITSET_DEFINE(sei_msi_bitmap, MV_AP806_SEI_CP_SIZE);
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2019-10-20 10:48:27 +00:00
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struct mv_ap806_sei_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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};
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struct mv_ap806_sei_softc {
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device_t dev;
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struct resource *mem_res;
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struct resource *irq_res;
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void *irq_ih;
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struct mtx mtx;
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struct mv_ap806_sei_irqsrc *isrcs;
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2021-02-17 15:28:46 +00:00
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struct sei_msi_bitmap msi_bitmap;
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2019-10-20 10:48:27 +00:00
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};
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static struct ofw_compat_data compat_data[] = {
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{"marvell,ap806-sei", 1},
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{NULL, 0}
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};
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#define RD4(sc, reg) bus_read_4((sc)->mem_res, (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val))
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2021-02-17 15:28:46 +00:00
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static msi_alloc_msi_t mv_ap806_sei_alloc_msi;
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static msi_release_msi_t mv_ap806_sei_release_msi;
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static msi_map_msi_t mv_ap806_sei_map_msi;
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2019-10-20 10:48:27 +00:00
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static inline void
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mv_ap806_sei_isrc_mask(struct mv_ap806_sei_softc *sc,
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struct mv_ap806_sei_irqsrc *sisrc, uint32_t val)
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{
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uint32_t tmp;
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int bit;
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bit = GICP_SEMR_BIT(sisrc->irq);
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MV_AP806_SEI_LOCK(sc);
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tmp = RD4(sc, GICP_SEMR(sisrc->irq));
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if (val != 0)
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tmp |= 1 << bit;
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else
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tmp &= ~(1 << bit);
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WR4(sc, GICP_SEMR(sisrc->irq), tmp);
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MV_AP806_SEI_UNLOCK(sc);
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}
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static inline void
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mv_ap806_sei_isrc_eoi(struct mv_ap806_sei_softc *sc,
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struct mv_ap806_sei_irqsrc *sisrc)
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{
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WR4(sc, GICP_SECR(sisrc->irq), GICP_SECR_BIT(sisrc->irq));
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}
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static void
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mv_ap806_sei_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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mv_ap806_sei_isrc_mask(sc, sisrc, 0);
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}
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static void
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mv_ap806_sei_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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mv_ap806_sei_isrc_mask(sc, sisrc, 1);
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}
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static int
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mv_ap806_sei_map(device_t dev, struct intr_map_data *data, u_int *irqp)
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{
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struct intr_map_data_fdt *daf;
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u_int irq;
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if (data->type != INTR_MAP_DATA_FDT)
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return (ENOTSUP);
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daf = (struct intr_map_data_fdt *)data;
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2021-02-17 15:28:46 +00:00
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if (daf->ncells != 1)
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2019-10-20 10:48:27 +00:00
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return (EINVAL);
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2021-02-17 15:28:46 +00:00
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if (daf->cells[0] < MV_AP806_SEI_AP_FIRST ||
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daf->cells[0] >= MV_AP806_SEI_AP_FIRST + MV_AP806_SEI_AP_SIZE)
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return (EINVAL);
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2019-10-20 10:48:27 +00:00
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irq = daf->cells[0];
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if (irqp != NULL)
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*irqp = irq;
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return(0);
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}
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static int
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mv_ap806_sei_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct mv_ap806_sei_softc *sc;
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u_int irq;
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int rv;
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sc = device_get_softc(dev);
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rv = mv_ap806_sei_map(dev, data, &irq);
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if (rv == 0)
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*isrcp = &sc->isrcs[irq].isrc;
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return (rv);
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}
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static int
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mv_ap806_sei_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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u_int irq;
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int rv;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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if (data == NULL)
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return (ENOTSUP);
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rv = mv_ap806_sei_map(dev, data, &irq);
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if (rv != 0)
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return (rv);
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if (irq != sisrc->irq)
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return (EINVAL);
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mv_ap806_sei_isrc_mask(sc, sisrc, 0);
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return (0);
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}
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static int
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mv_ap806_sei_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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mv_ap806_sei_isrc_mask(sc, sisrc, 1);
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return (0);
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}
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static void
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mv_ap806_sei_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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mv_ap806_sei_isrc_mask(sc, sisrc, 1);
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mv_ap806_sei_isrc_eoi(sc, sisrc);
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}
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static void
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mv_ap806_sei_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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mv_ap806_sei_isrc_mask(sc, sisrc, 1);
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}
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static void
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mv_ap806_sei_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sisrc;
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sc = device_get_softc(dev);
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sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
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mv_ap806_sei_isrc_mask(sc, sisrc, 1);
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mv_ap806_sei_isrc_eoi(sc, sisrc);
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}
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/* ----------------------------------------------------------------------------
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*
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* B u s i n t e r f a c e
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*/
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static int
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mv_ap806_sei_intr(void *arg)
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{
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struct mv_ap806_sei_softc *sc;
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struct mv_ap806_sei_irqsrc *sirq;
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struct trapframe *tf;
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uint64_t cause;
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u_int irq;
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sc = (struct mv_ap806_sei_softc *)arg;
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tf = curthread->td_intr_frame;
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while (1) {
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cause = RD4(sc, GICP_SECR1);
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cause <<= 32;
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cause |= RD4(sc, GICP_SECR0);
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irq = ffsll(cause);
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if (irq == 0) break;
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irq--;
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sirq = &sc->isrcs[irq];
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if (intr_isrc_dispatch(&sirq->isrc, tf) != 0) {
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mv_ap806_sei_isrc_mask(sc, sirq, 0);
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mv_ap806_sei_isrc_eoi(sc, sirq);
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device_printf(sc->dev,
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"Stray irq %u disabled\n", irq);
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}
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}
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return (FILTER_HANDLED);
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}
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static int
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mv_ap806_sei_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell SEI");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mv_ap806_sei_attach(device_t dev)
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{
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struct mv_ap806_sei_softc *sc;
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phandle_t xref, node;
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uint32_t irq;
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const char *name;
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int rv, rid;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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MV_AP806_SEI_LOCK_INIT(sc);
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/* Allocate resources. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot allocate memory resources\n");
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rv = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
|
|
|
|
if (sc->irq_res == NULL) {
|
|
|
|
device_printf(dev, "Cannot allocate IRQ resources\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Mask all interrupts) */
|
|
|
|
WR4(sc, GICP_SEMR0, 0xFFFFFFFF);
|
|
|
|
WR4(sc, GICP_SEMR1, 0xFFFFFFFF);
|
|
|
|
|
|
|
|
/* Create all interrupt sources */
|
|
|
|
sc->isrcs = malloc(sizeof(*sc->isrcs) * MV_AP806_SEI_MAX_NIRQS,
|
|
|
|
M_DEVBUF, M_WAITOK | M_ZERO);
|
|
|
|
name = device_get_nameunit(sc->dev);
|
|
|
|
for (irq = 0; irq < MV_AP806_SEI_MAX_NIRQS; irq++) {
|
|
|
|
sc->isrcs[irq].irq = irq;
|
|
|
|
rv = intr_isrc_register(&sc->isrcs[irq].isrc,
|
|
|
|
sc->dev, 0, "%s,%u", name, irq);
|
|
|
|
if (rv != 0)
|
|
|
|
goto fail; /* XXX deregister ISRCs */
|
|
|
|
}
|
2021-08-16 22:51:38 +00:00
|
|
|
xref = OF_xref_from_node(node);
|
2019-10-20 10:48:27 +00:00
|
|
|
if (intr_pic_register(dev, xref) == NULL) {
|
|
|
|
device_printf(dev, "Cannot register SEI\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
if (bus_setup_intr(dev, sc->irq_res,INTR_TYPE_MISC | INTR_MPSAFE,
|
|
|
|
mv_ap806_sei_intr, NULL, sc, &sc->irq_ih)) {
|
|
|
|
device_printf(dev,
|
|
|
|
"Unable to register interrupt handler\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
2020-09-01 21:17:24 +00:00
|
|
|
|
2021-02-17 15:28:46 +00:00
|
|
|
/*
|
|
|
|
* Bitmap of all IRQs.
|
|
|
|
* 1 - available, 0 - used.
|
|
|
|
*/
|
|
|
|
BIT_FILL(MV_AP806_SEI_CP_SIZE, &sc->msi_bitmap);
|
|
|
|
|
2019-10-20 10:48:27 +00:00
|
|
|
OF_device_register_xref(xref, dev);
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
fail:
|
|
|
|
if (sc->irq_ih != NULL)
|
|
|
|
bus_teardown_intr(dev, sc->irq_res, sc->irq_ih);
|
|
|
|
if (sc->irq_res != NULL)
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
|
|
|
|
if (sc->mem_res != NULL)
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
|
|
|
|
MV_AP806_SEI_LOCK_DESTROY(sc);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mv_ap806_sei_detach(device_t dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
return (EBUSY);
|
|
|
|
}
|
|
|
|
|
2021-02-17 15:28:46 +00:00
|
|
|
static int
|
|
|
|
mv_ap806_sei_alloc_msi(device_t dev, device_t child, int count, int maxcount,
|
|
|
|
device_t *pic, struct intr_irqsrc **srcs)
|
|
|
|
{
|
|
|
|
struct mv_ap806_sei_softc *sc;
|
|
|
|
int i, ret = 0, vector;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
/*
|
|
|
|
* Find first available MSI vector represented by first set bit
|
|
|
|
* in the bitmap. BIT_FFS starts the count from 1,
|
|
|
|
* 0 means that nothing was found.
|
|
|
|
*/
|
|
|
|
vector = BIT_FFS_AT(MV_AP806_SEI_CP_SIZE, &sc->msi_bitmap, 0);
|
|
|
|
if (vector == 0) {
|
|
|
|
ret = ENOMEM;
|
|
|
|
i--;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
vector--;
|
|
|
|
BIT_CLR(MV_AP806_SEI_CP_SIZE, vector, &sc->msi_bitmap);
|
|
|
|
vector += MV_AP806_SEI_CP_FIRST;
|
|
|
|
|
|
|
|
srcs[i] = &sc->isrcs[vector].isrc;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (ret);
|
|
|
|
fail:
|
|
|
|
mv_ap806_sei_release_msi(dev, child, i + 1, srcs);
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mv_ap806_sei_release_msi(device_t dev, device_t child, int count, struct intr_irqsrc **srcs)
|
|
|
|
{
|
|
|
|
struct mv_ap806_sei_softc *sc;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
BIT_SET(MV_AP806_SEI_CP_SIZE,
|
|
|
|
srcs[i]->isrc_irq - MV_AP806_SEI_CP_FIRST,
|
|
|
|
&sc->msi_bitmap);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mv_ap806_sei_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
|
|
|
|
uint64_t *addr, uint32_t *data)
|
|
|
|
{
|
|
|
|
struct mv_ap806_sei_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
*addr = rman_get_start(sc->mem_res) + MV_AP806_SEI_SETSPI_OFFSET;
|
|
|
|
*data = isrc->isrc_irq;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2019-10-20 10:48:27 +00:00
|
|
|
static device_method_t mv_ap806_sei_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, mv_ap806_sei_probe),
|
|
|
|
DEVMETHOD(device_attach, mv_ap806_sei_attach),
|
|
|
|
DEVMETHOD(device_detach, mv_ap806_sei_detach),
|
|
|
|
|
|
|
|
/* Interrupt controller interface */
|
|
|
|
DEVMETHOD(pic_disable_intr, mv_ap806_sei_disable_intr),
|
|
|
|
DEVMETHOD(pic_enable_intr, mv_ap806_sei_enable_intr),
|
|
|
|
DEVMETHOD(pic_map_intr, mv_ap806_sei_map_intr),
|
|
|
|
DEVMETHOD(pic_setup_intr, mv_ap806_sei_setup_intr),
|
|
|
|
DEVMETHOD(pic_teardown_intr, mv_ap806_sei_teardown_intr),
|
|
|
|
DEVMETHOD(pic_post_filter, mv_ap806_sei_post_filter),
|
|
|
|
DEVMETHOD(pic_post_ithread, mv_ap806_sei_post_ithread),
|
|
|
|
DEVMETHOD(pic_pre_ithread, mv_ap806_sei_pre_ithread),
|
|
|
|
|
2021-02-17 15:28:46 +00:00
|
|
|
/* MSI interface */
|
|
|
|
DEVMETHOD(msi_alloc_msi, mv_ap806_sei_alloc_msi),
|
|
|
|
DEVMETHOD(msi_release_msi, mv_ap806_sei_release_msi),
|
|
|
|
DEVMETHOD(msi_map_msi, mv_ap806_sei_map_msi),
|
|
|
|
|
2019-10-20 10:48:27 +00:00
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t mv_ap806_sei_driver = {
|
|
|
|
"mv_ap806_sei",
|
|
|
|
mv_ap806_sei_methods,
|
|
|
|
sizeof(struct mv_ap806_sei_softc),
|
|
|
|
};
|
|
|
|
|
2022-05-09 21:26:45 +00:00
|
|
|
EARLY_DRIVER_MODULE(mv_ap806_sei, simplebus, mv_ap806_sei_driver, 0, 0,
|
|
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|