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freebsd-dev/sys/dev/ath/if_ath_rx_edma.c

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Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
/*-
* Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Driver for the Atheros Wireless LAN controller.
*
* This software is derived from work of Atsushi Onoe; his contribution
* is greatly appreciated.
*/
#include "opt_inet.h"
#include "opt_ath.h"
/*
* This is needed for register operations which are performed
* by the driver - eg, calls to ath_hal_gettsf32().
*
* It's also required for any AH_DEBUG checks in here, eg the
* module dependencies.
*/
#include "opt_ah.h"
#include "opt_wlan.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysctl.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <sys/errno.h>
#include <sys/callout.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/kthread.h>
#include <sys/taskqueue.h>
#include <sys/priv.h>
#include <sys/module.h>
#include <sys/ktr.h>
#include <sys/smp.h> /* for mp_ncpus */
#include <machine/bus.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_llc.h>
#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_regdomain.h>
#ifdef IEEE80211_SUPPORT_SUPERG
#include <net80211/ieee80211_superg.h>
#endif
#ifdef IEEE80211_SUPPORT_TDMA
#include <net80211/ieee80211_tdma.h>
#endif
#include <net/bpf.h>
#ifdef INET
#include <netinet/in.h>
#include <netinet/if_ether.h>
#endif
#include <dev/ath/if_athvar.h>
#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
#include <dev/ath/ath_hal/ah_diagcodes.h>
#include <dev/ath/if_ath_debug.h>
#include <dev/ath/if_ath_misc.h>
#include <dev/ath/if_ath_tsf.h>
#include <dev/ath/if_ath_tx.h>
#include <dev/ath/if_ath_sysctl.h>
#include <dev/ath/if_ath_led.h>
#include <dev/ath/if_ath_keycache.h>
#include <dev/ath/if_ath_rx.h>
#include <dev/ath/if_ath_beacon.h>
#include <dev/ath/if_athdfs.h>
#ifdef ATH_TX99_DIAG
#include <dev/ath/ath_tx99/ath_tx99.h>
#endif
#include <dev/ath/if_ath_rx_edma.h>
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/*
* some general macros
*/
#define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
#define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
MALLOC_DECLARE(M_ATHDEV);
/*
* XXX TODO:
*
* + Add an RX lock, just to ensure we don't have things clash;
* + Make sure the FIFO is correctly flushed and reinitialised
* through a reset;
* + Handle the "kickpcu" state where the FIFO overflows.
* + Implement a "flush" routine, which doesn't push any
* new frames into the FIFO.
* + Verify multi-descriptor frames work!
* + There's a "memory use after free" which needs to be tracked down
* and fixed ASAP. I've seen this in the legacy path too, so it
* may be a generic RX path issue.
*/
/*
* XXX shuffle the function orders so these pre-declarations aren't
* required!
*/
static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
int nbufs);
static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
static int ath_edma_recv_proc_queue(struct ath_softc *sc,
HAL_RX_QUEUE qtype, int dosched);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
static void
ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
{
struct ath_hal *ah = sc->sc_ah;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK(sc);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
ath_hal_stoppcurecv(ah);
ath_hal_setrxfilter(ah, 0);
ath_hal_stopdmarecv(ah);
DELAY(3000);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Flush RX pending for each queue */
/* XXX should generic-ify this */
if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
}
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
}
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_UNLOCK(sc);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
}
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
/*
* Re-initialise the FIFO given the current buffer contents.
* Specifically, walk from head -> tail, pushing the FIFO contents
* back into the FIFO.
*/
static void
ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
{
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
struct ath_buf *bf;
int i, j;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
i = re->m_fifo_head;
for (j = 0; j < re->m_fifo_depth; j++) {
bf = re->m_fifo[i];
Add some debugging and comments about what's going on when reinitialising the FIFO. I still see some corner cases where no RX occurs when it should be occuring. It's quite possible that there's a subtle race condition somewhere; or maybe I'm not programming the RX queues right. There's also no locking here yet, so any reset/configuration path state change (ie, enabling/disabling receive from the ioctl, net80211 taskqueue, etc) could quite possibly confuse things.
2012-07-10 07:45:47 +00:00
DPRINTF(sc, ATH_DEBUG_EDMA_RX,
Cast a bus address to a uintmax_t for a debug printf to fix the build on arm.
2012-07-11 15:04:20 +00:00
"%s: Q%d: pos=%i, addr=0x%jx\n",
Add some debugging and comments about what's going on when reinitialising the FIFO. I still see some corner cases where no RX occurs when it should be occuring. It's quite possible that there's a subtle race condition somewhere; or maybe I'm not programming the RX queues right. There's also no locking here yet, so any reset/configuration path state change (ie, enabling/disabling receive from the ioctl, net80211 taskqueue, etc) could quite possibly confuse things.
2012-07-10 07:45:47 +00:00
__func__,
qtype,
i,
Cast a bus address to a uintmax_t for a debug printf to fix the build on arm.
2012-07-11 15:04:20 +00:00
(uintmax_t)bf->bf_daddr);
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
INCR(i, re->m_fifolen);
}
/* Ensure this worked out right */
if (i != re->m_fifo_tail) {
device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
__func__,
i,
re->m_fifo_tail);
}
}
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/*
* Start receive.
*
* XXX TODO: this needs to reallocate the FIFO entries when a reset
* occurs, in case the FIFO is filled up and no new descriptors get
* thrown into the FIFO.
*/
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
static int
ath_edma_startrecv(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Enable RX FIFO */
ath_hal_rxena(ah);
/*
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
* Entries should only be written out if the
* FIFO is empty.
Add some debugging and comments about what's going on when reinitialising the FIFO. I still see some corner cases where no RX occurs when it should be occuring. It's quite possible that there's a subtle race condition somewhere; or maybe I'm not programming the RX queues right. There's also no locking here yet, so any reset/configuration path state change (ie, enabling/disabling receive from the ioctl, net80211 taskqueue, etc) could quite possibly confuse things.
2012-07-10 07:45:47 +00:00
*
* XXX This isn't correct. I should be looking
* at the value of AR_RXDP_SIZE (0x0070) to determine
* how many entries are in here.
*
* A warm reset will clear the registers but not the FIFO.
*
* And I believe this is actually the address of the last
* handled buffer rather than the current FIFO pointer.
* So if no frames have been (yet) seen, we'll reinit the
* FIFO.
*
* I'll chase that up at some point.
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
*/
Add some debugging and comments about what's going on when reinitialising the FIFO. I still see some corner cases where no RX occurs when it should be occuring. It's quite possible that there's a subtle race condition somewhere; or maybe I'm not programming the RX queues right. There's also no locking here yet, so any reset/configuration path state change (ie, enabling/disabling receive from the ioctl, net80211 taskqueue, etc) could quite possibly confuse things.
2012-07-10 07:45:47 +00:00
if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
DPRINTF(sc, ATH_DEBUG_EDMA_RX,
"%s: Re-initing HP FIFO\n", __func__);
ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
}
if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
DPRINTF(sc, ATH_DEBUG_EDMA_RX,
"%s: Re-initing LP FIFO\n", __func__);
ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
}
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Add up to m_fifolen entries in each queue */
/*
* These must occur after the above write so the FIFO buffers
* are pushed/tracked in the same order as the hardware will
* process them.
*/
ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
ath_mode_init(sc);
ath_hal_startpcurecv(ah);
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_UNLOCK(sc);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
return (0);
}
static void
ath_edma_recv_flush(struct ath_softc *sc)
{
device_printf(sc->sc_dev, "%s: called\n", __func__);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
ATH_PCU_LOCK(sc);
sc->sc_rxproc_cnt++;
ATH_PCU_UNLOCK(sc);
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
ATH_PCU_LOCK(sc);
sc->sc_rxproc_cnt--;
ATH_PCU_UNLOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
}
/*
* Process frames from the current queue.
*
* TODO:
*
* + Add a "dosched" flag, so we don't reschedule any FIFO frames
* to the hardware or re-kick the PCU after 'kickpcu' is set.
*
* + Perhaps split "check FIFO contents" and "handle frames", so
* we can run the "check FIFO contents" in ath_intr(), but
* "handle frames" in the RX tasklet.
*/
static int
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
int dosched)
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
{
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
struct ath_rx_status *rs;
struct ath_desc *ds;
struct ath_buf *bf;
struct mbuf *m;
struct ath_hal *ah = sc->sc_ah;
uint64_t tsf;
int16_t nf;
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
int ngood = 0, npkts = 0;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ath_bufhead rxlist;
struct ath_buf *next;
TAILQ_INIT(&rxlist);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
tsf = ath_hal_gettsf64(ah);
nf = ath_hal_getchannoise(ah, sc->sc_curchan);
sc->sc_stats.ast_rx_noise = nf;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
do {
bf = re->m_fifo[re->m_fifo_head];
/* This shouldn't occur! */
if (bf == NULL) {
device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
__func__,
qtype);
break;
}
m = bf->bf_m;
ds = bf->bf_desc;
/*
* Sync descriptor memory - this also syncs the buffer for us.
*
* EDMA descriptors are in cached memory.
*/
bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
BUS_DMASYNC_POSTREAD);
rs = &bf->bf_status.ds_rxstat;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
NULL, rs);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
#ifdef ATH_DEBUG
if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
#endif
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
if (bf->bf_rxstatus == HAL_EINPROGRESS)
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
break;
/*
* Completed descriptor.
*
* In the future we'll call ath_rx_pkt(), but it first
* has to be taught about EDMA RX queues (so it can
* access sc_rxpending correctly.)
*/
DPRINTF(sc, ATH_DEBUG_EDMA_RX,
"%s: Q%d: completed!\n", __func__, qtype);
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
npkts++;
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/*
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
* Remove the FIFO entry and place it on the completion
* queue.
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
*/
re->m_fifo[re->m_fifo_head] = NULL;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
TAILQ_INSERT_TAIL(&rxlist, bf, bf_list);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
/* Bump the descriptor FIFO stats */
INCR(re->m_fifo_head, re->m_fifolen);
re->m_fifo_depth--;
/* XXX check it doesn't fall below 0 */
} while (re->m_fifo_depth > 0);
/* Append some more fresh frames to the FIFO */
if (dosched)
ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
ATH_RX_UNLOCK(sc);
/* Handle the completed descriptors */
TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/*
* Skip the RX descriptor status - start at the data offset
*/
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
m_adj(bf->bf_m, sc->sc_rx_statuslen);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Handle the frame */
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
/*
* Note: this may or may not free bf->bf_m and sync/unmap
* the frame.
*/
Make sure that 'rs' is pointing to the correct RX status.
2012-07-14 05:53:03 +00:00
rs = &bf->bf_status.ds_rxstat;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf))
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ngood++;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
}
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
/* Free in one set, inside the lock */
ATH_RX_LOCK(sc);
TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Free the buffer/mbuf */
ath_edma_rxbuf_free(sc, bf);
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
}
ATH_RX_UNLOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
/* rx signal state monitoring */
ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
if (ngood)
sc->sc_lastrx = tsf;
CTR2(ATH_KTR_INTR, "ath edma rx proc: npkts=%d, ngood=%d",
npkts, ngood);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Handle resched and kickpcu appropriately */
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ATH_PCU_LOCK(sc);
if (dosched && sc->sc_kickpcu) {
CTR0(ATH_KTR_ERR, "ath_edma_recv_proc_queue(): kickpcu");
device_printf(sc->sc_dev, "%s: handled %d descriptors\n",
__func__, ngood);
/*
* XXX TODO: what should occur here? Just re-poke and
* re-enable the RX FIFO?
*/
sc->sc_kickpcu = 0;
}
ATH_PCU_UNLOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
return (ngood);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
}
static void
ath_edma_recv_tasklet(void *arg, int npending)
{
struct ath_softc *sc = (struct ath_softc *) arg;
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
struct ifnet *ifp = sc->sc_ifp;
Fix build breakage when one isn't building with IEEE80211_SUPPORT_SUPERG. Noticed by: mav
2012-07-14 12:15:20 +00:00
#ifdef IEEE80211_SUPPORT_SUPERG
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
struct ieee80211com *ic = ifp->if_l2com;
Fix build breakage when one isn't building with IEEE80211_SUPPORT_SUPERG. Noticed by: mav
2012-07-14 12:15:20 +00:00
#endif
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
__func__,
npending);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ATH_PCU_LOCK(sc);
if (sc->sc_inreset_cnt > 0) {
device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
__func__);
ATH_PCU_UNLOCK(sc);
return;
}
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
sc->sc_rxproc_cnt++;
Add/fix EDMA RX behaviour. * For now, kickpcu should hopefully just do nothing - the PCU doesn't need 'kicking' for Osprey and later NICs. The PCU will just restart once the next FIFO entry is pushed in. * Teach "proc" about "dosched", so it can be used to just flush the FIFO contents without adding new FIFO entries. * .. and now, implement the RX "flush" routine. * Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.) When PCU RX is disabled (ie, writing RX_D to the RX configuration register) then the FIFO will be completely emptied. If the software FIFO is full, then no further descriptors are pushed into the FIFO and things stall. This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
ATH_PCU_UNLOCK(sc);
ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
Merge in some other features from the legacy RX path: * wrap the RX proc calls in the RX refcount; * call the DFS checking, fast frames staging and TX rescheduling if required. TODO: * figure out if I can just make "do TX rescheduling" mean "schedule TX taskqueue" ?
2012-07-14 07:56:47 +00:00
/* XXX inside IF_LOCK ? */
if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
#ifdef IEEE80211_SUPPORT_SUPERG
ieee80211_ff_age_all(ic, 100);
#endif
if (! IFQ_IS_EMPTY(&ifp->if_snd))
ath_tx_kick(sc);
}
if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
ATH_PCU_LOCK(sc);
sc->sc_rxproc_cnt--;
ATH_PCU_UNLOCK(sc);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
}
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/*
* Allocate an RX mbuf for the given ath_buf and initialise
* it for EDMA.
*
* + Allocate a 4KB mbuf;
* + Setup the DMA map for the given buffer;
* + Keep a pointer to the start of the mbuf - that's where the
* descriptor lies;
* + Take a pointer to the start of the RX buffer, set the
* mbuf "start" to be there;
* + Return that.
*/
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
static int
ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
{
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
struct mbuf *m;
int error;
int len;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
// device_printf(sc->sc_dev, "%s: called; bf=%p\n", __func__, bf);
m = m_getm(NULL, sc->sc_edma_bufsize, M_DONTWAIT, MT_DATA);
if (! m)
return (ENOBUFS); /* XXX ?*/
/* XXX warn/enforce alignment */
len = m->m_ext.ext_size;
#if 0
device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
__func__,
m,
len,
mtod(m, char *));
#endif
m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
/*
* Create DMA mapping.
*/
error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
if (error != 0) {
device_printf(sc->sc_dev, "%s: failed; error=%d\n",
__func__,
error);
m_freem(m);
return (error);
}
/*
* Populate ath_buf fields.
*/
bf->bf_desc = mtod(m, struct ath_desc *);
bf->bf_daddr = bf->bf_segs[0].ds_addr;
bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
bf->bf_m = m;
/* Zero the descriptor */
memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
#if 0
/*
* Adjust mbuf header and length/size to compensate for the
* descriptor size.
*/
m_adj(m, sc->sc_rx_statuslen);
#endif
/* Finish! */
return (0);
}
static struct ath_buf *
ath_edma_rxbuf_alloc(struct ath_softc *sc)
{
struct ath_buf *bf;
int error;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Allocate buffer */
bf = TAILQ_FIRST(&sc->sc_rxbuf);
/* XXX shouldn't happen upon startup? */
if (bf == NULL)
return (NULL);
/* Remove it from the free list */
TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
/* Assign RX mbuf to it */
error = ath_edma_rxbuf_init(sc, bf);
if (error != 0) {
device_printf(sc->sc_dev,
"%s: bf=%p, rxbuf alloc failed! error=%d\n",
__func__,
bf,
error);
TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
return (NULL);
}
return (bf);
}
static void
ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
{
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
/* We're doing this multiple times? */
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
if (bf->bf_m) {
m_freem(bf->bf_m);
bf->bf_m = NULL;
}
/* XXX lock? */
TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
}
/*
* Allocate up to 'n' entries and push them onto the hardware FIFO.
*
* Return how many entries were successfully pushed onto the
* FIFO.
*/
static int
ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
{
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
struct ath_buf *bf;
int i;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/*
* Allocate buffers until the FIFO is full or nbufs is reached.
*/
for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
/* Ensure the FIFO is already blank, complain loudly! */
if (re->m_fifo[re->m_fifo_tail] != NULL) {
device_printf(sc->sc_dev,
"%s: Q%d: fifo[%d] != NULL (%p)\n",
__func__,
qtype,
re->m_fifo_tail,
re->m_fifo[re->m_fifo_tail]);
/* Free the slot */
ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
re->m_fifo_depth--;
/* XXX check it's not < 0 */
re->m_fifo[re->m_fifo_tail] = NULL;
}
bf = ath_edma_rxbuf_alloc(sc);
/* XXX should ensure the FIFO is not NULL? */
if (bf == NULL) {
device_printf(sc->sc_dev, "%s: Q%d: alloc failed?\n",
__func__,
qtype);
break;
}
re->m_fifo[re->m_fifo_tail] = bf;
/*
* Flush the descriptor contents before it's handed to the
* hardware.
*/
bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
BUS_DMASYNC_PREREAD);
/* Write to the RX FIFO */
DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: putrxbuf=%p\n",
__func__,
qtype,
bf->bf_desc);
ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
re->m_fifo_depth++;
INCR(re->m_fifo_tail, re->m_fifolen);
}
/*
* Return how many were allocated.
*/
DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
__func__,
qtype,
nbufs,
i);
return (i);
}
static int
ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
{
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
int i;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
for (i = 0; i < re->m_fifolen; i++) {
if (re->m_fifo[i] != NULL) {
#ifdef ATH_DEBUG
Fix build when ATH_DEBUG is not defined.
2012-07-10 18:57:05 +00:00
struct ath_buf *bf = re->m_fifo[i];
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
ath_printrxbuf(sc, bf, 0, HAL_OK);
#endif
ath_edma_rxbuf_free(sc, re->m_fifo[i]);
re->m_fifo[i] = NULL;
re->m_fifo_depth--;
}
}
if (re->m_rxpending != NULL) {
m_freem(re->m_rxpending);
re->m_rxpending = NULL;
}
re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
return (0);
}
/*
* Setup the initial RX FIFO structure.
*/
static int
ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
{
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK_ASSERT(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
__func__,
qtype);
return (-EINVAL);
}
device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
__func__,
qtype,
re->m_fifolen);
/* Allocate ath_buf FIFO array, pre-zero'ed */
re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
M_ATHDEV,
M_NOWAIT | M_ZERO);
if (re->m_fifo == NULL) {
device_printf(sc->sc_dev, "%s: malloc failed\n",
__func__);
return (-ENOMEM);
}
/*
* Set initial "empty" state.
*/
re->m_rxpending = NULL;
re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
return (0);
}
static int
ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
{
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
__func__,
qtype);
free(re->m_fifo, M_ATHDEV);
return (0);
}
static int
ath_edma_dma_rxsetup(struct ath_softc *sc)
{
int error;
Fix EDMA RX to actually work without panicing the machine. I was setting up the RX EDMA buffer to be 4096 bytes rather than the RX data buffer portion. The hardware was likely getting very confused and DMAing descriptor portions into places it shouldn't, leading to memory corruption and occasional panics. Whilst here, don't bother allocating descriptors for the RX EDMA case. We don't use those descriptors. Instead, just allocate ath_buf entries.
2012-07-14 02:07:51 +00:00
/*
* Create RX DMA tag and buffers.
*/
error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
"rx", ath_rxbuf, sc->sc_rx_statuslen);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
if (error != 0)
return error;
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
(void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
(void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_UNLOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
return (0);
}
static int
ath_edma_dma_rxteardown(struct ath_softc *sc)
{
device_printf(sc->sc_dev, "%s: called\n", __func__);
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_LOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
Change the RX EDMA path to first complete the FIFO, then re-populate it with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
2012-07-14 02:52:48 +00:00
ATH_RX_UNLOCK(sc);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Free RX ath_buf */
/* Free RX DMA tag */
if (sc->sc_rxdma.dd_desc_len != 0)
ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
return (0);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
}
void
ath_recv_setup_edma(struct ath_softc *sc)
{
device_printf(sc->sc_dev, "DMA setup: EDMA\n");
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
/* Set buffer size to 4k */
sc->sc_edma_bufsize = 4096;
/* Fetch EDMA field and buffer sizes */
(void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
(void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
(void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
(void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
Fix EDMA RX to actually work without panicing the machine. I was setting up the RX EDMA buffer to be 4096 bytes rather than the RX data buffer portion. The hardware was likely getting very confused and DMAing descriptor portions into places it shouldn't, leading to memory corruption and occasional panics. Whilst here, don't bother allocating descriptors for the RX EDMA case. We don't use those descriptors. Instead, just allocate ath_buf entries.
2012-07-14 02:07:51 +00:00
/* Configure the hardware with the RX buffer size */
(void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
sc->sc_rx_statuslen);
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
device_printf(sc->sc_dev, "RX status length: %d\n",
sc->sc_rx_statuslen);
device_printf(sc->sc_dev, "TX descriptor length: %d\n",
sc->sc_tx_desclen);
device_printf(sc->sc_dev, "TX status length: %d\n",
sc->sc_tx_statuslen);
device_printf(sc->sc_dev, "TX/RX buffer size: %d\n",
sc->sc_edma_bufsize);
device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
sc->sc_tx_nmaps);
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
sc->sc_rx.recv_stop = ath_edma_stoprecv;
sc->sc_rx.recv_start = ath_edma_startrecv;
sc->sc_rx.recv_flush = ath_edma_recv_flush;
sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
Implement EDMA RX for AR93xx and later chips. This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
2012-07-10 00:08:39 +00:00
sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
Begin abstracting out the RX path in preparation for RX EDMA support. The RX EDMA support requires a modified approach to the RX descriptor handling. Specifically: * There's now two RX queues - high and low priority; * The RX queues are implemented as FIFOs; they're now an array of pointers to buffers; * .. and the RX buffer and descriptor are in the same "buffer", rather than being separate. So to that end, this commit abstracts out most of the RX related functions from the bulk of the driver. Notably, the RX DMA/buffer allocation isn't updated, primarily because I haven't yet fleshed out what it should look like. Whilst I'm here, create a set of matching but mostly unimplemented EDMA stubs. Tested: * AR9280, station mode TODO: * Thorough AP and other mode testing for non-EDMA chips; * Figure out how to allocate RX buffers suitable for RX EDMA, including correctly setting the mbuf length to compensate for the RX descriptor and completion status area.
2012-07-03 06:59:12 +00:00
}
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