249 lines
7.3 KiB
C
249 lines
7.3 KiB
C
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/*
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* Copyright (c) 2010-2011 Qlogic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* File: qla_reg.h
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* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
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*/
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#ifndef _QLA_REG_H_
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#define _QLA_REG_H_
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/*
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* Begin Definitions for QLA82xx Registers
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*/
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/*
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* Register offsets for QLA8022
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*/
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/******************************
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* PCIe Registers
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******************************/
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#define Q8_CRB_WINDOW_2M 0x130060
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#define Q8_INT_VECTOR 0x130100
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#define Q8_INT_MASK 0x130104
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#define Q8_INT_TARGET_STATUS_F0 0x130118
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#define Q8_INT_TARGET_MASK_F0 0x130128
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#define Q8_INT_TARGET_STATUS_F1 0x130160
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#define Q8_INT_TARGET_MASK_F1 0x130170
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#define Q8_INT_TARGET_STATUS_F2 0x130164
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#define Q8_INT_TARGET_MASK_F2 0x130174
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#define Q8_INT_TARGET_STATUS_F3 0x130168
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#define Q8_INT_TARGET_MASK_F3 0x130178
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#define Q8_INT_TARGET_STATUS_F4 0x130360
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#define Q8_INT_TARGET_MASK_F4 0x130370
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#define Q8_INT_TARGET_STATUS_F5 0x130364
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#define Q8_INT_TARGET_MASK_F5 0x130374
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#define Q8_INT_TARGET_STATUS_F6 0x130368
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#define Q8_INT_TARGET_MASK_F6 0x130378
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#define Q8_INT_TARGET_STATUS_F7 0x13036C
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#define Q8_INT_TARGET_MASK_F7 0x13037C
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#define Q8_SEM2_LOCK 0x13C010
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#define Q8_SEM2_UNLOCK 0x13C014
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#define Q8_SEM3_LOCK 0x13C018
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#define Q8_SEM3_UNLOCK 0x13C01C
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#define Q8_SEM5_LOCK 0x13C028
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#define Q8_SEM5_UNLOCK 0x13C02C
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#define Q8_SEM7_LOCK 0x13C038
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#define Q8_SEM7_UNLOCK 0x13C03C
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/* Valid bit for a SEM<N>_LOCK registers */
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#define SEM_LOCK_BIT 0x00000001
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#define Q8_ROM_LOCKID 0x1B2100
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/*******************************
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* Firmware Interface Registers
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*******************************/
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#define Q8_FW_VER_MAJOR 0x1B2150
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#define Q8_FW_VER_MINOR 0x1B2154
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#define Q8_FW_VER_SUB 0x1B2158
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#define Q8_FW_VER_BUILD 0x1B2168
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#define Q8_CMDPEG_STATE 0x1B2250
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#define Q8_RCVPEG_STATE 0x1B233C
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/*
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* definitions for Q8_CMDPEG_STATE
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*/
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#define CMDPEG_PHAN_INIT_COMPLETE 0xFF01
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#define Q8_ROM_STATUS 0x1A0004
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/*
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* definitions for Q8_ROM_STATUS
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* bit definitions for Q8_UNM_ROMUSB_GLB_STATUS
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* 31:3 Reserved; Rest as below
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*/
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#define ROM_STATUS_RDY 0x0004
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#define ROM_STATUS_DONE 0x0002
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#define ROM_STATUS_AUTO_ROM_SHDW 0x0001
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#define Q8_ASIC_RESET 0x1A0008
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/*
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* definitions for Q8_ASIC_RESET
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*/
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#define ASIC_RESET_RST_XDMA 0x00800000 /* Reset XDMA */
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#define ASIC_RESET_PEG_ICACHE 0x00000020 /* Reset PEG_ICACHE */
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#define ASIC_RESET_PEG_DCACHE 0x00000010 /* Reset PEG_DCACHE */
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#define ASIC_RESET_PEG_3 0x00000008 /* Reset PEG_3 */
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#define ASIC_RESET_PEG_2 0x00000004 /* Reset PEG_2 */
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#define ASIC_RESET_PEG_1 0x00000002 /* Reset PEG_1 */
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#define ASIC_RESET_PEG_0 0x00000001 /* Reset PEG_0 */
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#define Q8_COLD_BOOT 0x1B21FC
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/*
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* definitions for Q8_COLD_BOOT
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*/
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#define COLD_BOOT_VALUE 0x12345678
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#define Q8_MIU_TEST_AGT_CTRL 0x180090
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#define Q8_MIU_TEST_AGT_ADDR_LO 0x180094
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#define Q8_MIU_TEST_AGT_ADDR_HI 0x180098
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#define Q8_MIU_TEST_AGT_WRDATA_LO 0x1800A0
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#define Q8_MIU_TEST_AGT_WRDATA_HI 0x1800A4
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#define Q8_MIU_TEST_AGT_RDDATA_LO 0x1800A8
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#define Q8_MIU_TEST_AGT_RDDATA_HI 0x1800AC
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#define Q8_MIU_TEST_AGT_WRDATA_ULO 0x1800B0
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#define Q8_MIU_TEST_AGT_WRDATA_UHI 0x1800B4
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#define Q8_MIU_TEST_AGT_RDDATA_ULO 0x1800B8
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#define Q8_MIU_TEST_AGT_RDDATA_UHI 0x1800BC
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#define Q8_PEG_0_RESET 0x160018
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#define Q8_PEG_0_CLR1 0x160008
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#define Q8_PEG_0_CLR2 0x16000C
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#define Q8_PEG_1_CLR1 0x161008
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#define Q8_PEG_1_CLR2 0x16100C
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#define Q8_PEG_2_CLR1 0x162008
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#define Q8_PEG_2_CLR2 0x16200C
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#define Q8_PEG_3_CLR1 0x163008
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#define Q8_PEG_3_CLR2 0x16300C
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#define Q8_PEG_4_CLR1 0x164008
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#define Q8_PEG_4_CLR2 0x16400C
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#define Q8_PEG_D_RESET1 0x1650EC
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#define Q8_PEG_D_RESET2 0x16504C
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#define Q8_PEG_HALT_STATUS1 0x1B20A8
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#define Q8_PEG_HALT_STATUS2 0x1B20AC
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#define Q8_FIRMWARE_HEARTBEAT 0x1B20B0
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#define Q8_PEG_I_RESET 0x16604C
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#define Q8_CRB_MAC_BLOCK_START 0x1B21C0
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/***************************************************
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* Flash ROM Access Registers ( Indirect Registers )
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***************************************************/
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#define Q8_ROM_INSTR_OPCODE 0x03310004
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/*
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* bit definitions for Q8_ROM_INSTR_OPCODE
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* 31:8 Reserved; Rest Below
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*/
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#define ROM_OPCODE_WR_STATUS_REG 0x01
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#define ROM_OPCODE_PROG_PAGE 0x02
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#define ROM_OPCODE_RD_BYTE 0x03
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#define ROM_OPCODE_WR_DISABLE 0x04
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#define ROM_OPCODE_RD_STATUS_REG 0x05
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#define ROM_OPCODE_WR_ENABLE 0x06
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#define ROM_OPCODE_FAST_RD 0x0B
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#define ROM_OPCODE_REL_DEEP_PWR_DWN 0xAB
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#define ROM_OPCODE_BULK_ERASE 0xC7
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#define ROM_OPCODE_DEEP_PWR_DWN 0xC9
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#define ROM_OPCODE_SECTOR_ERASE 0xD8
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#define Q8_ROM_ADDRESS 0x03310008
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/*
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* bit definitions for Q8_ROM_ADDRESS
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* 31:24 Reserved;
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* 23:0 Physical ROM Address in bytes
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*/
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#define Q8_ROM_ADDR_BYTE_COUNT 0x03310010
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/*
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* bit definitions for Q8_ROM_ADDR_BYTE_COUNT
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* 31:2 Reserved;
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* 1:0 max address bytes for ROM Interface
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*/
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#define Q8_ROM_DUMMY_BYTE_COUNT 0x03310014
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/*
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* bit definitions for Q8_ROM_DUMMY_BYTE_COUNT
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* 31:2 Reserved;
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* 1:0 dummy bytes for ROM Instructions
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*/
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#define Q8_ROM_RD_DATA 0x03310018
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#define Q8_NX_CDRP_CMD_RSP 0x1B2218
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#define Q8_NX_CDRP_ARG1 0x1B221C
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#define Q8_NX_CDRP_ARG2 0x1B2220
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#define Q8_NX_CDRP_ARG3 0x1B2224
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#define Q8_NX_CDRP_SIGNATURE 0x1B2228
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#define Q8_LINK_STATE 0x1B2298
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#define Q8_LINK_SPEED_0 0x1B22E8
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/*
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* Macros for reading and writing registers
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*/
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#if defined(__i386__) || defined(__amd64__)
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#define Q8_MB() __asm volatile("mfence" ::: "memory")
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#define Q8_WMB() __asm volatile("sfence" ::: "memory")
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#define Q8_RMB() __asm volatile("lfence" ::: "memory")
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#else
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#define Q8_MB()
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#define Q8_WMB()
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#define Q8_RMB()
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#endif
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#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
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#define READ_OFFSET32(ha, off) READ_REG32(ha, off)
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#define WRITE_REG32(ha, reg, val) \
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{\
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bus_write_4((ha->pci_reg), reg, val);\
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bus_read_4((ha->pci_reg), reg);\
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}
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#define WRITE_REG32_MB(ha, reg, val) \
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{\
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Q8_WMB();\
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bus_write_4((ha->pci_reg), reg, val);\
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}
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#define WRITE_OFFSET32(ha, off, val)\
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{\
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bus_write_4((ha->pci_reg), off, val);\
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bus_read_4((ha->pci_reg), off);\
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}
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#endif /* #ifndef _QLA_REG_H_ */
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