399 lines
12 KiB
C
399 lines
12 KiB
C
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/*
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* Copyright (c) 2001 Hellmuth Michaelis. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* Eicon Diehl DIVA 2.0 or 2.02 (ISA PnP) support for isic driver
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* --------------------------------------------------------------
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*
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* $FreeBSD$
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*
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* last edit-date: [Fri Jan 26 13:57:10 2001]
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*
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*---------------------------------------------------------------------------*/
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#include "isic.h"
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#include "opt_i4b.h"
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#if NISIC > 0 && defined EICON_DIVA
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <machine/i4b_ioctl.h>
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#include <i4b/layer1/isic/i4b_isic.h>
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#include <i4b/layer1/isic/i4b_ipac.h>
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#include <i4b/layer1/isic/i4b_isic.h>
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#include <i4b/layer1/isic/i4b_hscx.h>
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/* offsets from base address */
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#define DIVA_IPAC_OFF_ALE 0x00
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#define DIVA_IPAC_OFF_RW 0x01
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#define DIVA_ISAC_OFF_RW 0x02
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#define DIVA_ISAC_OFF_ALE 0x06
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#define DIVA_HSCX_OFF_RW 0x00
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#define DIVA_HSCX_OFF_ALE 0x04
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#define DIVA_CTRL_OFF 0x07
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#define DIVA_CTRL_RDIST 0x01
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#define DIVA_CTRL_WRRST 0x08
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#define DIVA_CTRL_WRLDA 0x20
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#define DIVA_CTRL_WRLDB 0x40
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#define DIVA_CTRL_WRICL 0x80
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/* HSCX channel base offsets */
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#define DIVA_HSCXA 0x00
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#define DIVA_HSCXB 0x40
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.02
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*---------------------------------------------------------------------------*/
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static void
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diva_ipac_read_fifo(struct l1_softc *sc,int what,void *buf,size_t size)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch ( what )
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_ISAC_OFF);
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bus_space_read_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_HSCXA_OFF);
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bus_space_read_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_HSCXB_OFF);
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bus_space_read_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.02
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*---------------------------------------------------------------------------*/
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static void
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diva_ipac_write_fifo(struct l1_softc *sc,int what,void *buf,size_t size)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch ( what )
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_ISAC_OFF);
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bus_space_write_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_HSCXA_OFF);
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bus_space_write_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,IPAC_HSCXB_OFF);
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bus_space_write_multi_1(t,h,DIVA_IPAC_OFF_RW,buf,size);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.02
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*---------------------------------------------------------------------------*/
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static void
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diva_ipac_write_reg(struct l1_softc *sc,int what,bus_size_t reg,u_int8_t data)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch ( what )
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_ISAC_OFF);
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bus_space_write_1(t,h,DIVA_IPAC_OFF_RW,data);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_HSCXA_OFF);
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bus_space_write_1(t,h,DIVA_IPAC_OFF_RW,data);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_HSCXB_OFF);
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bus_space_write_1(t,h,DIVA_IPAC_OFF_RW,data);
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break;
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case ISIC_WHAT_IPAC:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_IPAC_OFF);
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bus_space_write_1(t,h,DIVA_IPAC_OFF_RW,data);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.02
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*---------------------------------------------------------------------------*/
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static u_int8_t
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diva_ipac_read_reg(struct l1_softc *sc,int what,bus_size_t reg)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch ( what )
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_ISAC_OFF);
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return bus_space_read_1(t,h,DIVA_IPAC_OFF_RW);
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_HSCXA_OFF);
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return bus_space_read_1(t,h,DIVA_IPAC_OFF_RW);
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_HSCXB_OFF);
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return bus_space_read_1(t,h,DIVA_IPAC_OFF_RW);
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case ISIC_WHAT_IPAC:
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bus_space_write_1(t,h,DIVA_IPAC_OFF_ALE,reg+IPAC_IPAC_OFF);
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return bus_space_read_1(t,h,DIVA_IPAC_OFF_RW);
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default:
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return 0;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.02
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*---------------------------------------------------------------------------*/
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int
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isic_attach_diva_ipac(device_t dev)
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{
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int unit = device_get_unit(dev);
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struct l1_softc *sc = &l1_sc[unit];
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/* setup access routines */
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sc->clearirq = NULL;
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sc->readreg = diva_ipac_read_reg;
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sc->writereg = diva_ipac_write_reg;
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sc->readfifo = diva_ipac_read_fifo;
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sc->writefifo = diva_ipac_write_fifo;
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/* setup card type */
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sc->sc_cardtyp = CARD_TYPEP_DIVA_ISA;
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/* setup IOM bus type */
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sc->sc_bustyp = BUS_TYPE_IOM2;
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/* setup chip type = IPAC */
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sc->sc_ipac = 1;
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sc->sc_bfifolen = IPAC_BFIFO_LEN;
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/* enable hscx/isac irq's */
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IPAC_WRITE(IPAC_MASK, (IPAC_MASK_INT1 | IPAC_MASK_INT0));
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IPAC_WRITE(IPAC_ACFG, 0); /* outputs are open drain */
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IPAC_WRITE(IPAC_AOE, /* aux 5..2 are inputs, 7, 6 outputs */
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(IPAC_AOE_OE5 | IPAC_AOE_OE4 | IPAC_AOE_OE3 | IPAC_AOE_OE2));
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IPAC_WRITE(IPAC_ATX, 0xff); /* set all output lines high */
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return(0);
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.0
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*---------------------------------------------------------------------------*/
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static void
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diva_read_fifo(struct l1_softc *sc,int what,void *buf,size_t size)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch(what)
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_ISAC_OFF_ALE,0);
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bus_space_read_multi_1(t,h,DIVA_ISAC_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,DIVA_HSCXA);
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bus_space_read_multi_1(t,h,DIVA_HSCX_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,DIVA_HSCXB);
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bus_space_read_multi_1(t,h,DIVA_HSCX_OFF_RW,buf,size);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.0
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*---------------------------------------------------------------------------*/
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static void
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diva_write_fifo(struct l1_softc *sc,int what,void *buf,size_t size)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch(what)
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_ISAC_OFF_ALE,0);
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bus_space_write_multi_1(t,h,DIVA_ISAC_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,DIVA_HSCXA);
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bus_space_write_multi_1(t,h,DIVA_HSCX_OFF_RW,buf,size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,DIVA_HSCXB);
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bus_space_write_multi_1(t,h,DIVA_HSCX_OFF_RW,buf,size);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.0
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*---------------------------------------------------------------------------*/
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static void
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diva_write_reg(struct l1_softc *sc,int what,bus_size_t reg,u_int8_t data)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch(what)
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_ISAC_OFF_ALE,reg);
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bus_space_write_1(t,h,DIVA_ISAC_OFF_RW,data);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,reg+DIVA_HSCXA);
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bus_space_write_1(t,h,DIVA_HSCX_OFF_RW,data);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,reg+DIVA_HSCXB);
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bus_space_write_1(t,h,DIVA_HSCX_OFF_RW,data);
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break;
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}
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}
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/*---------------------------------------------------------------------------*
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* Eicon Diehl DIVA 2.0
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*---------------------------------------------------------------------------*/
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static u_int8_t
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diva_read_reg(struct l1_softc *sc,int what,bus_size_t reg)
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{
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bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
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bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
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switch(what)
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{
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t,h,DIVA_ISAC_OFF_ALE,reg);
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return bus_space_read_1(t,h,DIVA_ISAC_OFF_RW);
|
||
|
|
|
||
|
|
case ISIC_WHAT_HSCXA:
|
||
|
|
bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,reg+DIVA_HSCXA);
|
||
|
|
return bus_space_read_1(t,h,DIVA_HSCX_OFF_RW);
|
||
|
|
|
||
|
|
case ISIC_WHAT_HSCXB:
|
||
|
|
bus_space_write_1(t,h,DIVA_HSCX_OFF_ALE,reg+DIVA_HSCXB);
|
||
|
|
return bus_space_read_1(t,h,DIVA_HSCX_OFF_RW);
|
||
|
|
|
||
|
|
default:
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*
|
||
|
|
* Eicon Diehl DIVA 2.0
|
||
|
|
*---------------------------------------------------------------------------*/
|
||
|
|
int
|
||
|
|
isic_attach_diva(device_t dev)
|
||
|
|
{
|
||
|
|
int unit = device_get_unit(dev);
|
||
|
|
struct l1_softc *sc = &l1_sc[unit];
|
||
|
|
bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
|
||
|
|
bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
|
||
|
|
|
||
|
|
/* setup access routines */
|
||
|
|
|
||
|
|
sc->clearirq = NULL;
|
||
|
|
sc->readreg = diva_read_reg;
|
||
|
|
sc->writereg = diva_write_reg;
|
||
|
|
|
||
|
|
sc->readfifo = diva_read_fifo;
|
||
|
|
sc->writefifo = diva_write_fifo;
|
||
|
|
|
||
|
|
/* setup card type */
|
||
|
|
|
||
|
|
sc->sc_cardtyp = CARD_TYPEP_DIVA_ISA;
|
||
|
|
|
||
|
|
/* setup IOM bus type */
|
||
|
|
|
||
|
|
sc->sc_bustyp = BUS_TYPE_IOM2;
|
||
|
|
|
||
|
|
/* setup chip type = ISAC/HSCX */
|
||
|
|
|
||
|
|
sc->sc_ipac = 0;
|
||
|
|
sc->sc_bfifolen = HSCX_FIFO_LEN;
|
||
|
|
|
||
|
|
/* Read HSCX A/B VSTR. Expected value is 0x05 (V2.1). */
|
||
|
|
|
||
|
|
if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
|
||
|
|
((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
|
||
|
|
{
|
||
|
|
printf("isic%d: HSCX VSTR test failed for Eicon DIVA 2.0\n",
|
||
|
|
sc->sc_unit);
|
||
|
|
printf("isic%d: HSC0: VSTR: %#x\n",
|
||
|
|
sc->sc_unit, HSCX_READ(0, H_VSTR));
|
||
|
|
printf("isic%d: HSC1: VSTR: %#x\n",
|
||
|
|
sc->sc_unit, HSCX_READ(1, H_VSTR));
|
||
|
|
return ENXIO;
|
||
|
|
}
|
||
|
|
/* reset on */
|
||
|
|
bus_space_write_1(t,h,DIVA_CTRL_OFF,0);
|
||
|
|
DELAY(100);
|
||
|
|
/* reset off */
|
||
|
|
bus_space_write_1(t,h,DIVA_CTRL_OFF,DIVA_CTRL_WRRST);
|
||
|
|
return(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* NISIC > 0 && defined EICON_DIVA */
|