2005-01-07 02:29:27 +00:00
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/*-
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2017-11-27 15:09:59 +00:00
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* SPDX-License-Identifier: BSD-3-Clause
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*
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2003-06-28 08:52:49 +00:00
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* Copyright 2003 by Peter Grehan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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2007-08-11 19:25:32 +00:00
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* A driver for the PIC found in the Heathrow/Paddington MacIO chips.
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2003-06-28 08:52:49 +00:00
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* This was superseded by an OpenPIC in the Keylargo and beyond
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* MacIO versions.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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2004-06-25 13:42:48 +00:00
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#include <sys/module.h>
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2003-06-28 08:52:49 +00:00
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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2007-08-11 19:25:32 +00:00
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#include <sys/rman.h>
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2003-06-28 08:52:49 +00:00
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- Introduce an ofw_bus kobj-interface for retrieving the OFW node and a
subset ("compatible", "device_type", "model" and "name") of the standard
properties in drivers for devices on Open Firmware supported busses. The
standard properties "reg", "interrupts" und "address" are not covered by
this interface because they are only of interest in the respective bridge
code. There's a remaining standard property "status" which is unclear how
to support properly but which also isn't used in FreeBSD at present.
This ofw_bus kobj-interface allows to replace the various (ebus_get_node(),
ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type()
vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one.
This in turn allows to simplify and remove code-duplication in drivers for
devices that can hang off of more than one OFW supported bus.
- Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the
drivers for their children to use the ofw_bus kobj-interface. The IVAR-
interfaces of the Central, EBus and FHC are entirely replaced by this. The
PCI bus driver used its own kobj-interface and now also uses the ofw_bus
one. The IVARs special to the SBus, e.g. for retrieving the burst size,
remain.
Beware: this causes an ABI-breakage for modules of drivers which used the
IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be
recompiled.
The style-inconsistencies introduced in some of the bus drivers will be
fixed by tmm@ in a generic clean-up of the respective drivers later (he
requested to add the changes in the "new" style).
- Convert the powerpc MacIO bus driver and the drivers for its children to
use the ofw_bus kobj-interface. This invloves removing the IVARs related
to the "reg" property which were unused and a leftover from the NetBSD
origini of the code. There's no ABI-breakage caused by this because none
of these driver are currently built as modules.
There are other powerpc bus drivers which can be converted to the ofw_bus
kobj-interface, e.g. the PCI bus driver, which should be done together
with converting powerpc to use the OFW PCI code from sparc64.
- Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take
advantage of the ofw_bus kobj-interface and simplify them a bit.
Reviewed by: grehan, tmm
Approved by: re (scottl)
Discussed with: tmm
Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
2004-08-12 17:41:33 +00:00
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#include <dev/ofw/ofw_bus.h>
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2003-06-28 08:52:49 +00:00
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#include <dev/ofw/openfirm.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/pio.h>
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#include <machine/resource.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <powerpc/powermac/hrowpicvar.h>
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#include "pic_if.h"
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/*
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* MacIO interface
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*/
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2007-08-11 19:25:32 +00:00
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static int hrowpic_probe(device_t);
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static int hrowpic_attach(device_t);
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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static void hrowpic_dispatch(device_t, struct trapframe *);
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2019-01-12 22:05:42 +00:00
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static void hrowpic_enable(device_t, u_int, u_int, void **);
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static void hrowpic_eoi(device_t, u_int, void *);
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2008-02-12 18:14:46 +00:00
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static void hrowpic_ipi(device_t, u_int);
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2019-01-12 22:05:42 +00:00
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static void hrowpic_mask(device_t, u_int, void *);
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static void hrowpic_unmask(device_t, u_int, void *);
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2003-06-28 08:52:49 +00:00
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static device_method_t hrowpic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, hrowpic_probe),
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DEVMETHOD(device_attach, hrowpic_attach),
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/* PIC interface */
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2007-08-11 19:25:32 +00:00
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DEVMETHOD(pic_dispatch, hrowpic_dispatch),
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DEVMETHOD(pic_enable, hrowpic_enable),
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DEVMETHOD(pic_eoi, hrowpic_eoi),
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2008-02-12 18:14:46 +00:00
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DEVMETHOD(pic_ipi, hrowpic_ipi),
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2007-08-11 19:25:32 +00:00
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DEVMETHOD(pic_mask, hrowpic_mask),
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DEVMETHOD(pic_unmask, hrowpic_unmask),
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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{ 0, 0 },
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2003-06-28 08:52:49 +00:00
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};
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static driver_t hrowpic_driver = {
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"hrowpic",
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hrowpic_methods,
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sizeof(struct hrowpic_softc)
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};
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2022-05-10 17:21:38 +00:00
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DRIVER_MODULE(hrowpic, macio, hrowpic_driver, 0, 0);
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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static uint32_t
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hrowpic_read_reg(struct hrowpic_softc *sc, u_int reg, u_int bank)
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2004-01-13 11:25:40 +00:00
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{
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2007-08-11 19:25:32 +00:00
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if (bank == HPIC_PRIMARY)
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reg += HPIC_1ST_OFFSET;
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2004-01-13 11:25:40 +00:00
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2007-08-11 19:25:32 +00:00
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return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
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}
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2004-01-13 11:25:40 +00:00
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2007-08-11 19:25:32 +00:00
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static void
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hrowpic_write_reg(struct hrowpic_softc *sc, u_int reg, u_int bank,
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uint32_t val)
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{
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2004-01-13 11:25:40 +00:00
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2007-08-11 19:25:32 +00:00
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if (bank == HPIC_PRIMARY)
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reg += HPIC_1ST_OFFSET;
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bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
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2004-01-13 11:25:40 +00:00
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2007-08-11 19:25:32 +00:00
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/* XXX Issue a read to force the write to complete. */
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bus_space_read_4(sc->sc_bt, sc->sc_bh, reg);
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2004-01-13 11:25:40 +00:00
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}
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2003-06-28 08:52:49 +00:00
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static int
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hrowpic_probe(device_t dev)
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{
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2007-08-11 19:25:32 +00:00
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const char *type = ofw_bus_get_type(dev);
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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/*
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* OpenPIC cells have a type of "open-pic", so this
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* is sufficient to identify a Heathrow cell
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*/
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if (strcmp(type, "interrupt-controller") != 0)
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2003-06-28 08:52:49 +00:00
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return (ENXIO);
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2007-08-11 19:25:32 +00:00
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/*
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* The description was already printed out in the nexus
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* probe, so don't do it again here
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*/
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device_set_desc(dev, "Heathrow MacIO interrupt controller");
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2003-06-28 08:52:49 +00:00
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return (0);
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}
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static int
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hrowpic_attach(device_t dev)
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{
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struct hrowpic_softc *sc;
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sc = device_get_softc(dev);
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2007-08-11 19:25:32 +00:00
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sc->sc_dev = dev;
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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sc->sc_rrid = 0;
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sc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rrid,
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RF_ACTIVE);
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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if (sc->sc_rres == NULL) {
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device_printf(dev, "Could not alloc mem resource!\n");
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2003-06-28 08:52:49 +00:00
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return (ENXIO);
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}
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2007-08-11 19:25:32 +00:00
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sc->sc_bt = rman_get_bustag(sc->sc_rres);
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sc->sc_bh = rman_get_bushandle(sc->sc_rres);
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2003-06-28 08:52:49 +00:00
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/*
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* Disable all interrupt sources and clear outstanding interrupts
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*/
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hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_PRIMARY, 0);
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hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_PRIMARY, 0xffffffff);
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hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_SECONDARY, 0);
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hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff);
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2007-08-11 19:25:32 +00:00
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Fix the interrupt code, broken 7 months ago. The interrupt framework
already supported nested PICs, but was limited to having a nested
AT-PIC only. With G5 support the need for nested OpenPIC controllers
needed to be added. This was done the wrong way and broke the MPC8555
eval system in the process.
OFW, as well as FDT, describe the interrupt routing in terms of a
controller and an interrupt pin on it. This needs to be mapped to a
flat and global resource: the IRQ. The IRQ is the same as the PCI
intline and as such needs to be representable in 8 bits. Secondly,
ISA support pretty much dictates that IRQ 0-15 should be reserved
for ISA interrupts, because of the internal workins of south bridges.
Both were broken.
This change reverts revision 209298 for a big part and re-implements
it simpler. In particular:
o The id() method of the PIC I/F is removed again. It's not needed.
o The openpic_attach() function has been changed to take the OFW
or FDT phandle of the controller as a second argument. All bus
attachments that previously used openpic_attach() as the attach
method of the device I/F now implement as bus-specific method
and pass the phandle_t to the renamed openpic_attach().
o Change powerpc_register_pic() to take a few more arguments. In
particular:
- Pass the number of IPIs specificly. The number of IRQs carved
out for a PIC is the sum of the number of int. pins and IPIs.
- Pass a flag indicating whether the PIC is an AT-PIC or not.
This tells the interrupt framework whether to assign IRQ 0-15
or some other range.
o Until we implement proper multi-pass bus enumeration, we have to
handle the case where we need to map from PIC+pin to IRQ *before*
the PIC gets registered. This is done in a similar way as before,
but rather than carving out 256 IRQs per PIC, we carve out 128
IRQs (124 pins + 4 IPIs). This is supposed to handle the G5 case,
but should really be fixed properly using multiple passes.
o Have the interrupt framework set root_pic in most cases and not
put that burden in PIC drivers (for the most part).
o Remove powerpc_ign_lookup() and replace it with powerpc_get_irq().
Remove IGN_SHIFT, INTR_INTLINE and INTR_IGN.
Related to the above, fix the Freescale PCI controller driver, broken
by the FDT code. Besides not attaching properly, bus numbers were
assigned improperly and enumeration was broken in general. This
prevented the AT PIC from being discovered and interrupt routing to
work properly. Consequently, the ata(4) controller stopped functioning.
Fix the driver, and FDT PCI support, enough to get the MPC8555CDS
going again. The FDT PCI code needs a whole lot more work.
No breakages are expected, but lackiong G5 hardware, it's possible
that there are unpleasant side-effects. At least MPC85xx support is
back to where it was 7 months ago -- it's amazing how badly support
can be broken in just 7 months...
Sponsored by: Juniper Networks
2011-01-29 20:58:38 +00:00
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powerpc_register_pic(dev, ofw_bus_get_node(dev), 64, 0, FALSE);
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2007-08-11 19:25:32 +00:00
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return (0);
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2003-06-28 08:52:49 +00:00
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}
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2007-08-11 19:25:32 +00:00
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/*
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* Local routines
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*/
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2003-06-28 08:52:49 +00:00
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static void
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hrowpic_toggle_irq(struct hrowpic_softc *sc, int irq, int enable)
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{
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u_int roffset;
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u_int rbit;
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2009-10-24 18:31:22 +00:00
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KASSERT((irq > 0) && (irq <= HROWPIC_IRQMAX), ("en irq out of range"));
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/*
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* Humor the SMP layer if it wants to set up an IPI handler.
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*/
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if (irq == HROWPIC_IRQMAX)
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return;
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2003-06-28 08:52:49 +00:00
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/*
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* Calculate prim/sec register bank for the IRQ, update soft copy,
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* and enable the IRQ as an interrupt source
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*/
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roffset = HPIC_INT_TO_BANK(irq);
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rbit = HPIC_INT_TO_REGBIT(irq);
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if (enable)
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sc->sc_softreg[roffset] |= (1 << rbit);
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else
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sc->sc_softreg[roffset] &= ~(1 << rbit);
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hrowpic_write_reg(sc, HPIC_ENABLE, roffset, sc->sc_softreg[roffset]);
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}
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2007-08-11 19:25:32 +00:00
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/*
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* PIC I/F methods.
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*/
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2003-06-28 08:52:49 +00:00
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static void
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2007-08-11 19:25:32 +00:00
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hrowpic_dispatch(device_t dev, struct trapframe *tf)
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2003-06-28 08:52:49 +00:00
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{
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struct hrowpic_softc *sc;
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2007-08-11 19:25:32 +00:00
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uint64_t mask;
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uint32_t reg;
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u_int irq;
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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sc = device_get_softc(dev);
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while (1) {
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mask = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_SECONDARY);
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reg = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_PRIMARY);
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mask = (mask << 32) | reg;
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if (mask == 0)
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break;
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irq = 0;
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while (irq < HROWPIC_IRQMAX) {
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if (mask & 1)
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powerpc_dispatch_intr(sc->sc_vector[irq], tf);
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mask >>= 1;
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irq++;
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2003-06-28 08:52:49 +00:00
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}
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2007-08-11 19:25:32 +00:00
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}
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2003-06-28 08:52:49 +00:00
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}
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static void
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2019-01-12 22:05:42 +00:00
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hrowpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
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2003-06-28 08:52:49 +00:00
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{
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2007-08-11 19:25:32 +00:00
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struct hrowpic_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_vector[irq] = vector;
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hrowpic_toggle_irq(sc, irq, 1);
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2003-06-28 08:52:49 +00:00
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}
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static void
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2019-01-12 22:05:42 +00:00
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hrowpic_eoi(device_t dev, u_int irq, void *priv __unused)
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2003-06-28 08:52:49 +00:00
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{
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2007-08-11 19:25:32 +00:00
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struct hrowpic_softc *sc;
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int bank;
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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sc = device_get_softc(dev);
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bank = (irq >= 32) ? HPIC_SECONDARY : HPIC_PRIMARY ;
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hrowpic_write_reg(sc, HPIC_CLEAR, bank, 1U << (irq & 0x1f));
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}
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2003-06-28 08:52:49 +00:00
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2008-02-12 18:14:46 +00:00
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static void
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hrowpic_ipi(device_t dev, u_int irq)
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{
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/* No SMP support. */
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}
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2007-08-11 19:25:32 +00:00
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static void
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2019-01-12 22:05:42 +00:00
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hrowpic_mask(device_t dev, u_int irq, void *priv __unused)
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2003-06-28 08:52:49 +00:00
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{
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2007-08-11 19:25:32 +00:00
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struct hrowpic_softc *sc;
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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sc = device_get_softc(dev);
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hrowpic_toggle_irq(sc, irq, 0);
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2003-06-28 08:52:49 +00:00
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}
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2007-08-11 19:25:32 +00:00
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static void
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2019-01-12 22:05:42 +00:00
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hrowpic_unmask(device_t dev, u_int irq, void *priv __unused)
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2003-06-28 08:52:49 +00:00
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{
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2007-08-11 19:25:32 +00:00
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struct hrowpic_softc *sc;
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2003-06-28 08:52:49 +00:00
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2007-08-11 19:25:32 +00:00
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sc = device_get_softc(dev);
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hrowpic_toggle_irq(sc, irq, 1);
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2003-06-28 08:52:49 +00:00
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}
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