59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
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/* $FreeBSD$ */
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#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_
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#define _MIPS32_SENTRY5_SENTRY5REG_H_
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#define SENTRY5_UART0ADR 0x18000300
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#define SENTRY5_UART1ADR 0x18000400
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/* Reset register implemented here in a PLD device. */
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#define SENTRY5_EXTIFADR 0x1F000000
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#define SENTRY5_DORESET 0x80
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/*
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* Custom CP0 register macros.
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* XXX: This really needs the mips cpuregs.h file for the barrier.
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*/
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#define S5_RDRW32_C0P0_CUST22(n,r) \
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static __inline u_int32_t \
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s5_rd_ ## n (void) \
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{ \
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int v0; \
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__asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \
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: [v0] "=&r"(v0)); \
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/*mips_barrier();*/ \
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return (v0); \
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} \
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static __inline void \
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s5_wr_ ## n (u_int32_t a0) \
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{ \
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__asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \
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__XSTRING(COP0_SYNC)";" \
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"nop;" \
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"nop;" \
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: \
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: [a0] "r"(a0)); \
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/*mips_barrier();*/ \
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} struct __hack
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/*
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* All 5 of these sub-registers are used by Linux.
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* There is a further custom register at 25 which is not used.
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*/
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#define S5_CP0_DIAG 0
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#define S5_CP0_CLKCFG1 1
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#define S5_CP0_CLKCFG2 2
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#define S5_CP0_SYNC 3
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#define S5_CP0_CLKCFG3 4
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#define S5_CP0_RESET 5
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/* s5_[rd|wr]_xxx() */
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S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG);
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S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1);
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S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2);
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S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC);
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S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3);
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S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET);
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#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */
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