307 lines
11 KiB
C++
307 lines
11 KiB
C++
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//===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a wrapper around MCSchedModel that allows the interface
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// to benefit from information currently only available in TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
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cl::desc("Use TargetSchedModel for latency lookup"));
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static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
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cl::desc("Use InstrItineraryData for latency lookup"));
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bool TargetSchedModel::hasInstrSchedModel() const {
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return EnableSchedModel && SchedModel.hasInstrSchedModel();
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}
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bool TargetSchedModel::hasInstrItineraries() const {
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return EnableSchedItins && !InstrItins.isEmpty();
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}
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static unsigned gcd(unsigned Dividend, unsigned Divisor) {
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// Dividend and Divisor will be naturally swapped as needed.
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while(Divisor) {
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unsigned Rem = Dividend % Divisor;
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Dividend = Divisor;
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Divisor = Rem;
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};
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return Dividend;
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}
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static unsigned lcm(unsigned A, unsigned B) {
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unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
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assert((LCM >= A && LCM >= B) && "LCM overflow");
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return LCM;
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}
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void TargetSchedModel::init(const MCSchedModel &sm,
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const TargetSubtargetInfo *sti,
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const TargetInstrInfo *tii) {
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SchedModel = sm;
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STI = sti;
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TII = tii;
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STI->initInstrItins(InstrItins);
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unsigned NumRes = SchedModel.getNumProcResourceKinds();
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ResourceFactors.resize(NumRes);
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ResourceLCM = SchedModel.IssueWidth;
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for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
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unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
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if (NumUnits > 0)
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ResourceLCM = lcm(ResourceLCM, NumUnits);
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}
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MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
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for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
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unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
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ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
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}
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}
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unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
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const MCSchedClassDesc *SC) const {
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if (hasInstrItineraries()) {
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int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
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return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
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}
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if (hasInstrSchedModel()) {
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if (!SC)
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SC = resolveSchedClass(MI);
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if (SC->isValid())
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return SC->NumMicroOps;
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}
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return MI->isTransient() ? 0 : 1;
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}
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// The machine model may explicitly specify an invalid latency, which
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// effectively means infinite latency. Since users of the TargetSchedule API
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// don't know how to handle this, we convert it to a very large latency that is
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// easy to distinguish when debugging the DAG but won't induce overflow.
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static unsigned convertLatency(int Cycles) {
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return Cycles >= 0 ? Cycles : 1000;
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}
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/// If we can determine the operand latency from the def only, without machine
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/// model or itinerary lookup, do so. Otherwise return -1.
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int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
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bool FindMin) const {
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// Return a latency based on the itinerary properties and defining instruction
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// if possible. Some common subtargets don't require per-operand latency,
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// especially for minimum latencies.
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if (FindMin) {
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// If MinLatency is invalid, then use the itinerary for MinLatency. If no
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// itinerary exists either, then use single cycle latency.
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if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
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return 1;
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}
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return SchedModel.MinLatency;
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}
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else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
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return TII->defaultDefLatency(&SchedModel, DefMI);
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}
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// ...operand lookup required
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return -1;
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}
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/// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
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/// evaluation of predicates that depend on instruction operands or flags.
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const MCSchedClassDesc *TargetSchedModel::
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resolveSchedClass(const MachineInstr *MI) const {
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// Get the definition's scheduling class descriptor from this machine model.
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unsigned SchedClass = MI->getDesc().getSchedClass();
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const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
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#ifndef NDEBUG
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unsigned NIter = 0;
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#endif
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while (SCDesc->isVariant()) {
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assert(++NIter < 6 && "Variants are nested deeper than the magic number");
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SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
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SCDesc = SchedModel.getSchedClassDesc(SchedClass);
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}
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return SCDesc;
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}
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/// Find the def index of this operand. This index maps to the machine model and
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/// is independent of use operands. Def operands may be reordered with uses or
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/// merged with uses without affecting the def index (e.g. before/after
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/// regalloc). However, an instruction's def operands must never be reordered
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/// with respect to each other.
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static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
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unsigned DefIdx = 0;
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for (unsigned i = 0; i != DefOperIdx; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef())
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++DefIdx;
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}
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return DefIdx;
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}
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/// Find the use index of this operand. This is independent of the instruction's
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/// def operands.
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///
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/// Note that uses are not determined by the operand's isUse property, which
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/// is simply the inverse of isDef. Here we consider any readsReg operand to be
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/// a "use". The machine model allows an operand to be both a Def and Use.
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static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
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unsigned UseIdx = 0;
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for (unsigned i = 0; i != UseOperIdx; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.readsReg())
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++UseIdx;
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}
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return UseIdx;
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}
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// Top-level API for clients that know the operand indices.
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unsigned TargetSchedModel::computeOperandLatency(
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const MachineInstr *DefMI, unsigned DefOperIdx,
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const MachineInstr *UseMI, unsigned UseOperIdx,
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bool FindMin) const {
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int DefLatency = getDefLatency(DefMI, FindMin);
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if (DefLatency >= 0)
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return DefLatency;
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if (hasInstrItineraries()) {
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int OperLatency = 0;
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if (UseMI) {
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OperLatency =
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TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
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}
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else {
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unsigned DefClass = DefMI->getDesc().getSchedClass();
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OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
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}
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if (OperLatency >= 0)
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return OperLatency;
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// No operand latency was found.
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unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
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// Expected latency is the max of the stage latency and itinerary props.
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// Rather than directly querying InstrItins stage latency, we call a TII
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// hook to allow subtargets to specialize latency. This hook is only
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// applicable to the InstrItins model. InstrSchedModel should model all
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// special cases without TII hooks.
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if (!FindMin)
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InstrLatency = std::max(InstrLatency,
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TII->defaultDefLatency(&SchedModel, DefMI));
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return InstrLatency;
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}
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assert(!FindMin && hasInstrSchedModel() &&
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"Expected a SchedModel for this cpu");
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const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
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unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
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if (DefIdx < SCDesc->NumWriteLatencyEntries) {
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// Lookup the definition's write latency in SubtargetInfo.
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const MCWriteLatencyEntry *WLEntry =
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STI->getWriteLatencyEntry(SCDesc, DefIdx);
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unsigned WriteID = WLEntry->WriteResourceID;
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unsigned Latency = convertLatency(WLEntry->Cycles);
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if (!UseMI)
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return Latency;
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// Lookup the use's latency adjustment in SubtargetInfo.
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const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
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if (UseDesc->NumReadAdvanceEntries == 0)
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return Latency;
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unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
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return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
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}
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// If DefIdx does not exist in the model (e.g. implicit defs), then return
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// unit latency (defaultDefLatency may be too conservative).
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#ifndef NDEBUG
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if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
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&& !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
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std::string Err;
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raw_string_ostream ss(Err);
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ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
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<< *DefMI;
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report_fatal_error(ss.str());
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}
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#endif
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return DefMI->isTransient() ? 0 : 1;
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}
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unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
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// For the itinerary model, fall back to the old subtarget hook.
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// Allow subtargets to compute Bundle latencies outside the machine model.
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if (hasInstrItineraries() || MI->isBundle())
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return TII->getInstrLatency(&InstrItins, MI);
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if (hasInstrSchedModel()) {
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const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
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if (SCDesc->isValid()) {
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unsigned Latency = 0;
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for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
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DefIdx != DefEnd; ++DefIdx) {
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// Lookup the definition's write latency in SubtargetInfo.
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const MCWriteLatencyEntry *WLEntry =
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STI->getWriteLatencyEntry(SCDesc, DefIdx);
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Latency = std::max(Latency, convertLatency(WLEntry->Cycles));
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}
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return Latency;
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}
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}
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return TII->defaultDefLatency(&SchedModel, MI);
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}
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unsigned TargetSchedModel::
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computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
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const MachineInstr *DepMI) const {
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// MinLatency == -1 is for in-order processors that always have unit
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// MinLatency. MinLatency > 0 is for in-order processors with varying min
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// latencies, but since this is not a RAW dep, we always use unit latency.
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if (SchedModel.MinLatency != 0)
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return 1;
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// MinLatency == 0 indicates an out-of-order processor that can dispatch
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// WAW dependencies in the same cycle.
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// Treat predication as a data dependency for out-of-order cpus. In-order
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// cpus do not need to treat predicated writes specially.
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//
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// TODO: The following hack exists because predication passes do not
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// correctly append imp-use operands, and readsReg() strangely returns false
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// for predicated defs.
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unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
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const MachineFunction &MF = *DefMI->getParent()->getParent();
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
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return computeInstrLatency(DefMI);
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// If we have a per operand scheduling model, check if this def is writing
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// an unbuffered resource. If so, it treated like an in-order cpu.
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if (hasInstrSchedModel()) {
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const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
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if (SCDesc->isValid()) {
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for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
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*PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
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if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)
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return 1;
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}
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}
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}
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return 0;
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}
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