2019-10-25 18:10:02 +00:00
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.Org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Rockchip PHY TYPEC
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/phy/phy_usb.h>
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#include <dev/extres/syscon/syscon.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "syscon_if.h"
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#define GRF_USB3OTG_BASE(x) (0x2430 + (0x10 * x))
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#define GRF_USB3OTG_CON0(x) (GRF_USB3OTG_BASE(x) + 0x0)
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#define GRF_USB3OTG_CON1(x) (GRF_USB3OTG_BASE(x) + 0x4)
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#define USB3OTG_CON1_U3_DIS (1 << 0)
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#define GRF_USB3PHY_BASE(x) (0x0e580 + (0xc * (x)))
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#define GRF_USB3PHY_CON0(x) (GRF_USB3PHY_BASE(x) + 0x0)
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#define USB3PHY_CON0_USB2_ONLY (1 << 3)
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#define GRF_USB3PHY_CON1(x) (GRF_USB3PHY_BASE(x) + 0x4)
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#define GRF_USB3PHY_CON2(x) (GRF_USB3PHY_BASE(x) + 0x8)
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#define GRF_USB3PHY_STATUS0 0x0e5c0
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#define GRF_USB3PHY_STATUS1 0x0e5c4
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#define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
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#define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
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#define CMN_PLL0_INTDIV (0x94 << 2)
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#define CMN_PLL0_FRACDIV (0x95 << 2)
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#define CMN_PLL0_HIGH_THR (0x96 << 2)
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#define CMN_PLL0_DSM_DIAG (0x97 << 2)
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#define CMN_PLL0_SS_CTRL1 (0x98 << 2)
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#define CMN_PLL0_SS_CTRL2 (0x99 << 2)
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#define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2)
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#define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2)
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#define CMN_DIAG_PLL0_OVRD (0x1c2 << 2)
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#define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2)
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#define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2)
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#define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2)
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#define CMN_DIAG_HSCLK_SEL (0x1e0 << 2)
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#define CMN_DIAG_HSCLK_SEL_PLL_CONFIG 0x30
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#define CMN_DIAG_HSCLK_SEL_PLL_MASK 0x33
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#define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2)
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#define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2)
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#define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2)
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#define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2)
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#define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2)
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#define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2)
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#define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2)
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#define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2)
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#define TX_RCVDET_ST_TMR(lane) ((0x4123 | ((lane) << 9)) << 2)
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#define RX_PSC_A0(lane) ((0x8000 | ((lane) << 9)) << 2)
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#define RX_PSC_A1(lane) ((0x8001 | ((lane) << 9)) << 2)
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#define RX_PSC_A2(lane) ((0x8002 | ((lane) << 9)) << 2)
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#define RX_PSC_A3(lane) ((0x8003 | ((lane) << 9)) << 2)
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#define RX_PSC_CAL(lane) ((0x8006 | ((lane) << 9)) << 2)
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#define RX_PSC_RDY(lane) ((0x8007 | ((lane) << 9)) << 2)
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#define RX_SIGDET_HL_FILT_TMR(lane) ((0x8090 | ((lane) << 9)) << 2)
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#define RX_REE_CTRL_DATA_MASK(lane) ((0x81bb | ((lane) << 9)) << 2)
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#define RX_DIAG_SIGDET_TUNE(lane) ((0x81dc | ((lane) << 9)) << 2)
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#define PMA_LANE_CFG (0xc000 << 2)
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#define PIN_ASSIGN_D_F 0x5100
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#define DP_MODE_CTL (0xc008 << 2)
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#define DP_MODE_ENTER_A2 0xc104
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#define PMA_CMN_CTRL1 (0xc800 << 2)
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#define PMA_CMN_CTRL1_READY (1 << 0)
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static struct ofw_compat_data compat_data[] = {
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{ "rockchip,rk3399-typec-phy", 1 },
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{ NULL, 0 }
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};
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static struct resource_spec rk_typec_phy_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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struct rk_typec_phy_softc {
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device_t dev;
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struct resource *res;
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struct syscon *grf;
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clk_t tcpdcore;
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clk_t tcpdphy_ref;
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hwreset_t rst_uphy;
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hwreset_t rst_pipe;
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hwreset_t rst_tcphy;
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int mode;
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int phy_ctrl_id;
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};
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#define RK_TYPEC_PHY_READ(sc, reg) bus_read_4(sc->res, (reg))
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#define RK_TYPEC_PHY_WRITE(sc, reg, val) bus_write_4(sc->res, (reg), (val))
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/* Phy class and methods. */
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static int rk_typec_phy_enable(struct phynode *phynode, bool enable);
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static int rk_typec_phy_get_mode(struct phynode *phy, int *mode);
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static int rk_typec_phy_set_mode(struct phynode *phy, int mode);
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static phynode_method_t rk_typec_phy_phynode_methods[] = {
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PHYNODEMETHOD(phynode_enable, rk_typec_phy_enable),
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PHYNODEMETHOD(phynode_usb_get_mode, rk_typec_phy_get_mode),
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PHYNODEMETHOD(phynode_usb_set_mode, rk_typec_phy_set_mode),
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PHYNODEMETHOD_END
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};
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DEFINE_CLASS_1(rk_typec_phy_phynode, rk_typec_phy_phynode_class,
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rk_typec_phy_phynode_methods,
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sizeof(struct phynode_usb_sc), phynode_usb_class);
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enum RK3399_USBPHY {
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RK3399_TYPEC_PHY_DP = 0,
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RK3399_TYPEC_PHY_USB3,
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};
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static void
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rk_typec_phy_set_usb2_only(struct rk_typec_phy_softc *sc, bool usb2only)
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{
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uint32_t reg;
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/* Disable usb3tousb2 only */
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reg = SYSCON_READ_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id));
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if (usb2only)
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reg |= USB3PHY_CON0_USB2_ONLY;
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else
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reg &= ~USB3PHY_CON0_USB2_ONLY;
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/* Write Mask */
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reg |= (USB3PHY_CON0_USB2_ONLY) << 16;
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SYSCON_WRITE_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id), reg);
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/* Enable the USB3 Super Speed port */
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reg = SYSCON_READ_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id));
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if (usb2only)
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reg |= USB3OTG_CON1_U3_DIS;
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else
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reg &= ~USB3OTG_CON1_U3_DIS;
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/* Write Mask */
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reg |= (USB3OTG_CON1_U3_DIS) << 16;
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SYSCON_WRITE_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id), reg);
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}
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static int
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rk_typec_phy_enable(struct phynode *phynode, bool enable)
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{
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struct rk_typec_phy_softc *sc;
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device_t dev;
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intptr_t phy;
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uint32_t reg;
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2019-10-29 18:36:16 +00:00
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int err, retry;
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2019-10-25 18:10:02 +00:00
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dev = phynode_get_device(phynode);
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phy = phynode_get_id(phynode);
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sc = device_get_softc(dev);
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if (phy != RK3399_TYPEC_PHY_USB3)
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return (ERANGE);
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rk_typec_phy_set_usb2_only(sc, false);
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err = clk_enable(sc->tcpdcore);
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if (err != 0) {
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device_printf(dev, "Could not enable clock %s\n",
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clk_get_name(sc->tcpdcore));
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return (ENXIO);
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}
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err = clk_enable(sc->tcpdphy_ref);
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if (err != 0) {
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device_printf(dev, "Could not enable clock %s\n",
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clk_get_name(sc->tcpdphy_ref));
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clk_disable(sc->tcpdcore);
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return (ENXIO);
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}
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hwreset_deassert(sc->rst_tcphy);
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/* 24M configuration, magic values from rockchip */
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RK_TYPEC_PHY_WRITE(sc, PMA_CMN_CTRL1, 0x830);
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for (int i = 0; i < 4; i++) {
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RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90);
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RK_TYPEC_PHY_WRITE(sc, TX_RCVDET_EN_TMR(i), 0x960);
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RK_TYPEC_PHY_WRITE(sc, TX_RCVDET_ST_TMR(i), 0x30);
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}
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reg = RK_TYPEC_PHY_READ(sc, CMN_DIAG_HSCLK_SEL);
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reg &= ~CMN_DIAG_HSCLK_SEL_PLL_MASK;
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reg |= CMN_DIAG_HSCLK_SEL_PLL_CONFIG;
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_HSCLK_SEL, reg);
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/* PLL configuration, magic values from rockchip */
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_VCOCAL_INIT, 0xf0);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_VCOCAL_ITER, 0x18);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_INTDIV, 0xd0);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_FRACDIV, 0x4a4a);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_HIGH_THR, 0x34);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_SS_CTRL1, 0x1ee);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_SS_CTRL2, 0x7f03);
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RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_DSM_DIAG, 0x20);
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_OVRD, 0);
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_FBH_OVRD, 0);
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_FBL_OVRD, 0);
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_V2I_TUNE, 0x7);
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_CP_TUNE, 0x45);
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RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_LF_PROG, 0x8);
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/* Configure the TX and RX line, magic values from rockchip */
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RK_TYPEC_PHY_WRITE(sc, TX_PSC_A0(0), 0x7799);
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RK_TYPEC_PHY_WRITE(sc, TX_PSC_A1(0), 0x7798);
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RK_TYPEC_PHY_WRITE(sc, TX_PSC_A2(0), 0x5098);
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RK_TYPEC_PHY_WRITE(sc, TX_PSC_A3(0), 0x5098);
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RK_TYPEC_PHY_WRITE(sc, TX_TXCC_MGNFS_MULT_000(0), 0x0);
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RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_BIDI_CTRL(0), 0xbf);
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RK_TYPEC_PHY_WRITE(sc, RX_PSC_A0(1), 0xa6fd);
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RK_TYPEC_PHY_WRITE(sc, RX_PSC_A1(1), 0xa6fd);
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RK_TYPEC_PHY_WRITE(sc, RX_PSC_A2(1), 0xa410);
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RK_TYPEC_PHY_WRITE(sc, RX_PSC_A3(1), 0x2410);
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RK_TYPEC_PHY_WRITE(sc, RX_PSC_CAL(1), 0x23ff);
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RK_TYPEC_PHY_WRITE(sc, RX_SIGDET_HL_FILT_TMR(1), 0x13);
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RK_TYPEC_PHY_WRITE(sc, RX_REE_CTRL_DATA_MASK(1), 0x03e7);
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RK_TYPEC_PHY_WRITE(sc, RX_DIAG_SIGDET_TUNE(1), 0x1004);
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RK_TYPEC_PHY_WRITE(sc, RX_PSC_RDY(1), 0x2010);
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RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_BIDI_CTRL(1), 0xfb);
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RK_TYPEC_PHY_WRITE(sc, PMA_LANE_CFG, PIN_ASSIGN_D_F);
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RK_TYPEC_PHY_WRITE(sc, DP_MODE_CTL, DP_MODE_ENTER_A2);
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hwreset_deassert(sc->rst_uphy);
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2019-10-29 18:36:16 +00:00
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for (retry = 10000; retry > 0; retry--) {
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2019-10-25 18:10:02 +00:00
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reg = RK_TYPEC_PHY_READ(sc, PMA_CMN_CTRL1);
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if (reg & PMA_CMN_CTRL1_READY)
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break;
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DELAY(10);
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}
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2019-10-29 18:36:16 +00:00
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if (retry == 0) {
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2019-10-25 18:10:02 +00:00
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device_printf(sc->dev, "Timeout waiting for PMA\n");
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return (ENXIO);
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}
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hwreset_deassert(sc->rst_pipe);
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return (0);
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}
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static int
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rk_typec_phy_get_mode(struct phynode *phynode, int *mode)
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{
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struct rk_typec_phy_softc *sc;
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intptr_t phy;
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device_t dev;
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dev = phynode_get_device(phynode);
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phy = phynode_get_id(phynode);
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sc = device_get_softc(dev);
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if (phy != RK3399_TYPEC_PHY_USB3)
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return (ERANGE);
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*mode = sc->mode;
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return (0);
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}
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static int
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rk_typec_phy_set_mode(struct phynode *phynode, int mode)
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{
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struct rk_typec_phy_softc *sc;
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intptr_t phy;
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device_t dev;
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dev = phynode_get_device(phynode);
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phy = phynode_get_id(phynode);
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sc = device_get_softc(dev);
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if (phy != RK3399_TYPEC_PHY_USB3)
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return (ERANGE);
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sc->mode = mode;
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return (0);
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}
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static int
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rk_typec_phy_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Rockchip RK3399 PHY TYPEC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk_typec_phy_attach(device_t dev)
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{
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struct rk_typec_phy_softc *sc;
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struct phynode_init_def phy_init;
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struct phynode *phynode;
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phandle_t node, usb3;
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phandle_t reg_prop[4];
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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/*
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* Find out which phy we are.
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* There is not property for this so we need to know the
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* address to use the correct GRF registers.
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*/
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if (OF_getencprop(node, "reg", reg_prop, sizeof(reg_prop)) <= 0) {
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device_printf(dev, "Cannot guess phy controller id\n");
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return (ENXIO);
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}
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switch (reg_prop[1]) {
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case 0xff7c0000:
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sc->phy_ctrl_id = 0;
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break;
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case 0xff800000:
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sc->phy_ctrl_id = 1;
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break;
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default:
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device_printf(dev, "Unknown address %x for typec-phy\n", reg_prop[1]);
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return (ENXIO);
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}
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if (bus_alloc_resources(dev, rk_typec_phy_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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goto fail;
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}
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if (syscon_get_by_ofw_property(dev, node,
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"rockchip,grf", &sc->grf) != 0) {
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device_printf(dev, "Cannot get syscon handle\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "tcpdcore", &sc->tcpdcore) != 0) {
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device_printf(dev, "Cannot get tcpdcore clock\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "tcpdphy-ref", &sc->tcpdphy_ref) != 0) {
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device_printf(dev, "Cannot get tcpdphy-ref clock\n");
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goto fail;
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}
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if (hwreset_get_by_ofw_name(dev, 0, "uphy", &sc->rst_uphy) != 0) {
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|
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device_printf(dev, "Cannot get uphy reset\n");
|
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|
|
goto fail;
|
|
|
|
}
|
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|
|
if (hwreset_get_by_ofw_name(dev, 0, "uphy-pipe", &sc->rst_pipe) != 0) {
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|
|
device_printf(dev, "Cannot get uphy-pipe reset\n");
|
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|
|
goto fail;
|
|
|
|
}
|
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|
|
if (hwreset_get_by_ofw_name(dev, 0, "uphy-tcphy", &sc->rst_tcphy) != 0) {
|
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device_printf(dev, "Cannot get uphy-tcphy reset\n");
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|
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goto fail;
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|
|
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}
|
|
|
|
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|
|
/*
|
|
|
|
* Make sure that the module is asserted
|
|
|
|
* We need to deassert in a certain order when we enable the phy
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|
|
|
*/
|
|
|
|
hwreset_assert(sc->rst_uphy);
|
|
|
|
hwreset_assert(sc->rst_pipe);
|
|
|
|
hwreset_assert(sc->rst_tcphy);
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|
|
/* Set the assigned clocks parent and freq */
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|
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if (clk_set_assigned(dev, node) != 0) {
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device_printf(dev, "clk_set_assigned failed\n");
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|
|
goto fail;
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|
|
|
}
|
|
|
|
|
|
|
|
/* Only usb3 port is supported right now */
|
|
|
|
usb3 = ofw_bus_find_child(node, "usb3-port");
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|
|
|
if (usb3 == 0) {
|
|
|
|
device_printf(dev, "Cannot find usb3-port child node\n");
|
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|
|
goto fail;
|
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|
|
}
|
|
|
|
/* If the child isn't enable attach the driver
|
|
|
|
* but do not register the PHY.
|
|
|
|
*/
|
|
|
|
if (!ofw_bus_node_status_okay(usb3))
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
phy_init.id = RK3399_TYPEC_PHY_USB3;
|
|
|
|
phy_init.ofw_node = usb3;
|
|
|
|
phynode = phynode_create(dev, &rk_typec_phy_phynode_class, &phy_init);
|
|
|
|
if (phynode == NULL) {
|
|
|
|
device_printf(dev, "failed to create phy usb3-port\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
if (phynode_register(phynode) == NULL) {
|
|
|
|
device_printf(dev, "failed to register phy usb3-port\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
OF_device_register_xref(OF_xref_from_node(usb3), dev);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
fail:
|
|
|
|
bus_release_resources(dev, rk_typec_phy_spec, &sc->res);
|
|
|
|
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t rk_typec_phy_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, rk_typec_phy_probe),
|
|
|
|
DEVMETHOD(device_attach, rk_typec_phy_attach),
|
|
|
|
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t rk_typec_phy_driver = {
|
|
|
|
"rk_typec_phy",
|
|
|
|
rk_typec_phy_methods,
|
|
|
|
sizeof(struct rk_typec_phy_softc)
|
|
|
|
};
|
|
|
|
|
2022-05-09 21:26:45 +00:00
|
|
|
EARLY_DRIVER_MODULE(rk_typec_phy, simplebus, rk_typec_phy_driver, 0, 0,
|
|
|
|
BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
|
2019-10-25 18:10:02 +00:00
|
|
|
MODULE_VERSION(rk_typec_phy, 1);
|