2015-06-12 13:16:50 +00:00
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/*-
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2020-01-24 16:08:06 +00:00
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* Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com>
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2015-06-12 13:16:50 +00:00
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* Copyright (c) 2014 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Generic ECAM PCIe driver */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2016-02-24 06:05:30 +00:00
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#include "opt_platform.h"
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2015-06-12 13:16:50 +00:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/rman.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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2015-12-14 17:08:40 +00:00
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2015-06-12 13:16:50 +00:00
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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2016-02-24 06:05:30 +00:00
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#include <dev/pci/pci_host_generic.h>
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2015-12-14 17:08:40 +00:00
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2015-06-12 13:16:50 +00:00
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include "pcib_if.h"
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/* Forward prototypes */
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static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes);
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static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes);
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static int generic_pcie_maxslots(device_t dev);
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static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result);
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static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
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uintptr_t value);
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2018-07-10 09:49:27 +00:00
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2016-02-24 06:05:30 +00:00
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int
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2016-11-21 18:24:05 +00:00
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pci_host_generic_core_attach(device_t dev)
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2015-06-12 13:16:50 +00:00
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{
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2016-11-21 18:24:05 +00:00
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struct generic_pcie_core_softc *sc;
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2015-06-12 13:16:50 +00:00
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int error;
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int rid;
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sc = device_get_softc(dev);
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sc->dev = dev;
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2016-05-31 09:15:21 +00:00
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/* Create the parent DMA tag to pass down the coherent flag */
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error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
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1, 0, /* alignment, bounds */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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BUS_SPACE_MAXSIZE, /* maxsize */
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BUS_SPACE_UNRESTRICTED, /* nsegments */
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BUS_SPACE_MAXSIZE, /* maxsegsize */
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sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->dmat);
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if (error != 0)
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return (error);
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2015-06-12 13:16:50 +00:00
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rid = 0;
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2018-11-19 03:34:15 +00:00
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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2015-06-12 13:16:50 +00:00
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if (sc->res == NULL) {
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device_printf(dev, "could not map memory.\n");
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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sc->mem_rman.rm_type = RMAN_ARRAY;
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sc->mem_rman.rm_descr = "PCIe Memory";
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sc->io_rman.rm_type = RMAN_ARRAY;
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sc->io_rman.rm_descr = "PCIe IO window";
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/* Initialize rman and allocate memory regions */
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error = rman_init(&sc->mem_rman);
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if (error) {
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device_printf(dev, "rman_init() failed. error = %d\n", error);
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return (error);
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}
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error = rman_init(&sc->io_rman);
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if (error) {
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device_printf(dev, "rman_init() failed. error = %d\n", error);
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return (error);
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}
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return (0);
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}
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static uint32_t
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generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes)
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{
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2016-11-21 18:24:05 +00:00
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struct generic_pcie_core_softc *sc;
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2015-06-12 13:16:50 +00:00
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint64_t offset;
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uint32_t data;
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sc = device_get_softc(dev);
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2018-11-19 02:55:18 +00:00
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if ((bus < sc->bus_start) || (bus > sc->bus_end))
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return (~0U);
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if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
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(reg > PCIE_REGMAX))
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return (~0U);
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2015-06-12 13:16:50 +00:00
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2018-11-19 02:55:18 +00:00
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offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
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2015-06-12 13:16:50 +00:00
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t = sc->bst;
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h = sc->bsh;
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switch (bytes) {
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case 1:
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data = bus_space_read_1(t, h, offset);
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break;
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case 2:
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data = le16toh(bus_space_read_2(t, h, offset));
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break;
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case 4:
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data = le32toh(bus_space_read_4(t, h, offset));
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break;
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default:
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return (~0U);
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}
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return (data);
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}
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static void
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generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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2016-11-21 18:24:05 +00:00
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struct generic_pcie_core_softc *sc;
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2015-06-12 13:16:50 +00:00
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bus_space_handle_t h;
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bus_space_tag_t t;
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uint64_t offset;
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sc = device_get_softc(dev);
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2018-11-19 02:55:18 +00:00
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if ((bus < sc->bus_start) || (bus > sc->bus_end))
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return;
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if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
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(reg > PCIE_REGMAX))
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return;
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2015-06-12 13:16:50 +00:00
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2018-11-19 02:55:18 +00:00
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offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
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2015-06-12 13:16:50 +00:00
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t = sc->bst;
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h = sc->bsh;
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switch (bytes) {
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case 1:
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bus_space_write_1(t, h, offset, val);
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break;
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case 2:
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bus_space_write_2(t, h, offset, htole16(val));
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break;
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case 4:
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bus_space_write_4(t, h, offset, htole32(val));
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break;
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default:
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return;
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}
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}
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static int
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generic_pcie_maxslots(device_t dev)
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{
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return (31); /* max slots per bus acc. to standard */
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}
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static int
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generic_pcie_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result)
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{
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2016-11-21 18:24:05 +00:00
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struct generic_pcie_core_softc *sc;
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2015-06-12 13:16:50 +00:00
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sc = device_get_softc(dev);
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if (index == PCIB_IVAR_BUS) {
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2018-11-19 02:55:18 +00:00
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*result = sc->bus_start;
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2015-06-12 13:16:50 +00:00
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return (0);
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}
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if (index == PCIB_IVAR_DOMAIN) {
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*result = sc->ecam;
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return (0);
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}
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2016-02-24 06:05:30 +00:00
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if (bootverbose)
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device_printf(dev, "ERROR: Unknown index %d.\n", index);
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2015-06-12 13:16:50 +00:00
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return (ENOENT);
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}
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static int
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generic_pcie_write_ivar(device_t dev, device_t child, int index,
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uintptr_t value)
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{
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return (ENOENT);
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}
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static struct rman *
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2016-11-21 18:24:05 +00:00
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generic_pcie_rman(struct generic_pcie_core_softc *sc, int type)
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2015-06-12 13:16:50 +00:00
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{
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switch (type) {
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case SYS_RES_IOPORT:
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return (&sc->io_rman);
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case SYS_RES_MEMORY:
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return (&sc->mem_rman);
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default:
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break;
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}
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return (NULL);
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}
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2016-11-21 18:24:05 +00:00
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int
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pci_host_generic_core_release_resource(device_t dev, device_t child, int type,
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2015-06-12 13:16:50 +00:00
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int rid, struct resource *res)
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{
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2016-11-21 18:24:05 +00:00
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struct generic_pcie_core_softc *sc;
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2015-06-12 13:16:50 +00:00
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struct rman *rm;
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sc = device_get_softc(dev);
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2016-11-21 18:24:05 +00:00
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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if (type == PCI_RES_BUS) {
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return (pci_domain_release_bus(sc->ecam, child, rid, res));
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}
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#endif
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2015-06-12 13:16:50 +00:00
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rm = generic_pcie_rman(sc, type);
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if (rm != NULL) {
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KASSERT(rman_is_region_manager(res, rm), ("rman mismatch"));
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rman_release_resource(res);
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}
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return (bus_generic_release_resource(dev, child, type, rid, res));
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}
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2016-11-21 18:24:05 +00:00
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struct resource *
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pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type,
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int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
|
2016-02-24 06:05:30 +00:00
|
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{
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2016-11-21 18:24:05 +00:00
|
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struct generic_pcie_core_softc *sc;
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struct resource *res;
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struct rman *rm;
|
2016-02-24 06:05:30 +00:00
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2016-11-21 18:24:05 +00:00
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sc = device_get_softc(dev);
|
2016-02-24 06:05:30 +00:00
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2016-05-20 08:29:00 +00:00
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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if (type == PCI_RES_BUS) {
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return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end,
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count, flags));
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}
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#endif
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2015-06-12 13:16:50 +00:00
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rm = generic_pcie_rman(sc, type);
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if (rm == NULL)
|
2018-11-19 02:43:34 +00:00
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return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
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2015-06-12 13:16:50 +00:00
|
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type, rid, start, end, count, flags));
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if (bootverbose) {
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device_printf(dev,
|
2016-03-18 19:36:43 +00:00
|
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"rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n",
|
2015-06-12 13:16:50 +00:00
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start, end, count);
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}
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res = rman_reserve_resource(rm, start, end, count, flags, child);
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if (res == NULL)
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goto fail;
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rman_set_rid(res, *rid);
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if (flags & RF_ACTIVE)
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if (bus_activate_resource(child, type, *rid, res)) {
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rman_release_resource(res);
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goto fail;
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}
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return (res);
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fail:
|
2016-02-24 06:05:30 +00:00
|
|
|
device_printf(dev, "%s FAIL: type=%d, rid=%d, "
|
2016-03-18 19:36:43 +00:00
|
|
|
"start=%016jx, end=%016jx, count=%016jx, flags=%x\n",
|
2016-02-24 06:05:30 +00:00
|
|
|
__func__, type, *rid, start, end, count, flags);
|
2015-06-12 13:16:50 +00:00
|
|
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|
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return (NULL);
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|
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}
|
|
|
|
|
2018-11-19 03:43:10 +00:00
|
|
|
static int
|
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|
|
generic_pcie_activate_resource(device_t dev, device_t child, int type,
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|
|
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int rid, struct resource *r)
|
|
|
|
{
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|
|
struct generic_pcie_core_softc *sc;
|
|
|
|
uint64_t phys_base;
|
|
|
|
uint64_t pci_base;
|
|
|
|
uint64_t size;
|
|
|
|
int found;
|
|
|
|
int res;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
if ((res = rman_activate_resource(r)) != 0)
|
|
|
|
return (res);
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case SYS_RES_IOPORT:
|
2019-05-17 17:05:16 +00:00
|
|
|
case SYS_RES_MEMORY:
|
2018-11-19 03:43:10 +00:00
|
|
|
found = 0;
|
|
|
|
for (i = 0; i < MAX_RANGES_TUPLES; i++) {
|
|
|
|
pci_base = sc->ranges[i].pci_base;
|
|
|
|
phys_base = sc->ranges[i].phys_base;
|
|
|
|
size = sc->ranges[i].size;
|
|
|
|
|
2019-05-17 17:05:16 +00:00
|
|
|
if ((rman_get_start(r) >= pci_base) && (rman_get_start(r) < (pci_base + size))) {
|
2018-11-19 03:43:10 +00:00
|
|
|
found = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (found) {
|
2019-05-17 17:05:16 +00:00
|
|
|
rman_set_start(r, rman_get_start(r) - pci_base + phys_base);
|
|
|
|
rman_set_end(r, rman_get_end(r) - pci_base + phys_base);
|
2018-11-19 03:43:10 +00:00
|
|
|
res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev),
|
|
|
|
child, type, rid, r);
|
|
|
|
} else {
|
|
|
|
device_printf(dev,
|
2019-05-17 17:05:16 +00:00
|
|
|
"Failed to activate %s resource\n",
|
|
|
|
type == SYS_RES_IOPORT ? "IOPORT" : "MEMORY");
|
2019-09-05 15:45:21 +00:00
|
|
|
res = ENXIO;
|
2018-11-19 03:43:10 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SYS_RES_IRQ:
|
|
|
|
res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
|
|
|
|
type, rid, r);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (res);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
generic_pcie_deactivate_resource(device_t dev, device_t child, int type,
|
|
|
|
int rid, struct resource *r)
|
|
|
|
{
|
|
|
|
int res;
|
|
|
|
|
|
|
|
if ((res = rman_deactivate_resource(r)) != 0)
|
|
|
|
return (res);
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case SYS_RES_IOPORT:
|
|
|
|
case SYS_RES_MEMORY:
|
|
|
|
case SYS_RES_IRQ:
|
|
|
|
res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
|
|
|
|
type, rid, r);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (res);
|
|
|
|
}
|
|
|
|
|
2015-06-12 13:16:50 +00:00
|
|
|
static int
|
|
|
|
generic_pcie_adjust_resource(device_t dev, device_t child, int type,
|
2016-01-27 02:23:54 +00:00
|
|
|
struct resource *res, rman_res_t start, rman_res_t end)
|
2015-06-12 13:16:50 +00:00
|
|
|
{
|
2016-11-21 18:24:05 +00:00
|
|
|
struct generic_pcie_core_softc *sc;
|
2015-06-12 13:16:50 +00:00
|
|
|
struct rman *rm;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2016-05-20 08:29:00 +00:00
|
|
|
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
|
|
|
|
if (type == PCI_RES_BUS)
|
|
|
|
return (pci_domain_adjust_bus(sc->ecam, child, res, start,
|
|
|
|
end));
|
|
|
|
#endif
|
2015-06-12 13:16:50 +00:00
|
|
|
|
|
|
|
rm = generic_pcie_rman(sc, type);
|
|
|
|
if (rm != NULL)
|
|
|
|
return (rman_adjust_resource(res, start, end));
|
|
|
|
return (bus_generic_adjust_resource(dev, child, type, res, start, end));
|
|
|
|
}
|
|
|
|
|
2016-05-31 09:15:21 +00:00
|
|
|
static bus_dma_tag_t
|
|
|
|
generic_pcie_get_dma_tag(device_t dev, device_t child)
|
|
|
|
{
|
2016-11-21 18:24:05 +00:00
|
|
|
struct generic_pcie_core_softc *sc;
|
2016-05-31 09:15:21 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
return (sc->dmat);
|
|
|
|
}
|
|
|
|
|
2015-06-12 13:16:50 +00:00
|
|
|
static device_method_t generic_pcie_methods[] = {
|
2016-11-21 18:24:05 +00:00
|
|
|
DEVMETHOD(device_attach, pci_host_generic_core_attach),
|
2015-06-12 13:16:50 +00:00
|
|
|
DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar),
|
|
|
|
DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar),
|
2016-11-21 18:24:05 +00:00
|
|
|
DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource),
|
2015-06-12 13:16:50 +00:00
|
|
|
DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource),
|
2018-11-19 03:43:10 +00:00
|
|
|
DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource),
|
|
|
|
DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource),
|
2016-11-21 18:24:05 +00:00
|
|
|
DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource),
|
2015-06-12 13:16:50 +00:00
|
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
2015-12-14 17:08:40 +00:00
|
|
|
|
2016-05-31 09:15:21 +00:00
|
|
|
DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag),
|
|
|
|
|
2015-12-14 17:08:40 +00:00
|
|
|
/* pcib interface */
|
2015-06-12 13:16:50 +00:00
|
|
|
DEVMETHOD(pcib_maxslots, generic_pcie_maxslots),
|
|
|
|
DEVMETHOD(pcib_read_config, generic_pcie_read_config),
|
|
|
|
DEVMETHOD(pcib_write_config, generic_pcie_write_config),
|
2016-02-24 06:05:30 +00:00
|
|
|
|
2015-06-12 13:16:50 +00:00
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
2016-11-21 18:24:05 +00:00
|
|
|
DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
|
|
|
|
generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
|