2011-02-20 12:57:14 +00:00
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//===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// LiveIntervalUnion represents a coalesced set of live intervals. This may be
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// used during coalescing to represent a congruence class, or during register
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// allocation to model liveness of a physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveIntervalUnion.h"
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#include "llvm/ADT/SparseBitVector.h"
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#include "llvm/CodeGen/MachineLoopRanges.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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// Merge a LiveInterval's segments. Guarantee no overlaps.
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void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
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if (VirtReg.empty())
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return;
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++Tag;
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// Insert each of the virtual register's live segments into the map.
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LiveInterval::iterator RegPos = VirtReg.begin();
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LiveInterval::iterator RegEnd = VirtReg.end();
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SegmentIter SegPos = Segments.find(RegPos->start);
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2011-05-02 19:34:44 +00:00
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while (SegPos.valid()) {
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2011-02-20 12:57:14 +00:00
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SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
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if (++RegPos == RegEnd)
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return;
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SegPos.advanceTo(RegPos->start);
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}
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2011-05-02 19:34:44 +00:00
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// We have reached the end of Segments, so it is no longer necessary to search
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// for the insertion position.
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// It is faster to insert the end first.
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--RegEnd;
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SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
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for (; RegPos != RegEnd; ++RegPos, ++SegPos)
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SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
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2011-02-20 12:57:14 +00:00
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}
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// Remove a live virtual register's segments from this union.
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void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
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if (VirtReg.empty())
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return;
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++Tag;
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// Remove each of the virtual register's live segments from the map.
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LiveInterval::iterator RegPos = VirtReg.begin();
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LiveInterval::iterator RegEnd = VirtReg.end();
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SegmentIter SegPos = Segments.find(RegPos->start);
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for (;;) {
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assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
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SegPos.erase();
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if (!SegPos.valid())
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return;
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// Skip all segments that may have been coalesced.
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RegPos = VirtReg.advanceTo(RegPos, SegPos.start());
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if (RegPos == RegEnd)
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return;
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SegPos.advanceTo(RegPos->start);
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}
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}
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void
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LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
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OS << "LIU " << PrintReg(RepReg, TRI);
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if (empty()) {
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OS << " empty\n";
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return;
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}
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for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
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OS << " [" << SI.start() << ' ' << SI.stop() << "):"
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<< PrintReg(SI.value()->reg, TRI);
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}
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OS << '\n';
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}
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void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
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const TargetRegisterInfo *TRI) const {
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OS << '[' << start() << ';' << stop() << "):"
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<< PrintReg(interference()->reg, TRI);
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}
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void LiveIntervalUnion::Query::print(raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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OS << "Interferences with ";
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LiveUnion->print(OS, TRI);
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InterferenceResult IR = firstInterference();
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while (isInterference(IR)) {
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OS << " ";
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IR.print(OS, TRI);
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OS << '\n';
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nextInterference(IR);
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}
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}
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#ifndef NDEBUG
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// Verify the live intervals in this union and add them to the visited set.
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void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
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for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
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VisitedVRegs.set(SI.value()->reg);
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}
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#endif //!NDEBUG
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// Private interface accessed by Query.
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//
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// Find a pair of segments that intersect, one in the live virtual register
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// (LiveInterval), and the other in this LiveIntervalUnion. The caller (Query)
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// is responsible for advancing the LiveIntervalUnion segments to find a
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// "notable" intersection, which requires query-specific logic.
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//
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// This design assumes only a fast mechanism for intersecting a single live
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// virtual register segment with a set of LiveIntervalUnion segments. This may
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// be ok since most virtual registers have very few segments. If we had a data
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// structure that optimizd MxN intersection of segments, then we would bypass
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// the loop that advances within the LiveInterval.
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//
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// If no intersection exists, set VirtRegI = VirtRegEnd, and set SI to the first
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// segment whose start point is greater than LiveInterval's end point.
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//
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// Assumes that segments are sorted by start position in both
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// LiveInterval and LiveSegments.
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void LiveIntervalUnion::Query::findIntersection(InterferenceResult &IR) const {
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// Search until reaching the end of the LiveUnion segments.
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LiveInterval::iterator VirtRegEnd = VirtReg->end();
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if (IR.VirtRegI == VirtRegEnd)
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return;
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while (IR.LiveUnionI.valid()) {
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// Slowly advance the live virtual reg iterator until we surpass the next
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// segment in LiveUnion.
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//
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// Note: If this is ever used for coalescing of fixed registers and we have
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// a live vreg with thousands of segments, then change this code to use
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// upperBound instead.
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IR.VirtRegI = VirtReg->advanceTo(IR.VirtRegI, IR.LiveUnionI.start());
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if (IR.VirtRegI == VirtRegEnd)
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break; // Retain current (nonoverlapping) LiveUnionI
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// VirtRegI may have advanced far beyond LiveUnionI, catch up.
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IR.LiveUnionI.advanceTo(IR.VirtRegI->start);
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// Check if no LiveUnionI exists with VirtRegI->Start < LiveUnionI.end
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if (!IR.LiveUnionI.valid())
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break;
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if (IR.LiveUnionI.start() < IR.VirtRegI->end) {
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assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
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"upperBound postcondition");
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break;
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}
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}
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if (!IR.LiveUnionI.valid())
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IR.VirtRegI = VirtRegEnd;
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}
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// Find the first intersection, and cache interference info
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// (retain segment iterators into both VirtReg and LiveUnion).
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const LiveIntervalUnion::InterferenceResult &
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LiveIntervalUnion::Query::firstInterference() {
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if (CheckedFirstInterference)
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return FirstInterference;
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CheckedFirstInterference = true;
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InterferenceResult &IR = FirstInterference;
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2011-05-02 19:34:44 +00:00
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IR.LiveUnionI.setMap(LiveUnion->getMap());
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2011-02-20 12:57:14 +00:00
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// Quickly skip interference check for empty sets.
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if (VirtReg->empty() || LiveUnion->empty()) {
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IR.VirtRegI = VirtReg->end();
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} else if (VirtReg->beginIndex() < LiveUnion->startIndex()) {
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// VirtReg starts first, perform double binary search.
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IR.VirtRegI = VirtReg->find(LiveUnion->startIndex());
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if (IR.VirtRegI != VirtReg->end())
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2011-05-02 19:34:44 +00:00
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IR.LiveUnionI.find(IR.VirtRegI->start);
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2011-02-20 12:57:14 +00:00
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} else {
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// LiveUnion starts first, perform double binary search.
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2011-05-02 19:34:44 +00:00
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IR.LiveUnionI.find(VirtReg->beginIndex());
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2011-02-20 12:57:14 +00:00
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if (IR.LiveUnionI.valid())
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IR.VirtRegI = VirtReg->find(IR.LiveUnionI.start());
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else
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IR.VirtRegI = VirtReg->end();
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}
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findIntersection(FirstInterference);
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assert((IR.VirtRegI == VirtReg->end() || IR.LiveUnionI.valid())
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&& "Uninitialized iterator");
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return FirstInterference;
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}
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// Treat the result as an iterator and advance to the next interfering pair
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// of segments. This is a plain iterator with no filter.
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bool LiveIntervalUnion::Query::nextInterference(InterferenceResult &IR) const {
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assert(isInterference(IR) && "iteration past end of interferences");
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// Advance either the VirtReg or LiveUnion segment to ensure that we visit all
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// unique overlapping pairs.
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if (IR.VirtRegI->end < IR.LiveUnionI.stop()) {
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if (++IR.VirtRegI == VirtReg->end())
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return false;
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}
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else {
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if (!(++IR.LiveUnionI).valid()) {
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IR.VirtRegI = VirtReg->end();
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return false;
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}
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}
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// Short-circuit findIntersection() if possible.
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if (overlap(*IR.VirtRegI, IR.LiveUnionI))
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return true;
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// Find the next intersection.
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findIntersection(IR);
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return isInterference(IR);
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}
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// Scan the vector of interfering virtual registers in this union. Assume it's
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// quite small.
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bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
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SmallVectorImpl<LiveInterval*>::const_iterator I =
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std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
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return I != InterferingVRegs.end();
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}
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// Count the number of virtual registers in this union that interfere with this
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// query's live virtual register.
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//
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// The number of times that we either advance IR.VirtRegI or call
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// LiveUnion.upperBound() will be no more than the number of holes in
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// VirtReg. So each invocation of collectInterferingVRegs() takes
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// time proportional to |VirtReg Holes| * time(LiveUnion.upperBound()).
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//
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// For comments on how to speed it up, see Query::findIntersection().
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unsigned LiveIntervalUnion::Query::
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2011-07-17 15:36:56 +00:00
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collectInterferingVRegs(unsigned MaxInterferingRegs) {
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2011-02-20 12:57:14 +00:00
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InterferenceResult IR = firstInterference();
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LiveInterval::iterator VirtRegEnd = VirtReg->end();
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LiveInterval *RecentInterferingVReg = NULL;
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if (IR.VirtRegI != VirtRegEnd) while (IR.LiveUnionI.valid()) {
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// Advance the union's iterator to reach an unseen interfering vreg.
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do {
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if (IR.LiveUnionI.value() == RecentInterferingVReg)
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continue;
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if (!isSeenInterference(IR.LiveUnionI.value()))
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break;
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// Cache the most recent interfering vreg to bypass isSeenInterference.
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RecentInterferingVReg = IR.LiveUnionI.value();
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} while ((++IR.LiveUnionI).valid());
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if (!IR.LiveUnionI.valid())
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break;
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// Advance the VirtReg iterator until surpassing the next segment in
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// LiveUnion.
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IR.VirtRegI = VirtReg->advanceTo(IR.VirtRegI, IR.LiveUnionI.start());
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if (IR.VirtRegI == VirtRegEnd)
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break;
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// Check for intersection with the union's segment.
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if (overlap(*IR.VirtRegI, IR.LiveUnionI)) {
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if (!IR.LiveUnionI.value()->isSpillable())
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SeenUnspillableVReg = true;
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if (InterferingVRegs.size() == MaxInterferingRegs)
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// Leave SeenAllInterferences set to false to indicate that at least one
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// interference exists beyond those we collected.
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return MaxInterferingRegs;
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InterferingVRegs.push_back(IR.LiveUnionI.value());
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// Cache the most recent interfering vreg to bypass isSeenInterference.
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RecentInterferingVReg = IR.LiveUnionI.value();
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++IR.LiveUnionI;
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2011-05-02 19:34:44 +00:00
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2011-02-20 12:57:14 +00:00
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continue;
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}
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// VirtRegI may have advanced far beyond LiveUnionI,
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// do a fast intersection test to "catch up"
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IR.LiveUnionI.advanceTo(IR.VirtRegI->start);
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}
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SeenAllInterferences = true;
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return InterferingVRegs.size();
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}
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bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
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// VirtReg is likely live throughout the loop, so start by checking LIU-Loop
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// overlaps.
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IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
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Overlaps(LiveUnion->getMap(), Loop->getMap());
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if (!Overlaps.valid())
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return false;
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// The loop is overlapping an LIU assignment. Check VirtReg as well.
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LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
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for (;;) {
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if (VRI == VirtReg->end())
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return false;
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if (VRI->start < Overlaps.stop())
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return true;
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Overlaps.advanceTo(VRI->start);
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if (!Overlaps.valid())
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return false;
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if (Overlaps.start() < VRI->end)
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return true;
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VRI = VirtReg->advanceTo(VRI, Overlaps.start());
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}
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}
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