2012-05-17 10:11:18 +00:00
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/*-
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* Copyright (C) 2009-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/kthread.h>
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#include <sys/unistd.h>
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#include <dev/nand/nand.h>
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#include <dev/nand/nandsim_chip.h>
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#include <dev/nand/nandsim_log.h>
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#include <dev/nand/nandsim_swap.h>
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MALLOC_DEFINE(M_NANDSIM, "NANDsim", "NANDsim dynamic data");
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#define NANDSIM_CHIP_LOCK(chip) mtx_lock(&(chip)->ns_lock)
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#define NANDSIM_CHIP_UNLOCK(chip) mtx_unlock(&(chip)->ns_lock)
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static nandsim_evh_t erase_evh;
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static nandsim_evh_t idle_evh;
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static nandsim_evh_t poweron_evh;
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static nandsim_evh_t reset_evh;
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static nandsim_evh_t read_evh;
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static nandsim_evh_t readid_evh;
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static nandsim_evh_t readparam_evh;
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static nandsim_evh_t write_evh;
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static void nandsim_loop(void *);
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static void nandsim_undefined(struct nandsim_chip *, uint8_t);
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static void nandsim_bad_address(struct nandsim_chip *, uint8_t *);
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static void nandsim_ignore_address(struct nandsim_chip *, uint8_t);
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static void nandsim_sm_error(struct nandsim_chip *);
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static void nandsim_start_handler(struct nandsim_chip *, nandsim_evh_t);
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static void nandsim_callout_eh(void *);
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static int nandsim_delay(struct nandsim_chip *, int);
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static int nandsim_bbm_init(struct nandsim_chip *, uint32_t, uint32_t *);
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static int nandsim_blk_state_init(struct nandsim_chip *, uint32_t, uint32_t);
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static void nandsim_blk_state_destroy(struct nandsim_chip *);
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static int nandchip_is_block_valid(struct nandsim_chip *, int);
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static void nandchip_set_status(struct nandsim_chip *, uint8_t);
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static void nandchip_clear_status(struct nandsim_chip *, uint8_t);
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struct proc *nandsim_proc;
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struct nandsim_chip *
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nandsim_chip_init(struct nandsim_softc* sc, uint8_t chip_num,
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struct sim_chip *sim_chip)
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{
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struct nandsim_chip *chip;
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struct onfi_params *chip_param;
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char swapfile[20];
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uint32_t size;
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int error;
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chip = malloc(sizeof(*chip), M_NANDSIM, M_WAITOK | M_ZERO);
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mtx_init(&chip->ns_lock, "nandsim lock", NULL, MTX_DEF);
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2015-05-22 17:05:21 +00:00
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callout_init(&chip->ns_callout, 1);
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2012-05-17 10:11:18 +00:00
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STAILQ_INIT(&chip->nandsim_events);
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chip->chip_num = chip_num;
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chip->ctrl_num = sim_chip->ctrl_num;
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chip->sc = sc;
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if (!sim_chip->is_wp)
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nandchip_set_status(chip, NAND_STATUS_WP);
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chip_param = &chip->params;
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chip->id.dev_id = sim_chip->device_id;
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chip->id.man_id = sim_chip->manufact_id;
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chip->error_ratio = sim_chip->error_ratio;
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chip->wear_level = sim_chip->wear_level;
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chip->prog_delay = sim_chip->prog_time;
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chip->erase_delay = sim_chip->erase_time;
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chip->read_delay = sim_chip->read_time;
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chip_param->t_prog = sim_chip->prog_time;
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chip_param->t_bers = sim_chip->erase_time;
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chip_param->t_r = sim_chip->read_time;
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bcopy("onfi", &chip_param->signature, 4);
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chip_param->manufacturer_id = sim_chip->manufact_id;
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strncpy(chip_param->manufacturer_name, sim_chip->manufacturer, 12);
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chip_param->manufacturer_name[11] = 0;
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strncpy(chip_param->device_model, sim_chip->device_model, 20);
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chip_param->device_model[19] = 0;
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chip_param->bytes_per_page = sim_chip->page_size;
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chip_param->spare_bytes_per_page = sim_chip->oob_size;
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chip_param->pages_per_block = sim_chip->pgs_per_blk;
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chip_param->blocks_per_lun = sim_chip->blks_per_lun;
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chip_param->luns = sim_chip->luns;
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init_chip_geom(&chip->cg, chip_param->luns, chip_param->blocks_per_lun,
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chip_param->pages_per_block, chip_param->bytes_per_page,
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chip_param->spare_bytes_per_page);
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chip_param->address_cycles = sim_chip->row_addr_cycles |
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(sim_chip->col_addr_cycles << 4);
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chip_param->features = sim_chip->features;
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if (sim_chip->width == 16)
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chip_param->features |= ONFI_FEAT_16BIT;
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size = chip_param->blocks_per_lun * chip_param->luns;
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error = nandsim_blk_state_init(chip, size, sim_chip->wear_level);
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if (error) {
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mtx_destroy(&chip->ns_lock);
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free(chip, M_NANDSIM);
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return (NULL);
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}
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error = nandsim_bbm_init(chip, size, sim_chip->bad_block_map);
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if (error) {
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mtx_destroy(&chip->ns_lock);
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nandsim_blk_state_destroy(chip);
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free(chip, M_NANDSIM);
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return (NULL);
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}
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nandsim_start_handler(chip, poweron_evh);
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nand_debug(NDBG_SIM,"Create thread for chip%d [%8p]", chip->chip_num,
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chip);
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/* Create chip thread */
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error = kproc_kthread_add(nandsim_loop, chip, &nandsim_proc,
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&chip->nandsim_td, RFSTOPPED | RFHIGHPID,
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0, "nandsim", "chip");
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if (error) {
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mtx_destroy(&chip->ns_lock);
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nandsim_blk_state_destroy(chip);
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free(chip, M_NANDSIM);
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return (NULL);
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}
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thread_lock(chip->nandsim_td);
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sched_class(chip->nandsim_td, PRI_REALTIME);
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sched_add(chip->nandsim_td, SRQ_BORING);
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thread_unlock(chip->nandsim_td);
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size = (chip_param->bytes_per_page +
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chip_param->spare_bytes_per_page) *
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chip_param->pages_per_block;
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sprintf(swapfile, "chip%d%d.swp", chip->ctrl_num, chip->chip_num);
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chip->swap = nandsim_swap_init(swapfile, chip_param->blocks_per_lun *
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chip_param->luns, size);
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if (!chip->swap)
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nandsim_chip_destroy(chip);
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/* Wait for new thread to enter main loop */
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tsleep(chip->nandsim_td, PWAIT, "ns_chip", 1 * hz);
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return (chip);
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}
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static int
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nandsim_blk_state_init(struct nandsim_chip *chip, uint32_t size,
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uint32_t wear_lev)
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{
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int i;
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if (!chip || size == 0)
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return (-1);
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chip->blk_state = malloc(size * sizeof(struct nandsim_block_state),
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M_NANDSIM, M_WAITOK | M_ZERO);
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for (i = 0; i < size; i++) {
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if (wear_lev)
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chip->blk_state[i].wear_lev = wear_lev;
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else
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chip->blk_state[i].wear_lev = -1;
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}
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return (0);
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}
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static void
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nandsim_blk_state_destroy(struct nandsim_chip *chip)
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{
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if (chip && chip->blk_state)
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free(chip->blk_state, M_NANDSIM);
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}
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static int
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nandsim_bbm_init(struct nandsim_chip *chip, uint32_t size,
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uint32_t *sim_bbm)
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{
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uint32_t index;
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int i;
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if ((chip == NULL) || (size == 0))
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return (-1);
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if (chip->blk_state == NULL)
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return (-1);
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if (sim_bbm == NULL)
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return (0);
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for (i = 0; i < MAX_BAD_BLOCKS; i++) {
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index = sim_bbm[i];
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if (index == 0xffffffff)
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break;
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else if (index > size)
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return (-1);
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else
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chip->blk_state[index].is_bad = 1;
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}
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return (0);
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}
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void
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nandsim_chip_destroy(struct nandsim_chip *chip)
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{
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struct nandsim_ev *ev;
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ev = create_event(chip, NANDSIM_EV_EXIT, 0);
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if (ev)
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send_event(ev);
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}
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void
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nandsim_chip_freeze(struct nandsim_chip *chip)
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{
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chip->flags |= NANDSIM_CHIP_FROZEN;
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}
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static void
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nandsim_loop(void *arg)
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{
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struct nandsim_chip *chip = (struct nandsim_chip *)arg;
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struct nandsim_ev *ev;
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nand_debug(NDBG_SIM,"Start main loop for chip%d [%8p]", chip->chip_num,
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chip);
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for(;;) {
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NANDSIM_CHIP_LOCK(chip);
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if (!(chip->flags & NANDSIM_CHIP_ACTIVE)) {
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chip->flags |= NANDSIM_CHIP_ACTIVE;
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wakeup(chip->nandsim_td);
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}
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if (STAILQ_EMPTY(&chip->nandsim_events)) {
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nand_debug(NDBG_SIM,"Chip%d [%8p] going sleep",
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chip->chip_num, chip);
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msleep(chip, &chip->ns_lock, PRIBIO, "nandev", 0);
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}
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ev = STAILQ_FIRST(&chip->nandsim_events);
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STAILQ_REMOVE_HEAD(&chip->nandsim_events, links);
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NANDSIM_CHIP_UNLOCK(chip);
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if (ev->type == NANDSIM_EV_EXIT) {
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NANDSIM_CHIP_LOCK(chip);
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destroy_event(ev);
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wakeup(ev);
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while (!STAILQ_EMPTY(&chip->nandsim_events)) {
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ev = STAILQ_FIRST(&chip->nandsim_events);
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STAILQ_REMOVE_HEAD(&chip->nandsim_events,
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links);
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destroy_event(ev);
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wakeup(ev);
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2016-04-10 23:07:00 +00:00
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}
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2012-05-17 10:11:18 +00:00
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NANDSIM_CHIP_UNLOCK(chip);
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nandsim_log(chip, NANDSIM_LOG_SM, "destroyed\n");
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mtx_destroy(&chip->ns_lock);
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nandsim_blk_state_destroy(chip);
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nandsim_swap_destroy(chip->swap);
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free(chip, M_NANDSIM);
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nandsim_proc = NULL;
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kthread_exit();
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}
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if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
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nand_debug(NDBG_SIM,"Chip [%x] get event [%x]",
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chip->chip_num, ev->type);
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chip->ev_handler(chip, ev->type, ev->data);
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}
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wakeup(ev);
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destroy_event(ev);
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}
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}
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struct nandsim_ev *
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create_event(struct nandsim_chip *chip, uint8_t type, uint8_t data_size)
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{
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struct nandsim_ev *ev;
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ev = malloc(sizeof(*ev), M_NANDSIM, M_NOWAIT | M_ZERO);
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if (!ev) {
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nand_debug(NDBG_SIM,"Cannot create event");
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return (NULL);
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}
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if (data_size > 0)
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ev->data = malloc(sizeof(*ev), M_NANDSIM, M_NOWAIT | M_ZERO);
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ev->type = type;
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ev->chip = chip;
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return (ev);
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}
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void
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destroy_event(struct nandsim_ev *ev)
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{
|
|
|
|
|
|
|
|
if (ev->data)
|
|
|
|
free(ev->data, M_NANDSIM);
|
|
|
|
free(ev, M_NANDSIM);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
send_event(struct nandsim_ev *ev)
|
|
|
|
{
|
|
|
|
struct nandsim_chip *chip = ev->chip;
|
|
|
|
|
|
|
|
if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
|
|
|
|
nand_debug(NDBG_SIM,"Chip%d [%p] send event %x",
|
|
|
|
chip->chip_num, chip, ev->type);
|
|
|
|
|
|
|
|
NANDSIM_CHIP_LOCK(chip);
|
|
|
|
STAILQ_INSERT_TAIL(&chip->nandsim_events, ev, links);
|
|
|
|
NANDSIM_CHIP_UNLOCK(chip);
|
|
|
|
|
|
|
|
wakeup(chip);
|
|
|
|
if ((ev->type != NANDSIM_EV_TIMEOUT) && chip->nandsim_td &&
|
|
|
|
(curthread != chip->nandsim_td))
|
|
|
|
tsleep(ev, PWAIT, "ns_ev", 5 * hz);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandsim_callout_eh(void *arg)
|
|
|
|
{
|
|
|
|
struct nandsim_ev *ev = (struct nandsim_ev *)arg;
|
|
|
|
|
|
|
|
send_event(ev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nandsim_delay(struct nandsim_chip *chip, int timeout)
|
|
|
|
{
|
|
|
|
struct nandsim_ev *ev;
|
|
|
|
struct timeval delay;
|
|
|
|
int tm;
|
|
|
|
|
|
|
|
nand_debug(NDBG_SIM,"Chip[%d] Set delay: %d", chip->chip_num, timeout);
|
|
|
|
|
|
|
|
ev = create_event(chip, NANDSIM_EV_TIMEOUT, 0);
|
|
|
|
if (!ev)
|
|
|
|
return (-1);
|
|
|
|
|
|
|
|
chip->sm_state = NANDSIM_STATE_TIMEOUT;
|
|
|
|
tm = (timeout/10000) * (hz / 100);
|
|
|
|
if (callout_reset(&chip->ns_callout, tm, nandsim_callout_eh, ev))
|
|
|
|
return (-1);
|
|
|
|
|
|
|
|
delay.tv_sec = chip->read_delay / 1000000;
|
|
|
|
delay.tv_usec = chip->read_delay % 1000000;
|
|
|
|
timevaladd(&chip->delay_tv, &delay);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandsim_start_handler(struct nandsim_chip *chip, nandsim_evh_t evh)
|
|
|
|
{
|
|
|
|
struct nandsim_ev *ev;
|
|
|
|
|
|
|
|
chip->ev_handler = evh;
|
|
|
|
|
|
|
|
nand_debug(NDBG_SIM,"Start handler %p for chip%d [%p]", evh,
|
|
|
|
chip->chip_num, chip);
|
|
|
|
ev = create_event(chip, NANDSIM_EV_START, 0);
|
|
|
|
if (!ev)
|
|
|
|
nandsim_sm_error(chip);
|
|
|
|
|
|
|
|
send_event(ev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandchip_set_data(struct nandsim_chip *chip, uint8_t *data, uint32_t len,
|
|
|
|
uint32_t idx)
|
|
|
|
{
|
|
|
|
|
|
|
|
nand_debug(NDBG_SIM,"Chip [%x] data %p [%x] at %x", chip->chip_num,
|
|
|
|
data, len, idx);
|
|
|
|
chip->data.data_ptr = data;
|
|
|
|
chip->data.size = len;
|
|
|
|
chip->data.index = idx;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nandchip_chip_space(struct nandsim_chip *chip, int32_t row, int32_t column,
|
|
|
|
size_t size, uint8_t writing)
|
|
|
|
{
|
|
|
|
struct block_space *blk_space;
|
|
|
|
uint32_t lun, block, page, offset, block_size;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
block_size = chip->cg.block_size +
|
|
|
|
(chip->cg.oob_size * chip->cg.pgs_per_blk);
|
|
|
|
|
|
|
|
err = nand_row_to_blkpg(&chip->cg, row, &lun, &block, &page);
|
|
|
|
if (err) {
|
|
|
|
nand_debug(NDBG_SIM,"cannot get address\n");
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!nandchip_is_block_valid(chip, block)) {
|
|
|
|
nandchip_set_data(chip, NULL, 0, 0);
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
blk_space = get_bs(chip->swap, block, writing);
|
|
|
|
if (!blk_space) {
|
|
|
|
nandchip_set_data(chip, NULL, 0, 0);
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size > block_size)
|
|
|
|
size = block_size;
|
|
|
|
|
|
|
|
if (size == block_size) {
|
|
|
|
offset = 0;
|
|
|
|
column = 0;
|
|
|
|
} else
|
|
|
|
offset = page * (chip->cg.page_size + chip->cg.oob_size);
|
|
|
|
|
|
|
|
nandchip_set_data(chip, &blk_space->blk_ptr[offset], size, column);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nandchip_get_addr_byte(struct nandsim_chip *chip, void *data, uint32_t *value)
|
|
|
|
{
|
|
|
|
int ncycles = 0;
|
|
|
|
uint8_t byte;
|
|
|
|
uint8_t *buffer;
|
|
|
|
|
|
|
|
buffer = (uint8_t *)value;
|
|
|
|
byte = *((uint8_t *)data);
|
|
|
|
|
|
|
|
KASSERT((chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW ||
|
|
|
|
chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL),
|
|
|
|
("unexpected state"));
|
|
|
|
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
|
|
|
|
ncycles = chip->params.address_cycles & 0xf;
|
|
|
|
buffer[chip->sm_addr_cycle++] = byte;
|
|
|
|
} else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
|
|
|
|
ncycles = (chip->params.address_cycles >> 4) & 0xf;
|
|
|
|
buffer[chip->sm_addr_cycle++] = byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
nand_debug(NDBG_SIM, "Chip [%x] read addr byte: %02x (%d of %d)\n",
|
|
|
|
chip->chip_num, byte, chip->sm_addr_cycle, ncycles);
|
|
|
|
|
|
|
|
if (chip->sm_addr_cycle == ncycles) {
|
|
|
|
chip->sm_addr_cycle = 0;
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nandchip_is_block_valid(struct nandsim_chip *chip, int block_num)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (!chip || !chip->blk_state)
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
if (chip->blk_state[block_num].wear_lev == 0 ||
|
|
|
|
chip->blk_state[block_num].is_bad)
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandchip_set_status(struct nandsim_chip *chip, uint8_t flags)
|
|
|
|
{
|
|
|
|
|
|
|
|
chip->chip_status |= flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandchip_clear_status(struct nandsim_chip *chip, uint8_t flags)
|
|
|
|
{
|
|
|
|
|
|
|
|
chip->chip_status &= ~flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t
|
|
|
|
nandchip_get_status(struct nandsim_chip *chip)
|
|
|
|
{
|
|
|
|
return (chip->chip_status);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nandsim_chip_timeout(struct nandsim_chip *chip)
|
|
|
|
{
|
|
|
|
struct timeval tv;
|
|
|
|
|
|
|
|
getmicrotime(&tv);
|
|
|
|
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_TIMEOUT &&
|
|
|
|
timevalcmp(&tv, &chip->delay_tv, >=)) {
|
|
|
|
nandchip_set_status(chip, NAND_STATUS_RDY);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
|
|
poweron_evh(struct nandsim_chip *chip, uint32_t type, void *data)
|
|
|
|
{
|
|
|
|
uint8_t cmd;
|
|
|
|
|
|
|
|
if (type == NANDSIM_EV_START)
|
|
|
|
chip->sm_state = NANDSIM_STATE_IDLE;
|
|
|
|
else if (type == NANDSIM_EV_CMD) {
|
|
|
|
cmd = *(uint8_t *)data;
|
|
|
|
switch(cmd) {
|
|
|
|
case NAND_CMD_RESET:
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
|
|
|
|
nandsim_start_handler(chip, reset_evh);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
idle_evh(struct nandsim_chip *chip, uint32_t type, void *data)
|
|
|
|
{
|
|
|
|
uint8_t cmd;
|
|
|
|
|
|
|
|
if (type == NANDSIM_EV_START) {
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "in IDLE state\n");
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_CMD;
|
|
|
|
} else if (type == NANDSIM_EV_CMD) {
|
|
|
|
nandchip_clear_status(chip, NAND_STATUS_FAIL);
|
|
|
|
getmicrotime(&chip->delay_tv);
|
|
|
|
cmd = *(uint8_t *)data;
|
|
|
|
switch(cmd) {
|
|
|
|
case NAND_CMD_READ_ID:
|
|
|
|
nandsim_start_handler(chip, readid_evh);
|
|
|
|
break;
|
|
|
|
case NAND_CMD_READ_PARAMETER:
|
|
|
|
nandsim_start_handler(chip, readparam_evh);
|
|
|
|
break;
|
|
|
|
case NAND_CMD_READ:
|
|
|
|
nandsim_start_handler(chip, read_evh);
|
|
|
|
break;
|
|
|
|
case NAND_CMD_PROG:
|
|
|
|
nandsim_start_handler(chip, write_evh);
|
|
|
|
break;
|
|
|
|
case NAND_CMD_ERASE:
|
|
|
|
nandsim_start_handler(chip, erase_evh);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
readid_evh(struct nandsim_chip *chip, uint32_t type, void *data)
|
|
|
|
{
|
|
|
|
struct onfi_params *params;
|
|
|
|
uint8_t addr;
|
|
|
|
|
|
|
|
params = &chip->params;
|
|
|
|
|
|
|
|
if (type == NANDSIM_EV_START) {
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "in READID state\n");
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
|
|
|
|
} else if (type == NANDSIM_EV_ADDR) {
|
|
|
|
|
|
|
|
addr = *((uint8_t *)data);
|
|
|
|
|
|
|
|
if (addr == 0x0)
|
|
|
|
nandchip_set_data(chip, (uint8_t *)&chip->id, 2, 0);
|
|
|
|
else if (addr == ONFI_SIG_ADDR)
|
|
|
|
nandchip_set_data(chip, (uint8_t *)¶ms->signature,
|
|
|
|
4, 0);
|
|
|
|
else
|
|
|
|
nandsim_bad_address(chip, &addr);
|
|
|
|
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
readparam_evh(struct nandsim_chip *chip, uint32_t type, void *data)
|
|
|
|
{
|
|
|
|
struct onfi_params *params;
|
|
|
|
uint8_t addr;
|
|
|
|
|
|
|
|
params = &chip->params;
|
|
|
|
|
|
|
|
if (type == NANDSIM_EV_START) {
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "in READPARAM state\n");
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
|
|
|
|
} else if (type == NANDSIM_EV_ADDR) {
|
|
|
|
addr = *((uint8_t *)data);
|
|
|
|
|
|
|
|
if (addr == 0) {
|
|
|
|
nandchip_set_data(chip, (uint8_t *)params,
|
|
|
|
sizeof(*params), 0);
|
|
|
|
} else
|
|
|
|
nandsim_bad_address(chip, &addr);
|
|
|
|
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
read_evh(struct nandsim_chip *chip, uint32_t type, void *data)
|
|
|
|
{
|
|
|
|
static uint32_t column = 0, row = 0;
|
|
|
|
uint32_t size;
|
|
|
|
uint8_t cmd;
|
|
|
|
|
|
|
|
size = chip->cg.page_size + chip->cg.oob_size;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case NANDSIM_EV_START:
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "in READ state\n");
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
|
|
|
|
break;
|
|
|
|
case NANDSIM_EV_ADDR:
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
|
|
|
|
if (nandchip_get_addr_byte(chip, data, &column))
|
|
|
|
break;
|
|
|
|
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
|
|
|
|
} else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
|
|
|
|
if (nandchip_get_addr_byte(chip, data, &row))
|
|
|
|
break;
|
|
|
|
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_CMD;
|
|
|
|
} else
|
|
|
|
nandsim_ignore_address(chip, *((uint8_t *)data));
|
|
|
|
break;
|
|
|
|
case NANDSIM_EV_CMD:
|
|
|
|
cmd = *(uint8_t *)data;
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
|
|
|
|
cmd == NAND_CMD_READ_END) {
|
|
|
|
if (chip->read_delay != 0 &&
|
|
|
|
nandsim_delay(chip, chip->read_delay) == 0)
|
|
|
|
nandchip_clear_status(chip, NAND_STATUS_RDY);
|
|
|
|
else {
|
|
|
|
nandchip_chip_space(chip, row, column, size, 0);
|
|
|
|
nandchip_set_status(chip, NAND_STATUS_RDY);
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
break;
|
|
|
|
case NANDSIM_EV_TIMEOUT:
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
|
|
|
|
nandchip_chip_space(chip, row, column, size, 0);
|
|
|
|
nandchip_set_status(chip, NAND_STATUS_RDY);
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
|
|
write_evh(struct nandsim_chip *chip, uint32_t type, void *data)
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{
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static uint32_t column, row;
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uint32_t size;
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uint8_t cmd;
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int err;
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size = chip->cg.page_size + chip->cg.oob_size;
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switch(type) {
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case NANDSIM_EV_START:
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nandsim_log(chip, NANDSIM_LOG_SM, "in WRITE state\n");
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chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
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break;
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case NANDSIM_EV_ADDR:
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if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
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if (nandchip_get_addr_byte(chip, data, &column))
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break;
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chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
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} else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
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if (nandchip_get_addr_byte(chip, data, &row))
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break;
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err = nandchip_chip_space(chip, row, column, size, 1);
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if (err == -1)
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nandchip_set_status(chip, NAND_STATUS_FAIL);
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chip->sm_state = NANDSIM_STATE_WAIT_CMD;
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} else
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nandsim_ignore_address(chip, *((uint8_t *)data));
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break;
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case NANDSIM_EV_CMD:
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cmd = *(uint8_t *)data;
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if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
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cmd == NAND_CMD_PROG_END) {
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if (chip->prog_delay != 0 &&
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nandsim_delay(chip, chip->prog_delay) == 0)
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nandchip_clear_status(chip, NAND_STATUS_RDY);
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else {
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nandchip_set_status(chip, NAND_STATUS_RDY);
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nandsim_start_handler(chip, idle_evh);
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}
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} else
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nandsim_undefined(chip, type);
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break;
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case NANDSIM_EV_TIMEOUT:
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if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
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nandsim_start_handler(chip, idle_evh);
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nandchip_set_status(chip, NAND_STATUS_RDY);
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} else
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nandsim_undefined(chip, type);
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break;
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}
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}
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void
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erase_evh(struct nandsim_chip *chip, uint32_t type, void *data)
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{
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static uint32_t row, block_size;
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uint32_t lun, block, page;
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int err;
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uint8_t cmd;
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block_size = chip->cg.block_size +
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(chip->cg.oob_size * chip->cg.pgs_per_blk);
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switch (type) {
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case NANDSIM_EV_START:
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nandsim_log(chip, NANDSIM_LOG_SM, "in ERASE state\n");
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|
chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
|
|
|
|
break;
|
|
|
|
case NANDSIM_EV_CMD:
|
|
|
|
cmd = *(uint8_t *)data;
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
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|
|
cmd == NAND_CMD_ERASE_END) {
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|
|
if (chip->data.data_ptr != NULL &&
|
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|
|
chip->data.size == block_size)
|
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|
memset(chip->data.data_ptr, 0xff, block_size);
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|
else
|
|
|
|
nand_debug(NDBG_SIM,"Bad block erase data\n");
|
|
|
|
|
|
|
|
err = nand_row_to_blkpg(&chip->cg, row, &lun,
|
|
|
|
&block, &page);
|
|
|
|
if (!err) {
|
|
|
|
if (chip->blk_state[block].wear_lev > 0)
|
|
|
|
chip->blk_state[block].wear_lev--;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chip->erase_delay != 0 &&
|
|
|
|
nandsim_delay(chip, chip->erase_delay) == 0)
|
|
|
|
nandchip_clear_status(chip, NAND_STATUS_RDY);
|
|
|
|
else {
|
|
|
|
nandchip_set_status(chip, NAND_STATUS_RDY);
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
break;
|
|
|
|
case NANDSIM_EV_ADDR:
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
|
|
|
|
if (nandchip_get_addr_byte(chip, data, &row))
|
|
|
|
break;
|
|
|
|
|
|
|
|
err = nandchip_chip_space(chip, row, 0, block_size, 1);
|
|
|
|
if (err == -1) {
|
|
|
|
nandchip_set_status(chip, NAND_STATUS_FAIL);
|
|
|
|
}
|
|
|
|
chip->sm_state = NANDSIM_STATE_WAIT_CMD;
|
|
|
|
} else
|
|
|
|
nandsim_ignore_address(chip, *((uint8_t *)data));
|
|
|
|
break;
|
|
|
|
case NANDSIM_EV_TIMEOUT:
|
|
|
|
if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
|
|
|
|
nandchip_set_status(chip, NAND_STATUS_RDY);
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
reset_evh(struct nandsim_chip *chip, uint32_t type, void *data)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (type == NANDSIM_EV_START) {
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
|
|
|
|
chip->sm_state = NANDSIM_STATE_TIMEOUT;
|
|
|
|
nandchip_set_data(chip, NULL, 0, 0);
|
|
|
|
DELAY(500);
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
} else
|
|
|
|
nandsim_undefined(chip, type);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandsim_undefined(struct nandsim_chip *chip, uint8_t type)
|
|
|
|
{
|
|
|
|
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_ERR,
|
|
|
|
"ERR: Chip received ev %x in state %x\n",
|
|
|
|
type, chip->sm_state);
|
|
|
|
nandsim_start_handler(chip, idle_evh);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandsim_bad_address(struct nandsim_chip *chip, uint8_t *addr)
|
|
|
|
{
|
|
|
|
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_ERR,
|
|
|
|
"ERR: Chip received out of range address"
|
|
|
|
"%02x%02x - %02x%02x%02x\n", addr[0], addr[1], addr[2],
|
|
|
|
addr[3], addr[4]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandsim_ignore_address(struct nandsim_chip *chip, uint8_t byte)
|
|
|
|
{
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_SM, "ignored address byte: %d\n", byte);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nandsim_sm_error(struct nandsim_chip *chip)
|
|
|
|
{
|
|
|
|
|
|
|
|
nandsim_log(chip, NANDSIM_LOG_ERR, "ERR: State machine error."
|
|
|
|
"Restart required.\n");
|
|
|
|
}
|