2017-04-02 01:21:35 +00:00
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/*-
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* Copyright (c) 2017 Justin Hibbits <jhibbits@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include "spibus_if.h"
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/* TODO:
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*
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* Optimize FIFO reads and writes to do word-at-a-time instead of byte-at-a-time
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*/
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#define ESPI_SPMODE 0x0
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#define ESPI_SPMODE_EN 0x80000000
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#define ESPI_SPMODE_LOOP 0x40000000
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#define ESPI_SPMODE_HO_ADJ_M 0x00070000
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#define ESPI_SPMODE_TXTHR_M 0x00003f00
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#define ESPI_SPMODE_TXTHR_S 8
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#define ESPI_SPMODE_RXTHR_M 0x0000001f
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#define ESPI_SPMODE_RXTHR_S 0
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#define ESPI_SPIE 0x4
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#define ESPI_SPIE_RXCNT_M 0x3f000000
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#define ESPI_SPIE_RXCNT_S 24
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#define ESPI_SPIE_TXCNT_M 0x003f0000
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#define ESPI_SPIE_TXCNT_S 16
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#define ESPI_SPIE_TXE 0x00008000
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#define ESPI_SPIE_DON 0x00004000
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#define ESPI_SPIE_RXT 0x00002000
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#define ESPI_SPIE_RXF 0x00001000
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#define ESPI_SPIE_TXT 0x00000800
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#define ESPI_SPIE_RNE 0x00000200
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#define ESPI_SPIE_TNF 0x00000100
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#define ESPI_SPIM 0x8
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#define ESPI_SPCOM 0xc
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#define ESPI_SPCOM_CS_M 0xc0000000
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#define ESPI_SPCOM_CS_S 30
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#define ESPI_SPCOM_RXDELAY 0x20000000
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#define ESPI_SPCOM_DO 0x10000000
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#define ESPI_SPCOM_TO 0x08000000
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#define ESPI_SPCOM_HLD 0x04000000
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#define ESPI_SPCOM_RXSKIP_M 0x00ff0000
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#define ESPI_SPCOM_TRANLEN_M 0x0000ffff
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#define ESPI_SPITF 0x10
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#define ESPI_SPIRF 0x14
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#define ESPI_SPMODE0 0x20
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#define ESPI_SPMODE1 0x24
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#define ESPI_SPMODE2 0x28
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#define ESPI_SPMODE3 0x2c
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#define ESPI_CSMODE_CI 0x80000000
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#define ESPI_CSMODE_CP 0x40000000
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#define ESPI_CSMODE_REV 0x20000000
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#define ESPI_CSMODE_DIV16 0x10000000
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#define ESPI_CSMODE_PM_M 0x0f000000
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#define ESPI_CSMODE_PM_S 24
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#define ESPI_CSMODE_ODD 0x00800000
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#define ESPI_CSMODE_POL 0x00100000
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#define ESPI_CSMODE_LEN_M 0x000f0000
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#define ESPI_CSMODE_LEN(x) (x << 16)
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#define ESPI_CSMODE_CSBEF_M 0x0000f000
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#define ESPI_CSMODE_CSAFT_M 0x00000f00
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#define ESPI_CSMODE_CSCG_M 0x000000f8
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#define ESPI_CSMODE_CSCG(x) (x << 3)
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#define ESPI_CSMODE(n) (ESPI_SPMODE0 + n * 4)
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#define FSL_ESPI_WRITE(sc,off,val) bus_write_4(sc->sc_mem_res, off, val)
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#define FSL_ESPI_READ(sc,off) bus_read_4(sc->sc_mem_res, off)
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#define FSL_ESPI_WRITE_FIFO(sc,off,val) bus_write_1(sc->sc_mem_res, off, val)
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#define FSL_ESPI_READ_FIFO(sc,off) bus_read_1(sc->sc_mem_res, off)
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#define FSL_ESPI_LOCK(_sc) \
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mtx_lock(&(_sc)->sc_mtx)
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#define FSL_ESPI_UNLOCK(_sc) \
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mtx_unlock(&(_sc)->sc_mtx)
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struct fsl_espi_softc
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{
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device_t sc_dev;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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struct mtx sc_mtx;
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int sc_num_cs;
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struct spi_command *sc_cmd;
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uint32_t sc_len;
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uint32_t sc_read;
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uint32_t sc_flags;
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#define FSL_ESPI_BUSY 0x00000001
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uint32_t sc_written;
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void * sc_intrhand;
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};
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static void fsl_espi_intr(void *);
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static int
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fsl_espi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,mpc8536-espi"))
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return (ENXIO);
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device_set_desc(dev, "Freescale eSPI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fsl_espi_attach(device_t dev)
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{
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struct fsl_espi_softc *sc;
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int rid;
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phandle_t node;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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node = ofw_bus_get_node(dev);
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory resource\n");
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return (ENXIO);
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}
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot allocate interrupt\n");
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return (ENXIO);
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}
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/* Hook up our interrupt handler. */
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, fsl_espi_intr, sc, &sc->sc_intrhand)) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot setup the interrupt handler\n");
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return (ENXIO);
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}
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if (OF_getencprop(node, "fsl,espi-num-chipselects",
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&sc->sc_num_cs, sizeof(sc->sc_num_cs)) < 0 )
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sc->sc_num_cs = 4;
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mtx_init(&sc->sc_mtx, "fsl_espi", NULL, MTX_DEF);
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/* Enable the SPI controller. */
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FSL_ESPI_WRITE(sc, ESPI_SPMODE, ESPI_SPMODE_EN |
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(16 << ESPI_SPMODE_TXTHR_S) | (15 << ESPI_SPMODE_RXTHR_S));
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/* Disable all interrupts until we start transfers */
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FSL_ESPI_WRITE(sc, ESPI_SPIM, 0);
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device_add_child(dev, "spibus", -1);
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return (bus_generic_attach(dev));
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}
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static int
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fsl_espi_detach(device_t dev)
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{
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struct fsl_espi_softc *sc;
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bus_generic_detach(dev);
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sc = device_get_softc(dev);
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FSL_ESPI_WRITE(sc, ESPI_SPMODE, 0);
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sc = device_get_softc(dev);
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mtx_destroy(&sc->sc_mtx);
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (0);
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}
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static void
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fsl_espi_fill_fifo(struct fsl_espi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t spier, written;
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uint8_t *data;
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cmd = sc->sc_cmd;
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spier = FSL_ESPI_READ(sc, ESPI_SPIE);
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while (sc->sc_written < sc->sc_len &&
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(spier & ESPI_SPIE_TNF)) {
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data = (uint8_t *)cmd->tx_cmd;
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written = sc->sc_written++;
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if (written >= cmd->tx_cmd_sz) {
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data = (uint8_t *)cmd->tx_data;
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written -= cmd->tx_cmd_sz;
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}
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FSL_ESPI_WRITE_FIFO(sc, ESPI_SPITF, data[written]);
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spier = FSL_ESPI_READ(sc, ESPI_SPIE);
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}
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}
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static void
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fsl_espi_drain_fifo(struct fsl_espi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t spier, read;
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uint8_t *data;
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uint8_t r;
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cmd = sc->sc_cmd;
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spier = FSL_ESPI_READ(sc, ESPI_SPIE);
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while (sc->sc_read < sc->sc_len && (spier & ESPI_SPIE_RNE)) {
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data = (uint8_t *)cmd->rx_cmd;
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read = sc->sc_read++;
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if (read >= cmd->rx_cmd_sz) {
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data = (uint8_t *)cmd->rx_data;
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read -= cmd->rx_cmd_sz;
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}
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r = FSL_ESPI_READ_FIFO(sc, ESPI_SPIRF);
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data[read] = r;
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spier = FSL_ESPI_READ(sc, ESPI_SPIE);
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}
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}
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static void
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fsl_espi_intr(void *arg)
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{
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struct fsl_espi_softc *sc;
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uint32_t spie;
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sc = (struct fsl_espi_softc *)arg;
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FSL_ESPI_LOCK(sc);
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/* Filter stray interrupts. */
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if ((sc->sc_flags & FSL_ESPI_BUSY) == 0) {
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FSL_ESPI_UNLOCK(sc);
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return;
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}
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spie = FSL_ESPI_READ(sc, ESPI_SPIE);
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FSL_ESPI_WRITE(sc, ESPI_SPIE, spie);
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/* TX - Fill up the FIFO. */
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fsl_espi_fill_fifo(sc);
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/* RX - Drain the FIFO. */
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fsl_espi_drain_fifo(sc);
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/* Check for end of transfer. */
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if (spie & ESPI_SPIE_DON)
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wakeup(sc->sc_dev);
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FSL_ESPI_UNLOCK(sc);
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}
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static int
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fsl_espi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct fsl_espi_softc *sc;
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u_long plat_clk;
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uint32_t csmode, spi_clk, spi_mode;
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int cs, err, pm;
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sc = device_get_softc(dev);
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("TX/RX command sizes should be equal"));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("TX/RX data sizes should be equal"));
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/* Restrict transmit length to command max length */
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if (cmd->tx_cmd_sz + cmd->tx_data_sz > ESPI_SPCOM_TRANLEN_M + 1) {
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return (EINVAL);
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}
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/* Get the proper chip select for this child. */
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spibus_get_cs(child, &cs);
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if (cs < 0 || cs > sc->sc_num_cs) {
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device_printf(dev,
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"Invalid chip select %d requested by %s\n", cs,
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device_get_nameunit(child));
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return (EINVAL);
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}
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spibus_get_clock(child, &spi_clk);
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spibus_get_mode(child, &spi_mode);
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FSL_ESPI_LOCK(sc);
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/* If the controller is in use wait until it is available. */
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while (sc->sc_flags & FSL_ESPI_BUSY)
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mtx_sleep(dev, &sc->sc_mtx, 0, "fsl_espi", 0);
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/* Now we have control over SPI controller. */
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sc->sc_flags = FSL_ESPI_BUSY;
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/* Save a pointer to the SPI command. */
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sc->sc_cmd = cmd;
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sc->sc_read = 0;
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|
|
sc->sc_written = 0;
|
|
|
|
sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
|
|
|
|
|
|
|
|
plat_clk = mpc85xx_get_system_clock();
|
|
|
|
spi_clk = max(spi_clk, plat_clk / (16 * 16));
|
|
|
|
if (plat_clk == 0) {
|
|
|
|
device_printf(dev,
|
|
|
|
"unable to get platform clock, giving up.\n");
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
csmode = 0;
|
|
|
|
if (plat_clk > spi_clk * 16 * 2) {
|
|
|
|
csmode |= ESPI_CSMODE_DIV16;
|
|
|
|
plat_clk /= 16;
|
|
|
|
}
|
|
|
|
pm = howmany(plat_clk, spi_clk * 2) - 1;
|
|
|
|
if (pm < 0)
|
|
|
|
pm = 1;
|
|
|
|
if (pm > 15)
|
|
|
|
pm = 15;
|
|
|
|
|
|
|
|
csmode |= (pm << ESPI_CSMODE_PM_S);
|
|
|
|
csmode |= ESPI_CSMODE_REV;
|
|
|
|
if (spi_mode == SPIBUS_MODE_CPOL || spi_mode == SPIBUS_MODE_CPOL_CPHA)
|
|
|
|
csmode |= ESPI_CSMODE_CI;
|
|
|
|
if (spi_mode == SPIBUS_MODE_CPHA || spi_mode == SPIBUS_MODE_CPOL_CPHA)
|
|
|
|
csmode |= ESPI_CSMODE_CP;
|
|
|
|
if (!(cs & SPIBUS_CS_HIGH))
|
|
|
|
csmode |= ESPI_CSMODE_POL;
|
|
|
|
csmode |= ESPI_CSMODE_LEN(7);/* Only deal with 8-bit characters. */
|
|
|
|
csmode |= ESPI_CSMODE_CSCG(1); /* XXX: Make this configurable? */
|
|
|
|
/* Configure transaction */
|
|
|
|
FSL_ESPI_WRITE(sc, ESPI_SPCOM, (cs << ESPI_SPCOM_CS_S) | (sc->sc_len - 1));
|
|
|
|
FSL_ESPI_WRITE(sc, ESPI_CSMODE(cs), csmode);
|
|
|
|
/* Enable interrupts we need. */
|
|
|
|
FSL_ESPI_WRITE(sc, ESPI_SPIM,
|
|
|
|
ESPI_SPIE_TXE | ESPI_SPIE_DON | ESPI_SPIE_RXF);
|
|
|
|
|
|
|
|
/* Wait for the transaction to complete. */
|
|
|
|
err = mtx_sleep(dev, &sc->sc_mtx, 0, "fsl_espi", hz * 2);
|
|
|
|
FSL_ESPI_WRITE(sc, ESPI_SPIM, 0);
|
|
|
|
|
|
|
|
/* Release the controller and wakeup the next thread waiting for it. */
|
|
|
|
sc->sc_flags = 0;
|
|
|
|
wakeup_one(dev);
|
|
|
|
FSL_ESPI_UNLOCK(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for transfer timeout. The SPI controller doesn't
|
|
|
|
* return errors.
|
|
|
|
*/
|
|
|
|
if (err == EWOULDBLOCK) {
|
|
|
|
device_printf(sc->sc_dev, "SPI error\n");
|
|
|
|
err = EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
|
|
|
static phandle_t
|
|
|
|
fsl_espi_get_node(device_t bus, device_t dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
/* We only have one child, the SPI bus, which needs our own node. */
|
|
|
|
return (ofw_bus_get_node(bus));
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t fsl_espi_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, fsl_espi_probe),
|
|
|
|
DEVMETHOD(device_attach, fsl_espi_attach),
|
|
|
|
DEVMETHOD(device_detach, fsl_espi_detach),
|
|
|
|
|
|
|
|
/* SPI interface */
|
|
|
|
DEVMETHOD(spibus_transfer, fsl_espi_transfer),
|
|
|
|
|
|
|
|
/* ofw_bus interface */
|
|
|
|
DEVMETHOD(ofw_bus_get_node, fsl_espi_get_node),
|
|
|
|
|
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t fsl_espi_driver = {
|
|
|
|
"spi",
|
|
|
|
fsl_espi_methods,
|
|
|
|
sizeof(struct fsl_espi_softc),
|
|
|
|
};
|
|
|
|
|
2022-05-10 17:21:38 +00:00
|
|
|
DRIVER_MODULE(fsl_espi, simplebus, fsl_espi_driver, 0, 0);
|