d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
43975bd56c
freebsd-dev/sys/dev/aic7xxx/aic7xxx.c

6858 lines
180 KiB
C
Raw Normal View History

Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Generic driver for the aic7xxx based adaptec SCSI controllers
* Product specific probe and attach routines can be found in:
* i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers
* pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890,
* aic7880, aic7870, aic7860, and aic7850 controllers
*
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
* without modification.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
* Alternatively, this software may be distributed under the terms of the
* the GNU Public License ("GPL").
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
$Id$ -> $FreeBSD$
1999-08-28 01:08:13 +00:00
* $FreeBSD$
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
/*
* A few notes on features of the driver.
*
* SCB paging takes advantage of the fact that devices stay disconnected
* from the bus a relatively long time and that while they're disconnected,
* having the SCBs for these transactions down on the host adapter is of
* little use. Instead of leaving this idle SCB down on the card we copy
* it back up into kernel memory and reuse the SCB slot on the card to
* schedule another transaction. This can be a real payoff when doing random
* I/O to tagged queueing devices since there are more transactions active at
* once for the device to sort for optimal seek reduction. The algorithm goes
* like this...
*
* The sequencer maintains two lists of its hardware SCBs. The first is the
* singly linked free list which tracks all SCBs that are not currently in
* use. The second is the doubly linked disconnected list which holds the
* SCBs of transactions that are in the disconnected state sorted most
* recently disconnected first. When the kernel queues a transaction to
* the card, a hardware SCB to "house" this transaction is retrieved from
* either of these two lists. If the SCB came from the disconnected list,
* a check is made to see if any data transfer or SCB linking (more on linking
* in a bit) information has been changed since it was copied from the host
* and if so, DMAs the SCB back up before it can be used. Once a hardware
* SCB has been obtained, the SCB is DMAed from the host. Before any work
* can begin on this SCB, the sequencer must ensure that either the SCB is
* for a tagged transaction or the target is not already working on another
* non-tagged transaction. If a conflict arises in the non-tagged case, the
* sequencer finds the SCB for the active transactions and sets the SCB_LINKED
* field in that SCB to this next SCB to execute. To facilitate finding
* active non-tagged SCBs, the last four bytes of up to the first four hardware
* SCBs serve as a storage area for the currently active SCB ID for each
* target.
*
* When a device reconnects, a search is made of the hardware SCBs to find
* the SCB for this transaction. If the search fails, a hardware SCB is
* pulled from either the free or disconnected SCB list and the proper
* SCB is DMAed from the host. If the MK_MESSAGE control bit is set
* in the control byte of the SCB while it was disconnected, the sequencer
* will assert ATN and attempt to issue a message to the host.
*
* When a command completes, a check for non-zero status and residuals is
* made. If either of these conditions exists, the SCB is DMAed back up to
* the host so that it can interpret this information. Additionally, in the
* case of bad status, the sequencer generates a special interrupt and pauses
* itself. This allows the host to setup a request sense command if it
* chooses for this target synchronously with the error so that sense
* information isn't lost.
*
*/
#include <opt_aic7xxx.h>
#include <pci.h>
#include <stddef.h> /* For offsetof */
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
Implement a new generic mechanism for attaching handler functions to events, in order to pave the way for removing a number of the ad-hoc implementations currently in use. Retire the at_shutdown family of functions and replace them with new event handler lists. Rework kern_shutdown.c to take greater advantage of the use of event handlers. Reviewed by: green
1999-08-21 06:24:40 +00:00
#include <sys/eventhandler.h>
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#include <sys/proc.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/cam_debug.h>
#include <cam/scsi/scsi_all.h>
#include <cam/scsi/scsi_message.h>
#if NPCI > 0
#include <machine/bus_memio.h>
#endif
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <machine/clock.h>
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
#include <sys/rman.h>
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#include <dev/aic7xxx/aic7xxx.h>
#include <dev/aic7xxx/sequencer.h>
#include <aic7xxx_reg.h>
#include <aic7xxx_seq.h>
#include <sys/kernel.h>
#ifndef AHC_TMODE_ENABLE
#define AHC_TMODE_ENABLE 0
#endif
#define MAX(a,b) (((a) > (b)) ? (a) : (b))
#define MIN(a,b) (((a) < (b)) ? (a) : (b))
#define ALL_CHANNELS '\0'
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
#define ALL_TARGETS_MASK 0xFFFF
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
#define INITIATOR_WILDCARD (~0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#define SIM_IS_SCSIBUS_B(ahc, sim) \
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
((sim) == ahc->sim_b)
#define SIM_CHANNEL(ahc, sim) \
(((sim) == ahc->sim_b) ? 'B' : 'A')
#define SIM_SCSI_ID(ahc, sim) \
(((sim) == ahc->sim_b) ? ahc->our_id_b : ahc->our_id)
#define SIM_PATH(ahc, sim) \
(((sim) == ahc->sim_b) ? ahc->path_b : ahc->path)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#define SCB_IS_SCSIBUS_B(scb) \
(((scb)->hscb->tcl & SELBUSB) != 0)
#define SCB_TARGET(scb) \
(((scb)->hscb->tcl & TID) >> 4)
#define SCB_CHANNEL(scb) \
(SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A')
#define SCB_LUN(scb) \
((scb)->hscb->tcl & LID)
#define SCB_TARGET_OFFSET(scb) \
(SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0))
#define SCB_TARGET_MASK(scb) \
(0x01 << (SCB_TARGET_OFFSET(scb)))
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
#define TCL_CHANNEL(ahc, tcl) \
((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A')
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
#define TCL_SCSI_ID(ahc, tcl) \
(TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
#define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT)
#define TCL_LUN(tcl) ((tcl) & LID)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#define ccb_scb_ptr spriv_ptr0
#define ccb_ahc_ptr spriv_ptr1
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
char *ahc_chip_names[] =
{
"NONE",
"aic7770",
"aic7850",
"aic7855",
"aic7859",
"aic7860",
"aic7870",
"aic7880",
"aic7890/91",
"aic7892",
"aic7895",
"aic7896/97",
"aic7899"
};
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
typedef enum {
ROLE_UNKNOWN,
ROLE_INITIATOR,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ROLE_TARGET
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
} role_t;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
struct ahc_devinfo {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
int our_scsiid;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
int target_offset;
u_int16_t target_mask;
u_int8_t target;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
u_int8_t lun;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
char channel;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
role_t role; /*
* Only guaranteed to be correct if not
* in the busfree state.
*/
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
};
typedef enum {
SEARCH_COMPLETE,
SEARCH_COUNT,
SEARCH_REMOVE
} ahc_search_action;
#ifdef AHC_DEBUG
static int ahc_debug = AHC_DEBUG;
#endif
#if NPCI > 0
void ahc_pci_intr(struct ahc_softc *ahc);
#endif
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
static int ahcinitscbdata(struct ahc_softc *ahc);
static void ahcfiniscbdata(struct ahc_softc *ahc);
static bus_dmamap_callback_t ahcdmamapcb;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
#if UNUSED
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_dump_targcmd(struct target_cmd *cmd);
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
#endif
Implement a new generic mechanism for attaching handler functions to events, in order to pave the way for removing a number of the ad-hoc implementations currently in use. Retire the at_shutdown family of functions and replace them with new event handler lists. Rework kern_shutdown.c to take greater advantage of the use of event handlers. Reviewed by: green
1999-08-21 06:24:40 +00:00
static void ahc_shutdown(void *arg, int howto);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static cam_status
ahc_find_tmode_devs(struct ahc_softc *ahc,
struct cam_sim *sim, union ccb *ccb,
struct tmode_tstate **tstate,
struct tmode_lstate **lstate,
int notfound_failure);
static void ahc_action(struct cam_sim *sim, union ccb *ccb);
static void ahc_async(void *callback_arg, u_int32_t code,
struct cam_path *path, void *arg);
static void ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs,
int nsegments, int error);
static void ahc_poll(struct cam_sim *sim);
static void ahc_setup_data(struct ahc_softc *ahc,
struct ccb_scsiio *csio, struct scb *scb);
static void ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
static void ahcallocscbs(struct ahc_softc *ahc);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
#if UNUSED
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static void ahc_scb_devinfo(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
struct scb *scb);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_fetch_devinfo(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static void ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
u_int target, u_int lun, char channel,
role_t role);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static u_int ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_done(struct ahc_softc *ahc, struct scb *scbp);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static struct tmode_tstate *
ahc_alloc_tstate(struct ahc_softc *ahc,
u_int scsi_id, char channel);
static void ahc_free_tstate(struct ahc_softc *ahc,
u_int scsi_id, char channel, int force);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
static void ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim,
union ccb *ccb);
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
static void ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
static int ahc_handle_target_cmd(struct ahc_softc *ahc,
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
struct target_cmd *cmd);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
static void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static void ahc_build_transfer_msg(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo);
static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
struct scb *scb);
static void ahc_setup_target_msgin(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo);
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
static int ahc_handle_msg_reject(struct ahc_softc *ahc,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
struct ahc_devinfo *devinfo);
static void ahc_clear_msg_state(struct ahc_softc *ahc);
static void ahc_handle_message_phase(struct ahc_softc *ahc,
struct cam_path *path);
static int ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
typedef enum {
MSGLOOP_IN_PROG,
MSGLOOP_MSGCOMPLETE,
MSGLOOP_TERMINATED
} msg_loop_stat;
static int ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path,
struct ahc_devinfo *devinfo);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static void ahc_handle_devreset(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
cam_status status, ac_code acode,
char *message,
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
int verbose_level);
#ifdef AHC_DUMP_SEQ
static void ahc_dumpseq(struct ahc_softc *ahc);
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_loadseq(struct ahc_softc *ahc);
static int ahc_check_patch(struct ahc_softc *ahc,
struct patch **start_patch,
int start_instr, int *skip_addr);
static void ahc_download_instr(struct ahc_softc *ahc,
int instrptr, u_int8_t *dconsts);
static int ahc_match_scb(struct scb *scb, int target, char channel,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
int lun, u_int tag, role_t role);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#ifdef AHC_DEBUG
static void ahc_print_scb(struct scb *scb);
#endif
static int ahc_search_qinfifo(struct ahc_softc *ahc, int target,
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
char channel, int lun, u_int tag,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
role_t role, u_int32_t status,
ahc_search_action action);
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
static void ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim,
union ccb *ccb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static int ahc_reset_channel(struct ahc_softc *ahc, char channel,
int initiate_reset);
static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
char channel, int lun, u_int tag, role_t role,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
u_int32_t status);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static int ahc_search_disc_list(struct ahc_softc *ahc, int target,
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
char channel, int lun, u_int tag,
int stop_on_first, int remove,
int save_state);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
u_int prev, u_int scbptr);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
static void ahc_clear_intstat(struct ahc_softc *ahc);
static void ahc_reset_current_bus(struct ahc_softc *ahc);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static struct ahc_syncrate *
ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static struct ahc_syncrate *
ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
u_int maxsync);
static u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate,
u_int maxsync);
static void ahc_validate_offset(struct ahc_softc *ahc,
struct ahc_syncrate *syncrate,
u_int *offset, int wide);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static void ahc_update_target_msg_request(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo,
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
int force, int paused);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static int ahc_create_path(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
struct cam_path **path);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_set_syncrate(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
struct cam_path *path,
struct ahc_syncrate *syncrate,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
u_int period, u_int offset, u_int type,
int paused);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_set_width(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
struct cam_path *path, u_int width, u_int type,
int paused);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static void ahc_set_tags(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
int enable);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_construct_sdtr(struct ahc_softc *ahc,
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int period, u_int offset);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static void ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void ahc_calc_residual(struct scb *scb);
static void ahc_update_pending_syncrates(struct ahc_softc *ahc);
static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb);
static timeout_t
ahc_timeout;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
static void ahc_queue_lstate_event(struct ahc_softc *ahc,
struct tmode_lstate *lstate,
u_int initiator_id, u_int event_type,
u_int event_arg);
static void ahc_send_lstate_events(struct ahc_softc *ahc,
struct tmode_lstate *lstate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static __inline int sequencer_paused(struct ahc_softc *ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static __inline void pause_sequencer(struct ahc_softc *ahc);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
static __inline void unpause_sequencer(struct ahc_softc *ahc);
static void restart_sequencer(struct ahc_softc *ahc);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static __inline u_int ahc_index_busy_tcl(struct ahc_softc *ahc,
u_int tcl, int unbusy);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static __inline void ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb);
static __inline void ahc_freeze_ccb(union ccb* ccb);
static __inline cam_status ahc_ccb_status(union ccb* ccb);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
static __inline void ahcsetccbstatus(union ccb* ccb,
cam_status status);
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
static void ahc_run_qoutfifo(struct ahc_softc *ahc);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static __inline struct ahc_initiator_tinfo *
ahc_fetch_transinfo(struct ahc_softc *ahc,
char channel,
u_int our_id, u_int target,
struct tmode_tstate **tstate);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
static void ahcfreescb(struct ahc_softc *ahc, struct scb *scb);
static __inline struct scb *ahcgetscb(struct ahc_softc *ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static __inline u_int32_t
ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
{
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
return (ahc->scb_data->hscb_busaddr
+ (sizeof(struct hardware_scb) * index));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
#define AHC_BUSRESET_DELAY 25 /* Reset delay in us */
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static __inline int
sequencer_paused(struct ahc_softc *ahc)
{
return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static __inline void
pause_sequencer(struct ahc_softc *ahc)
{
ahc_outb(ahc, HCNTRL, ahc->pause);
/*
* Since the sequencer can disable pausing in a critical section, we
* must loop until it actually stops.
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
while (sequencer_paused(ahc) == 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
;
}
static __inline void
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(struct ahc_softc *ahc)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, HCNTRL, ahc->unpause);
}
/*
* Restart the sequencer program from address zero
*/
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
static void
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
restart_sequencer(struct ahc_softc *ahc)
{
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
u_int i;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
pause_sequencer(ahc);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
/*
* Everytime we restart the sequencer, there
* is the possiblitity that we have restarted
* within a three instruction window where an
* SCB has been marked free but has not made it
* onto the free list. Since SCSI events(bus reset,
* unexpected bus free) will always freeze the
* sequencer, we cannot close this window. To
* avoid losing an SCB, we reconsitute the free
* list every time we restart the sequencer.
*/
ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
ahc_outb(ahc, SCBPTR, i);
if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL)
ahc_add_curscb_to_free_list(ahc);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static __inline u_int
ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int scbid;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scbid = ahc->untagged_scbs[tcl];
if (unbusy)
ahc->untagged_scbs[tcl] = SCB_LIST_NULL;
return (scbid);
}
static __inline void
ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb)
{
ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag;
}
static __inline void
ahc_freeze_ccb(union ccb* ccb)
{
if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
ccb->ccb_h.status |= CAM_DEV_QFRZN;
xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
}
}
static __inline cam_status
ahc_ccb_status(union ccb* ccb)
{
return (ccb->ccb_h.status & CAM_STATUS_MASK);
}
static __inline void
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(union ccb* ccb, cam_status status)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= status;
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static __inline struct ahc_initiator_tinfo *
ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
u_int remote_id, struct tmode_tstate **tstate)
{
/*
* Transfer data structures are stored from the perspective
* of the target role. Since the parameters for a connection
* in the initiator role to a given target are the same as
* when the roles are reversed, we pretend we are the target.
*/
if (channel == 'B')
our_id += 8;
*tstate = ahc->enabled_targets[our_id];
return (&(*tstate)->transinfo[remote_id]);
}
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
static void
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
{
struct target_cmd *cmd;
while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
/*
* Only advance through the queue if we
* had the resources to process the command.
*/
if (ahc_handle_target_cmd(ahc, cmd) != 0)
break;
ahc->tqinfifonext++;
cmd->cmd_valid = 0;
/*
* Lazily update our position in the target mode incomming
* command queue as seen by the sequencer.
*/
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
if ((ahc->features & AHC_HS_MAILBOX) != 0) {
u_int hs_mailbox;
hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
hs_mailbox &= ~HOST_TQINPOS;
hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
} else {
if (!paused)
pause_sequencer(ahc);
ahc_outb(ahc, KERNEL_TQINPOS,
ahc->tqinfifonext & HOST_TQINPOS);
if (!paused)
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
}
}
}
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
static void
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc_run_qoutfifo(struct ahc_softc *ahc)
{
struct scb *scb;
u_int scb_index;
while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
scb_index = ahc->qoutfifo[ahc->qoutfifonext];
ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL;
scb = &ahc->scb_data->scbarray[scb_index];
if (scb_index >= ahc->scb_data->numscbs
|| (scb->flags & SCB_ACTIVE) == 0) {
printf("%s: WARNING no command for scb %d "
"(cmdcmplt)\nQOUTPOS = %d\n",
ahc_name(ahc), scb_index,
ahc->qoutfifonext - 1);
continue;
}
/*
* Save off the residual
* if there is one.
*/
if (scb->hscb->residual_SG_count != 0)
ahc_calc_residual(scb);
else
scb->ccb->csio.resid = 0;
ahc_done(ahc, scb);
}
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*
* An scb (and hence an scb entry on the board) is put onto the
* free list.
*/
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
static void
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcfreescb(struct ahc_softc *ahc, struct scb *scb)
{
struct hardware_scb *hscb;
int opri;
hscb = scb->hscb;
opri = splcam();
if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0
&& (scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
ahc->flags &= ~AHC_RESOURCE_SHORTAGE;
}
/* Clean up for the next user */
scb->flags = SCB_FREE;
hscb->control = 0;
hscb->status = 0;
SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links);
splx(opri);
}
/*
* Get a free scb, either one already assigned to a hardware slot
* on the adapter or one that will require an SCB to be paged out before
* use. If there are none, see if we can allocate a new SCB. Otherwise
* either return an error or sleep.
*/
static __inline struct scb *
ahcgetscb(struct ahc_softc *ahc)
{
struct scb *scbp;
int opri;
opri = splcam();
if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) {
SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links);
} else {
ahcallocscbs(ahc);
scbp = SLIST_FIRST(&ahc->scb_data->free_scbs);
if (scbp != NULL)
SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links);
}
splx(opri);
return (scbp);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
char *
ahc_name(struct ahc_softc *ahc)
{
static char name[10];
Examine all occurrences of sprintf(), strcat(), and str[n]cpy() for possible buffer overflow problems. Replaced most sprintf()'s with snprintf(); for others cases, added terminating NUL bytes where appropriate, replaced constants like "16" with sizeof(), etc. These changes include several bug fixes, but most changes are for maintainability's sake. Any instance where it wasn't "immediately obvious" that a buffer overflow could not occur was made safer. Reviewed by: Bruce Evans <bde@zeta.org.au> Reviewed by: Matthew Dillon <dillon@apollo.backplane.com> Reviewed by: Mike Spengler <mks@networkcs.com>
1998-12-04 22:54:57 +00:00
snprintf(name, sizeof(name), "ahc%d", ahc->unit);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return (name);
}
#ifdef AHC_DEBUG
static void
ahc_print_scb(struct scb *scb)
{
struct hardware_scb *hscb = scb->hscb;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
printf("scb:%p control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%x\n",
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scb,
hscb->control,
hscb->tcl,
hscb->cmdlen,
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
hscb->cmdpointer);
printf(" datlen:%d data:0x%x segs:0x%x segp:0x%x\n",
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
hscb->datalen,
hscb->data,
hscb->SG_count,
hscb->SG_pointer);
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
printf(" sg_addr:%x sg_len:%d\n",
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb->sg_list[0].addr,
scb->sg_list[0].len);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n",
hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2],
hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5],
hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8],
hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]);
}
#endif
static struct {
u_int8_t errno;
char *errmesg;
} hard_error[] = {
{ ILLHADDR, "Illegal Host Access" },
{ ILLSADDR, "Illegal Sequencer Address referrenced" },
{ ILLOPCODE, "Illegal Opcode in sequencer program" },
{ SQPARERR, "Sequencer Parity Error" },
{ DPARERR, "Data-path Parity Error" },
{ MPARERR, "Scratch or SCB Memory Parity Error" },
{ PCIERRSTAT, "PCI Error detected" },
{ CIOPARERR, "CIOBUS Parity Error" },
};
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
static struct {
u_int8_t phase;
u_int8_t mesg_out; /* Message response to parity errors */
char *phasemsg;
} phase_table[] = {
{ P_DATAOUT, MSG_NOOP, "in Data-out phase" },
{ P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
{ P_COMMAND, MSG_NOOP, "in Command phase" },
{ P_MESGOUT, MSG_NOOP, "in Message-out phase" },
{ P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
{ P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
{ P_BUSFREE, MSG_NOOP, "while idle" },
{ 0, MSG_NOOP, "in unknown phase" }
};
static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Valid SCSIRATE values. (p. 3-17)
* Provides a mapping of tranfer periods in ns to the proper value to
* stick in the scsiscfr reg to use that transfer rate.
*/
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
#define AHC_SYNCRATE_DT 0
#define AHC_SYNCRATE_ULTRA2 1
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
#define AHC_SYNCRATE_ULTRA 3
#define AHC_SYNCRATE_FAST 6
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static struct ahc_syncrate ahc_syncrates[] = {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
/* ultra2 fast/ultra period rate */
{ 0x42, 0x000, 9, "80.0" },
{ 0x03, 0x000, 10, "40.0" },
{ 0x04, 0x000, 11, "33.0" },
{ 0x05, 0x100, 12, "20.0" },
{ 0x06, 0x110, 15, "16.0" },
{ 0x07, 0x120, 18, "13.4" },
{ 0x08, 0x000, 25, "10.0" },
{ 0x19, 0x010, 31, "8.0" },
{ 0x1a, 0x020, 37, "6.67" },
{ 0x1b, 0x030, 43, "5.7" },
{ 0x1c, 0x040, 50, "5.0" },
{ 0x00, 0x050, 56, "4.4" },
{ 0x00, 0x060, 62, "4.0" },
{ 0x00, 0x070, 68, "3.6" },
{ 0x00, 0x000, 0, NULL }
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
};
/*
* Allocate a controller structure for a new device and initialize it.
*/
struct ahc_softc *
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahc_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id,
bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features,
ahc_flag flags, struct scb_data *scb_data)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
/*
* find unit and check we have that many defined
*/
struct ahc_softc *ahc;
size_t alloc_size;
/*
* Allocate a storage area for us
*/
if (scb_data == NULL)
/*
* We are not sharing SCB space with another controller
* so allocate our own SCB data space.
*/
alloc_size = sizeof(struct full_ahc_softc);
else
alloc_size = sizeof(struct ahc_softc);
ahc = malloc(alloc_size, M_DEVBUF, M_NOWAIT);
if (!ahc) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
device_printf(dev, "cannot malloc softc!\n");
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return NULL;
}
bzero(ahc, alloc_size);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
LIST_INIT(&ahc->pending_ccbs);
ahc->device = dev;
ahc->unit = device_get_unit(dev);
ahc->regs_res_type = regs_type;
ahc->regs_res_id = regs_id;
ahc->regs = regs;
ahc->tag = rman_get_bustag(regs);
ahc->bsh = rman_get_bushandle(regs);
ahc->parent_dmat = parent_dmat;
ahc->chip = chip;
ahc->features = features;
ahc->flags = flags;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (scb_data == NULL) {
struct full_ahc_softc* full_softc = (struct full_ahc_softc*)ahc;
ahc->scb_data = &full_softc->scb_data_storage;
} else
ahc->scb_data = scb_data;
ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN;
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
/* The IRQMS bit is only valid on VL and EISA chips */
if ((ahc->chip & AHC_PCI) != 0)
ahc->unpause &= ~IRQMS;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc->pause = ahc->unpause | PAUSE;
return (ahc);
}
void
ahc_free(ahc)
struct ahc_softc *ahc;
{
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcfiniscbdata(ahc);
switch (ahc->init_level) {
case 3:
bus_dmamap_unload(ahc->shared_data_dmat,
ahc->shared_data_dmamap);
case 2:
bus_dmamem_free(ahc->shared_data_dmat, ahc->qoutfifo,
ahc->shared_data_dmamap);
bus_dmamap_destroy(ahc->shared_data_dmat,
ahc->shared_data_dmamap);
case 1:
bus_dma_tag_destroy(ahc->buffer_dmat);
break;
}
if (ahc->regs != NULL)
bus_release_resource(ahc->device, ahc->regs_res_type,
ahc->regs_res_id, ahc->regs);
if (ahc->irq != NULL)
bus_release_resource(ahc->device, ahc->irq_res_type,
0, ahc->irq);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
free(ahc, M_DEVBUF);
return;
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
static int
ahcinitscbdata(struct ahc_softc *ahc)
{
struct scb_data *scb_data;
int i;
scb_data = ahc->scb_data;
SLIST_INIT(&scb_data->free_scbs);
SLIST_INIT(&scb_data->sg_maps);
/* Allocate SCB resources */
scb_data->scbarray =
(struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX,
M_DEVBUF, M_NOWAIT);
if (scb_data->scbarray == NULL)
return (ENOMEM);
bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX);
/* Determine the number of hardware SCBs and initialize them */
scb_data->maxhscbs = ahc_probe_scbs(ahc);
/* SCB 0 heads the free list */
ahc_outb(ahc, FREE_SCBH, 0);
for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
ahc_outb(ahc, SCBPTR, i);
/* Clear the control byte. */
ahc_outb(ahc, SCB_CONTROL, 0);
/* Set the next pointer */
ahc_outb(ahc, SCB_NEXT, i+1);
/* Make the tag number invalid */
ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
}
/* Make sure that the last SCB terminates the free list */
ahc_outb(ahc, SCBPTR, i-1);
ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
/* Ensure we clear the 0 SCB's control byte. */
ahc_outb(ahc, SCBPTR, 0);
ahc_outb(ahc, SCB_CONTROL, 0);
scb_data->maxhscbs = i;
if (ahc->scb_data->maxhscbs == 0)
panic("%s: No SCB space found", ahc_name(ahc));
/*
* Create our DMA tags. These tags define the kinds of device
Fix typo (accessable --> accessible). PR: 18588 Submitted by: Anatoly Vorobey <mellon@pobox.com> Reviewed by: asmodai
2000-06-14 17:53:40 +00:00
* accessible memory allocations and memory mappings we will
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
* need to perform during normal operation.
*
* Unless we need to further restrict the allocation, we rely
* on the restrictions of the parent dmat, hence the common
* use of MAXADDR and MAXSIZE.
*/
/* DMA tag for our hardware scb structures */
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*lowaddr*/BUS_SPACE_MAXADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
AHC_SCB_MAX * sizeof(struct hardware_scb),
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &scb_data->hscb_dmat) != 0) {
goto error_exit;
}
scb_data->init_level++;
/* Allocation for our ccbs */
if (bus_dmamem_alloc(scb_data->hscb_dmat, (void **)&scb_data->hscbs,
BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
goto error_exit;
}
scb_data->init_level++;
/* And permanently map them */
bus_dmamap_load(scb_data->hscb_dmat, scb_data->hscb_dmamap,
scb_data->hscbs,
AHC_SCB_MAX * sizeof(struct hardware_scb),
ahcdmamapcb, &scb_data->hscb_busaddr, /*flags*/0);
scb_data->init_level++;
/* DMA tag for our sense buffers */
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*lowaddr*/BUS_SPACE_MAXADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
AHC_SCB_MAX * sizeof(struct scsi_sense_data),
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &scb_data->sense_dmat) != 0) {
goto error_exit;
}
scb_data->init_level++;
/* Allocate them */
if (bus_dmamem_alloc(scb_data->sense_dmat, (void **)&scb_data->sense,
BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
goto error_exit;
}
scb_data->init_level++;
/* And permanently map them */
bus_dmamap_load(scb_data->sense_dmat, scb_data->sense_dmamap,
scb_data->sense,
AHC_SCB_MAX * sizeof(struct scsi_sense_data),
ahcdmamapcb, &scb_data->sense_busaddr, /*flags*/0);
scb_data->init_level++;
/* DMA tag for our S/G structures. We allocate in page sized chunks */
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*lowaddr*/BUS_SPACE_MAXADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
PAGE_SIZE, /*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &scb_data->sg_dmat) != 0) {
goto error_exit;
}
scb_data->init_level++;
/* Perform initial CCB allocation */
bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb));
ahcallocscbs(ahc);
if (scb_data->numscbs == 0) {
printf("%s: ahc_init_scb_data - "
"Unable to allocate initial scbs\n",
ahc_name(ahc));
goto error_exit;
}
/*
* Note that we were successfull
*/
return 0;
error_exit:
return ENOMEM;
}
static void
ahcfiniscbdata(struct ahc_softc *ahc)
{
struct scb_data *scb_data;
scb_data = ahc->scb_data;
switch (scb_data->init_level) {
default:
case 7:
{
struct sg_map_node *sg_map;
while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
bus_dmamap_unload(scb_data->sg_dmat,
sg_map->sg_dmamap);
bus_dmamem_free(scb_data->sg_dmat, sg_map->sg_vaddr,
sg_map->sg_dmamap);
free(sg_map, M_DEVBUF);
}
bus_dma_tag_destroy(scb_data->sg_dmat);
}
case 6:
bus_dmamap_unload(scb_data->sense_dmat,
scb_data->sense_dmamap);
case 5:
bus_dmamem_free(scb_data->sense_dmat, scb_data->sense,
scb_data->sense_dmamap);
bus_dmamap_destroy(scb_data->sense_dmat,
scb_data->sense_dmamap);
case 4:
bus_dma_tag_destroy(scb_data->sense_dmat);
case 3:
bus_dmamap_unload(scb_data->hscb_dmat, scb_data->hscb_dmamap);
case 2:
bus_dmamem_free(scb_data->hscb_dmat, scb_data->hscbs,
scb_data->hscb_dmamap);
bus_dmamap_destroy(scb_data->hscb_dmat, scb_data->hscb_dmamap);
case 1:
bus_dma_tag_destroy(scb_data->hscb_dmat);
break;
}
if (scb_data->scbarray != NULL)
free(scb_data->scbarray, M_DEVBUF);
}
static void
ahcdmamapcb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
bus_addr_t *baddr;
baddr = (bus_addr_t *)arg;
*baddr = segs->ds_addr;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
int
ahc_reset(struct ahc_softc *ahc)
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int sblkctl;
int wait;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
#ifdef AHC_DUMP_SEQ
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
if (ahc->init_level == 0)
ahc_dumpseq(ahc);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
/*
* Ensure that the reset has finished
*/
wait = 1000;
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
do {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
DELAY(1000);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
} while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (wait == 0) {
printf("%s: WARNING - Failed chip reset! "
"Trying to initialize anyway.\n", ahc_name(ahc));
}
ahc_outb(ahc, HCNTRL, ahc->pause);
/* Determine channel configuration */
sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
/* No Twin Channel PCI cards */
if ((ahc->chip & AHC_PCI) != 0)
sblkctl &= ~SELBUSB;
switch (sblkctl) {
case 0:
/* Single Narrow Channel */
break;
case 2:
/* Wide Channel */
ahc->features |= AHC_WIDE;
break;
case 8:
/* Twin Channel */
ahc->features |= AHC_TWIN;
break;
default:
printf(" Unsupported adapter type. Ignoring\n");
return(-1);
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return (0);
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/*
* Called when we have an active connection to a target on the bus,
* this function finds the nearest syncrate to the input period limited
* by the capabilities of the bus connectivity of the target.
*/
static struct ahc_syncrate *
ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) {
u_int maxsync;
if ((ahc->features & AHC_ULTRA2) != 0) {
if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
&& (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
maxsync = AHC_SYNCRATE_ULTRA2;
} else {
maxsync = AHC_SYNCRATE_ULTRA;
}
} else if ((ahc->features & AHC_ULTRA) != 0) {
maxsync = AHC_SYNCRATE_ULTRA;
} else {
maxsync = AHC_SYNCRATE_FAST;
}
return (ahc_find_syncrate(ahc, period, maxsync));
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Look up the valid period to SCSIRATE conversion in our table.
* Return the period and offset that should be sent to the target
* if this was the beginning of an SDTR.
*/
static struct ahc_syncrate *
ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync)
{
struct ahc_syncrate *syncrate;
syncrate = &ahc_syncrates[maxsync];
while ((syncrate->rate != NULL)
&& ((ahc->features & AHC_ULTRA2) == 0
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
|| (syncrate->sxfr_u2 != 0))) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (*period <= syncrate->period) {
/*
* When responding to a target that requests
* sync, the requested rate may fall between
* two rates that we can output, but still be
* a rate that we can receive. Because of this,
* we want to respond to the target with
* the same rate that it sent to us even
* if the period we use to send data to it
* is lower. Only lower the response period
* if we must.
*/
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
if (syncrate == &ahc_syncrates[maxsync])
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*period = syncrate->period;
break;
}
syncrate++;
}
if ((*period == 0)
|| (syncrate->rate == NULL)
|| ((ahc->features & AHC_ULTRA2) != 0
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
&& (syncrate->sxfr_u2 == 0))) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Use asynchronous transfers. */
*period = 0;
syncrate = NULL;
}
return (syncrate);
}
static u_int
ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
{
struct ahc_syncrate *syncrate;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
if ((ahc->features & AHC_ULTRA2) != 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scsirate &= SXFR_ULTRA2;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
else
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scsirate &= SXFR;
syncrate = &ahc_syncrates[maxsync];
while (syncrate->rate != NULL) {
if ((ahc->features & AHC_ULTRA2) != 0) {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
if (syncrate->sxfr_u2 == 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return (syncrate->period);
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
} else if (scsirate == (syncrate->sxfr & SXFR)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return (syncrate->period);
}
syncrate++;
}
return (0); /* async */
}
static void
ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate,
u_int *offset, int wide)
{
u_int maxoffset;
/* Limit offset to what we can do */
if (syncrate == NULL) {
maxoffset = 0;
} else if ((ahc->features & AHC_ULTRA2) != 0) {
maxoffset = MAX_OFFSET_ULTRA2;
} else {
if (wide)
maxoffset = MAX_OFFSET_16BIT;
else
maxoffset = MAX_OFFSET_8BIT;
}
*offset = MIN(*offset, maxoffset);
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
static void
ahc_update_target_msg_request(struct ahc_softc *ahc,
struct ahc_devinfo *devinfo,
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo,
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
int force, int paused)
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
{
u_int targ_msg_req_orig;
targ_msg_req_orig = ahc->targ_msg_req;
if (tinfo->current.period != tinfo->goal.period
|| tinfo->current.width != tinfo->goal.width
Add a number of interrelated CAM feature enhancements and bug fixes. NOTE: These changes will require recompilation of any userland applications, like cdrecord, xmcd, etc., that use the CAM passthrough interface. A make world is recommended. camcontrol.[c8]: - We now support two new commands, "tags" and "negotiate". - The tags commands allows users to view the number of tagged openings for a device as well as a number of other related parameters, and it allows users to set tagged openings for a device. - The negotiate command allows users to enable and disable disconnection and tagged queueing, set sync rates, offsets and bus width. Note that not all of those features are available for all controllers. Only the adv, ahc, and ncr drivers fully support all of the features at this point. Some cards do not allow the setting of sync rates, offsets and the like, and some of the drivers don't have any facilities to do so. Some drivers, like the adw driver, only support enabling or disabling sync negotiation, but do not support setting sync rates. - new description in the camcontrol man page of how to format a disk - cleanup of the camcontrol inquiry command - add support in the 'devlist' command for skipping unconfigured devices if -v was not specified on the command line. - make use of the new base_transfer_speed in the path inquiry CCB. - fix CCB bzero cases cam_xpt.c, cam_sim.[ch], cam_ccb.h: - new flags on many CCB function codes to designate whether they're non-immediate, use a user-supplied CCB, and can only be passed from userland programs via the xpt device. Use these flags in the transport layer and pass driver to categorize CCBs. - new flag in the transport layer device matching code for device nodes that indicates whether a device is unconfigured - bump the CAM version from 0x10 to 0x11 - Change the CAM ioctls to use the version as their group code, so we can force users to recompile code even when the CCB size doesn't change. - add + fill in a new value in the path inquiry CCB, base_transfer_speed. Remove a corresponding field from the cam_sim structure, and add code to every SIM to set this field to the proper value. - Fix the set transfer settings code in the transport layer. scsi_cd.c: - make some variables volatile instead of just casting them in various places - fix a race condition in the changer code - attach unless we get a "logical unit not supported" error. This should fix all of the cases where people have devices that return weird errors when they don't have media in the drive. scsi_da.c: - attach unless we get a "logical unit not supported" error scsi_pass.c: - for immediate CCBs, just malloc a CCB to send the user request in. This gets rid of the 'held' count problem in camcontrol tags. scsi_pass.h: - change the CAM ioctls to use the CAM version as their group code. adv driver: - Allow changing the sync rate and offset separately. adw driver - Allow changing the sync rate and offset separately. aha driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. ahc driver: - Allow setting offset and sync rate separately bt driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. NCR driver: - Fix the ultra/ultra 2 negotiation bug - allow setting both the sync rate and offset separately Other HBA drivers: - Put code in to set the base_transfer_speed field for XPT_GET_TRAN_SETTINGS CCBs. Reviewed by: gibbs, mjacob (isp), imp (aha)
1999-05-06 20:16:39 +00:00
|| tinfo->current.offset != tinfo->goal.offset
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
|| (force
&& (tinfo->goal.period != 0
|| tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT)))
ahc->targ_msg_req |= devinfo->target_mask;
else
ahc->targ_msg_req &= ~devinfo->target_mask;
if (ahc->targ_msg_req != targ_msg_req_orig) {
/* Update the message request bit for this target */
Better workaround for aic7890 chip bug. Use the HS_MAILBOX register to tell the sequencer to pause itself for a target msg variable update. This avoids the pause race entirely as HS_MAILBOX can be accessed without pausing the chip. 3.2 Merge candidate.
1999-05-14 05:07:25 +00:00
if ((ahc->features & AHC_HS_MAILBOX) != 0) {
if (paused) {
ahc_outb(ahc, TARGET_MSG_REQUEST,
ahc->targ_msg_req & 0xFF);
ahc_outb(ahc, TARGET_MSG_REQUEST + 1,
(ahc->targ_msg_req >> 8) & 0xFF);
} else {
ahc_outb(ahc, HS_MAILBOX,
0x01 << HOST_MAILBOX_SHIFT);
}
} else {
if (!paused)
pause_sequencer(ahc);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Better workaround for aic7890 chip bug. Use the HS_MAILBOX register to tell the sequencer to pause itself for a target msg variable update. This avoids the pause race entirely as HS_MAILBOX can be accessed without pausing the chip. 3.2 Merge candidate.
1999-05-14 05:07:25 +00:00
ahc_outb(ahc, TARGET_MSG_REQUEST,
ahc->targ_msg_req & 0xFF);
ahc_outb(ahc, TARGET_MSG_REQUEST + 1,
(ahc->targ_msg_req >> 8) & 0xFF);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Better workaround for aic7890 chip bug. Use the HS_MAILBOX register to tell the sequencer to pause itself for a target msg variable update. This avoids the pause race entirely as HS_MAILBOX can be accessed without pausing the chip. 3.2 Merge candidate.
1999-05-14 05:07:25 +00:00
if (!paused)
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
}
}
static int
ahc_create_path(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
struct cam_path **path)
{
path_id_t path_id;
if (devinfo->channel == 'B')
path_id = cam_sim_path(ahc->sim_b);
else
path_id = cam_sim_path(ahc->sim);
return (xpt_create_path(path, /*periph*/NULL,
path_id, devinfo->target,
devinfo->lun));
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
struct cam_path *path, struct ahc_syncrate *syncrate,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
u_int period, u_int offset, u_int type, int paused)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
u_int old_period;
u_int old_offset;
int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (syncrate == NULL) {
period = 0;
offset = 0;
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
old_period = tinfo->current.period;
old_offset = tinfo->current.offset;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((type & AHC_TRANS_CUR) != 0
&& (old_period != period || old_offset != offset)) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
struct cam_path *path2;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
u_int scsirate;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
scsirate = tinfo->scsirate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((ahc->features & AHC_ULTRA2) != 0) {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
/* XXX */
/* Force single edge until DT is fully implemented */
scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
if (syncrate != NULL)
scsirate |= syncrate->sxfr_u2|SINGLE_EDGE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
if (active)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SCSIOFFSET, offset);
} else {
scsirate &= ~(SXFR|SOFS);
/*
* Ensure Ultra mode is set properly for
* this target.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tstate->ultraenb &= ~devinfo->target_mask;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (syncrate != NULL) {
if (syncrate->sxfr & ULTRA_SXFR) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tstate->ultraenb |=
devinfo->target_mask;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
scsirate |= syncrate->sxfr & SXFR;
scsirate |= offset & SOFS;
}
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
if (active) {
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int sxfrctl0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
sxfrctl0 &= ~FAST20;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (tstate->ultraenb & devinfo->target_mask)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
sxfrctl0 |= FAST20;
ahc_outb(ahc, SXFRCTL0, sxfrctl0);
}
}
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
if (active)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SCSIRATE, scsirate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
tinfo->scsirate = scsirate;
tinfo->current.period = period;
tinfo->current.offset = offset;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Update the syncrates in any pending scbs */
ahc_update_pending_syncrates(ahc);
/*
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
* If possible, tell the SCSI layer about the
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
* new transfer parameters.
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* If possible, update the XPT's notion of our transfer rate */
path2 = NULL;
if (path == NULL) {
int error;
error = ahc_create_path(ahc, devinfo, &path2);
if (error == CAM_REQ_CMP)
path = path2;
else
path2 = NULL;
}
if (path != NULL) {
struct ccb_trans_settings neg;
neg.sync_period = period;
neg.sync_offset = offset;
neg.valid = CCB_TRANS_SYNC_RATE_VALID
| CCB_TRANS_SYNC_OFFSET_VALID;
xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1);
xpt_async(AC_TRANSFER_NEG, path, &neg);
}
if (path2 != NULL)
xpt_free_path(path2);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (bootverbose) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (offset != 0) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("%s: target %d synchronous at %sMHz, "
"offset = 0x%x\n", ahc_name(ahc),
devinfo->target, syncrate->rate, offset);
} else {
printf("%s: target %d using "
"asynchronous transfers\n",
ahc_name(ahc), devinfo->target);
}
}
}
if ((type & AHC_TRANS_GOAL) != 0) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
tinfo->goal.period = period;
tinfo->goal.offset = offset;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if ((type & AHC_TRANS_USER) != 0) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
tinfo->user.period = period;
tinfo->user.offset = offset;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
ahc_update_target_msg_request(ahc, devinfo, tinfo,
/*force*/FALSE,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
paused);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
struct cam_path *path, u_int width, u_int type, int paused)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
u_int oldwidth;
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
oldwidth = tinfo->current.width;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
struct cam_path *path2;
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int scsirate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
scsirate = tinfo->scsirate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scsirate &= ~WIDEXFER;
if (width == MSG_EXT_WDTR_BUS_16_BIT)
scsirate |= WIDEXFER;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
tinfo->scsirate = scsirate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
if (active)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SCSIRATE, scsirate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
tinfo->current.width = width;
/* If possible, update the XPT's notion of our transfer rate */
path2 = NULL;
if (path == NULL) {
int error;
error = ahc_create_path(ahc, devinfo, &path2);
if (error == CAM_REQ_CMP)
path = path2;
else
path2 = NULL;
}
if (path != NULL) {
struct ccb_trans_settings neg;
neg.bus_width = width;
neg.valid = CCB_TRANS_BUS_WIDTH_VALID;
xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1);
xpt_async(AC_TRANSFER_NEG, path, &neg);
}
if (path2 != NULL)
xpt_free_path(path2);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (bootverbose) {
printf("%s: target %d using %dbit transfers\n",
ahc_name(ahc), devinfo->target,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
8 * (0x01 << width));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if ((type & AHC_TRANS_GOAL) != 0)
tinfo->goal.width = width;
if ((type & AHC_TRANS_USER) != 0)
tinfo->user.width = width;
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
ahc_update_target_msg_request(ahc, devinfo, tinfo,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
/*force*/FALSE, paused);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static void
ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable)
{
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
if (enable)
tstate->tagenable |= devinfo->target_mask;
else
tstate->tagenable &= ~devinfo->target_mask;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Attach all the sub-devices we can find
*/
int
ahc_attach(struct ahc_softc *ahc)
{
struct ccb_setasync csa;
struct cam_devq *devq;
int bus_id;
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
int bus_id2;
struct cam_sim *sim;
struct cam_sim *sim2;
struct cam_path *path;
struct cam_path *path2;
int count;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
int s;
int error;
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
count = 0;
sim = NULL;
sim2 = NULL;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
s = splcam();
/* Hook up our interrupt handler */
Move the declaration of the interrupt type from the driver structure to the BUS_SETUP_INTR call.
1999-05-08 21:59:43 +00:00
if ((error = bus_setup_intr(ahc->device, ahc->irq, INTR_TYPE_CAM,
ahc_intr, ahc, &ahc->ih)) != 0) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
device_printf(ahc->device, "bus_setup_intr() failed: %d\n",
error);
goto fail;
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
/*
* Attach secondary channel first if the user has
* declared it the primary channel.
*/
if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) {
bus_id = 1;
bus_id2 = 0;
} else {
bus_id = 0;
bus_id2 = 1;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
* Create the device queue for our SIM(s).
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
devq = cam_simq_alloc(AHC_SCB_MAX);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (devq == NULL)
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
* Construct our first channel SIM entry
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
sim = cam_sim_alloc(ahc_action, ahc_poll, "ahc", ahc, ahc->unit,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
1, AHC_SCB_MAX, devq);
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
if (sim == NULL) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cam_simq_free(devq);
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
if (xpt_bus_register(sim, bus_id) != CAM_SUCCESS) {
cam_sim_free(sim, /*free_devq*/TRUE);
sim = NULL;
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
if (xpt_create_path(&path, /*periph*/NULL,
cam_sim_path(sim), CAM_TARGET_WILDCARD,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
xpt_bus_deregister(cam_sim_path(sim));
cam_sim_free(sim, /*free_devq*/TRUE);
sim = NULL;
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
xpt_setup_ccb(&csa.ccb_h, path, /*priority*/5);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
csa.ccb_h.func_code = XPT_SASYNC_CB;
csa.event_enable = AC_LOST_DEVICE;
csa.callback = ahc_async;
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
csa.callback_arg = sim;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_action((union ccb *)&csa);
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
count++;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (ahc->features & AHC_TWIN) {
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
sim2 = cam_sim_alloc(ahc_action, ahc_poll, "ahc",
ahc, ahc->unit, 1,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
AHC_SCB_MAX, devq);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
if (sim2 == NULL) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("ahc_attach: Unable to attach second "
"bus due to resource shortage");
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
if (xpt_bus_register(sim2, bus_id2) != CAM_SUCCESS) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("ahc_attach: Unable to attach second "
"bus due to resource shortage");
/*
* We do not want to destroy the device queue
* because the first bus is using it.
*/
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
cam_sim_free(sim2, /*free_devq*/FALSE);
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
if (xpt_create_path(&path2, /*periph*/NULL,
cam_sim_path(sim2),
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
CAM_TARGET_WILDCARD,
CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
xpt_bus_deregister(cam_sim_path(sim2));
cam_sim_free(sim2, /*free_devq*/FALSE);
sim2 = NULL;
goto fail;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
xpt_setup_ccb(&csa.ccb_h, path2, /*priority*/5);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
csa.ccb_h.func_code = XPT_SASYNC_CB;
csa.event_enable = AC_LOST_DEVICE;
csa.callback = ahc_async;
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
csa.callback_arg = sim2;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_action((union ccb *)&csa);
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
count++;
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
fail:
if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) {
ahc->sim_b = sim;
ahc->path_b = path;
ahc->sim = sim2;
ahc->path = path2;
} else {
ahc->sim = sim;
ahc->path = path;
ahc->sim_b = sim2;
ahc->path_b = path2;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
splx(s);
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
return (count);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
#if UNUSED
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static void
ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
struct scb *scb)
{
role_t role;
int our_id;
if (scb->ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) {
our_id = scb->ccb->ccb_h.target_id;
role = ROLE_TARGET;
} else {
our_id = SCB_CHANNEL(scb) == 'B' ? ahc->our_id_b : ahc->our_id;
role = ROLE_INITIATOR;
}
ahc_compile_devinfo(devinfo, our_id, SCB_TARGET(scb),
SCB_LUN(scb), SCB_CHANNEL(scb), role);
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
#endif
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
u_int saved_tcl;
role_t role;
int our_id;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc_inb(ahc, SSTAT0) & TARGET)
role = ROLE_TARGET;
else
role = ROLE_INITIATOR;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (role == ROLE_TARGET
&& (ahc->features & AHC_MULTI_TID) != 0
&& (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
/* We were selected, so pull our id from TARGIDIN */
our_id = ahc_inb(ahc, TARGIDIN) & OID;
} else if ((ahc->features & AHC_ULTRA2) != 0)
our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
else
our_id = ahc_inb(ahc, SCSIID) & OID;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
saved_tcl = ahc_inb(ahc, SAVED_TCL);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl),
TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl),
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
role);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
u_int lun, char channel, role_t role)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
devinfo->our_scsiid = our_id;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
devinfo->target = target;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
devinfo->lun = lun;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
devinfo->target_offset = target;
devinfo->channel = channel;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
devinfo->role = role;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (channel == 'B')
devinfo->target_offset += 8;
devinfo->target_mask = (0x01 << devinfo->target_offset);
}
/*
* Catch an interrupt from the adapter
*/
void
ahc_intr(void *arg)
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
struct ahc_softc *ahc;
u_int intstat;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc = (struct ahc_softc *)arg;
intstat = ahc_inb(ahc, INTSTAT);
/*
* Any interrupts to process?
*/
#if NPCI > 0
if ((intstat & INT_PEND) == 0) {
if ((ahc->chip & AHC_PCI) != 0
&& (ahc->unsolicited_ints > 500)) {
if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
ahc_pci_intr(ahc);
ahc->unsolicited_ints = 0;
} else {
ahc->unsolicited_ints++;
}
return;
} else {
ahc->unsolicited_ints = 0;
}
#else
if ((intstat & INT_PEND) == 0)
return;
#endif
if (intstat & CMDCMPLT) {
ahc_outb(ahc, CLRINT, CLRCMDINT);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc_run_qoutfifo(ahc);
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
if ((ahc->flags & AHC_TARGETMODE) != 0) {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
ahc_run_tqinfifo(ahc, /*paused*/FALSE);
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if (intstat & BRKADRINT) {
/*
* We upset the sequencer :-(
* Lookup the error message
*/
int i, error, num_errors;
error = ahc_inb(ahc, ERROR);
num_errors = sizeof(hard_error)/sizeof(hard_error[0]);
for (i = 0; error != 1 && i < num_errors; i++)
error >>= 1;
panic("%s: brkadrint, %s at seqaddr = 0x%x\n",
ahc_name(ahc), hard_error[i].errmesg,
ahc_inb(ahc, SEQADDR0) |
(ahc_inb(ahc, SEQADDR1) << 8));
/* Tell everyone that this HBA is no longer availible */
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
CAM_NO_HBA);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if (intstat & SEQINT)
ahc_handle_seqint(ahc, intstat);
if (intstat & SCSIINT)
ahc_handle_scsiint(ahc, intstat);
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
static struct tmode_tstate *
ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
{
struct tmode_tstate *master_tstate;
struct tmode_tstate *tstate;
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
int i, s;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
master_tstate = ahc->enabled_targets[ahc->our_id];
if (channel == 'B') {
scsi_id += 8;
master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
}
if (ahc->enabled_targets[scsi_id] != NULL
&& ahc->enabled_targets[scsi_id] != master_tstate)
panic("%s: ahc_alloc_tstate - Target already allocated",
ahc_name(ahc));
tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
if (tstate == NULL)
return (NULL);
/*
* If we have allocated a master tstate, copy user settings from
* the master tstate (taken from SRAM or the EEPROM) for this
* channel, but reset our current and goal settings to async/narrow
* until an initiator talks to us.
*/
if (master_tstate != NULL) {
bcopy(master_tstate, tstate, sizeof(*tstate));
bzero(tstate->enabled_luns, sizeof(tstate->enabled_luns));
tstate->ultraenb = 0;
for (i = 0; i < 16; i++) {
bzero(&tstate->transinfo[i].current,
sizeof(tstate->transinfo[i].current));
bzero(&tstate->transinfo[i].goal,
sizeof(tstate->transinfo[i].goal));
}
} else
bzero(tstate, sizeof(*tstate));
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
s = splcam();
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc->enabled_targets[scsi_id] = tstate;
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
splx(s);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
return (tstate);
}
static void
ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
{
struct tmode_tstate *tstate;
/* Don't clean up the entry for our initiator role */
if ((ahc->flags & AHC_INITIATORMODE) != 0
&& ((channel == 'B' && scsi_id == ahc->our_id_b)
|| (channel == 'A' && scsi_id == ahc->our_id))
&& force == FALSE)
return;
if (channel == 'B')
scsi_id += 8;
tstate = ahc->enabled_targets[scsi_id];
if (tstate != NULL)
free(tstate, M_DEVBUF);
ahc->enabled_targets[scsi_id] = NULL;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
{
struct tmode_tstate *tstate;
struct tmode_lstate *lstate;
struct ccb_en_lun *cel;
cam_status status;
int target;
int lun;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
u_int target_mask;
char channel;
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
int s;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
/* notfound_failure*/FALSE);
if (status != CAM_REQ_CMP) {
ccb->ccb_h.status = status;
return;
}
cel = &ccb->cel;
target = ccb->ccb_h.target_id;
lun = ccb->ccb_h.target_lun;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
channel = SIM_CHANNEL(ahc, sim);
target_mask = 0x01 << target;
if (channel == 'B')
target_mask <<= 8;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if (cel->enable != 0) {
u_int scsiseq;
/* Are we already enabled?? */
if (lstate != NULL) {
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
xpt_print_path(ccb->ccb_h.path);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
printf("Lun already enabled\n");
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
return;
}
if (cel->grp6_len != 0
|| cel->grp7_len != 0) {
/*
* Don't (yet?) support vendor
* specific commands.
*/
ccb->ccb_h.status = CAM_REQ_INVALID;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
printf("Non-zero Group Codes\n");
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
return;
}
/*
* Seems to be okay.
* Setup our data structures.
*/
if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tstate = ahc_alloc_tstate(ahc, target, channel);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if (tstate == NULL) {
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
xpt_print_path(ccb->ccb_h.path);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
printf("Couldn't allocate tstate\n");
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
return;
}
}
lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
if (lstate == NULL) {
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
xpt_print_path(ccb->ccb_h.path);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
printf("Couldn't allocate lstate\n");
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
return;
}
bzero(lstate, sizeof(*lstate));
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
status = xpt_create_path(&lstate->path, /*periph*/NULL,
xpt_path_path_id(ccb->ccb_h.path),
xpt_path_target_id(ccb->ccb_h.path),
xpt_path_lun_id(ccb->ccb_h.path));
if (status != CAM_REQ_CMP) {
free(lstate, M_DEVBUF);
xpt_print_path(ccb->ccb_h.path);
printf("Couldn't allocate path\n");
ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
return;
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
SLIST_INIT(&lstate->accept_tios);
SLIST_INIT(&lstate->immed_notifies);
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
s = splcam();
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
pause_sequencer(ahc);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if (target != CAM_TARGET_WILDCARD) {
tstate->enabled_luns[lun] = lstate;
ahc->enabled_luns++;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((ahc->features & AHC_MULTI_TID) != 0) {
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
u_int targid_mask;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
targid_mask = ahc_inb(ahc, TARGID)
| (ahc_inb(ahc, TARGID + 1) << 8);
targid_mask |= target_mask;
ahc_outb(ahc, TARGID, targid_mask);
ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
ahc_update_scsiid(ahc, targid_mask);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
} else {
int our_id;
char channel;
channel = SIM_CHANNEL(ahc, sim);
our_id = SIM_SCSI_ID(ahc, sim);
/*
* This can only happen if selections
* are not enabled
*/
if (target != our_id) {
u_int sblkctl;
char cur_channel;
int swap;
sblkctl = ahc_inb(ahc, SBLKCTL);
cur_channel = (sblkctl & SELBUSB)
? 'B' : 'A';
if ((ahc->features & AHC_TWIN) == 0)
cur_channel = 'A';
swap = cur_channel != channel;
if (channel == 'A')
ahc->our_id = target;
else
ahc->our_id_b = target;
if (swap)
ahc_outb(ahc, SBLKCTL,
sblkctl ^ SELBUSB);
ahc_outb(ahc, SCSIID, target);
if (swap)
ahc_outb(ahc, SBLKCTL, sblkctl);
}
}
} else
ahc->black_hole = lstate;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
/* Allow select-in operations */
if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
scsiseq |= ENSELI;
ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
scsiseq = ahc_inb(ahc, SCSISEQ);
scsiseq |= ENSELI;
ahc_outb(ahc, SCSISEQ, scsiseq);
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
splx(s);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_print_path(ccb->ccb_h.path);
printf("Lun now enabled for target mode\n");
} else {
struct ccb_hdr *elm;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
int i, empty;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if (lstate == NULL) {
ccb->ccb_h.status = CAM_LUN_INVALID;
return;
}
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
s = splcam();
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ccb->ccb_h.status = CAM_REQ_CMP;
LIST_FOREACH(elm, &ahc->pending_ccbs, sim_links.le) {
if (elm->func_code == XPT_CONT_TARGET_IO
&& !xpt_path_comp(elm->path, ccb->ccb_h.path)){
printf("CTIO pending\n");
ccb->ccb_h.status = CAM_REQ_INVALID;
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
splx(s);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
return;
}
}
if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
printf("ATIOs pending\n");
ccb->ccb_h.status = CAM_REQ_INVALID;
}
if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
printf("INOTs pending\n");
ccb->ccb_h.status = CAM_REQ_INVALID;
}
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if (ccb->ccb_h.status != CAM_REQ_CMP) {
splx(s);
return;
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
xpt_print_path(ccb->ccb_h.path);
printf("Target mode disabled\n");
xpt_free_path(lstate->path);
free(lstate, M_DEVBUF);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
pause_sequencer(ahc);
/* Can we clean up the target too? */
if (target != CAM_TARGET_WILDCARD) {
tstate->enabled_luns[lun] = NULL;
ahc->enabled_luns--;
for (empty = 1, i = 0; i < 8; i++)
if (tstate->enabled_luns[i] != NULL) {
empty = 0;
break;
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if (empty) {
ahc_free_tstate(ahc, target, channel,
/*force*/FALSE);
if (ahc->features & AHC_MULTI_TID) {
u_int targid_mask;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
targid_mask = ahc_inb(ahc, TARGID)
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
| (ahc_inb(ahc, TARGID + 1)
<< 8);
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
targid_mask &= ~target_mask;
ahc_outb(ahc, TARGID, targid_mask);
ahc_outb(ahc, TARGID+1,
(targid_mask >> 8));
ahc_update_scsiid(ahc, targid_mask);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
}
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
}
} else {
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
ahc->black_hole = NULL;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
/*
* We can't allow selections without
* our black hole device.
*/
empty = TRUE;
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
}
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if (ahc->enabled_luns == 0) {
/* Disallow select-in */
u_int scsiseq;
scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
scsiseq &= ~ENSELI;
ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
scsiseq = ahc_inb(ahc, SCSISEQ);
scsiseq &= ~ENSELI;
ahc_outb(ahc, SCSISEQ, scsiseq);
}
unpause_sequencer(ahc);
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
splx(s);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
}
}
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
static void
ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
{
u_int scsiid_mask;
u_int scsiid;
if ((ahc->features & AHC_MULTI_TID) == 0)
panic("ahc_update_scsiid called on non-multitid unit\n");
/*
* Since we will rely on the the TARGID mask
* for selection enables, ensure that OID
* in SCSIID is not set to some other ID
* that we don't want to allow selections on.
*/
if ((ahc->features & AHC_ULTRA2) != 0)
scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
else
scsiid = ahc_inb(ahc, SCSIID);
scsiid_mask = 0x1 << (scsiid & OID);
if ((targid_mask & scsiid_mask) == 0) {
u_int our_id;
/* ffs counts from 1 */
our_id = ffs(targid_mask);
if (our_id == 0)
our_id = ahc->our_id;
else
our_id--;
scsiid &= TID;
scsiid |= our_id;
}
if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
else
ahc_outb(ahc, SCSIID, scsiid);
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
static int
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
struct tmode_tstate *tstate;
struct tmode_lstate *lstate;
struct ccb_accept_tio *atio;
u_int8_t *byte;
int initiator;
int target;
int lun;
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
initiator = cmd->initiator_channel >> 4;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
target = cmd->targ_id;
lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
byte = cmd->bytes;
tstate = ahc->enabled_targets[target];
lstate = NULL;
if (tstate != NULL && lun < 8)
lstate = tstate->enabled_luns[lun];
/*
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
* Commands for disabled luns go to the black hole driver.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if (lstate == NULL)
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
lstate = ahc->black_hole;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (atio == NULL) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc->flags |= AHC_TQINFIFO_BLOCKED;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
/*
* Wait for more ATIOs from the peripheral driver for this lun.
*/
return (1);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
} else
ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
#if 0
printf("Incoming command from %d for %d:%d%s\n",
initiator, target, lun,
lstate == ahc->black_hole ? "(Black Holed)" : "");
#endif
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (lstate == ahc->black_hole) {
/* Fill in the wildcards */
atio->ccb_h.target_id = target;
atio->ccb_h.target_lun = lun;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Package it up and send it off to
* whomever has this lun enabled.
*/
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
atio->sense_len = 0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
atio->init_id = initiator;
if (byte[0] != 0xFF) {
/* Tag was included */
atio->tag_action = *byte++;
atio->tag_id = *byte++;
atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
} else {
byte++;
atio->ccb_h.flags = 0;
}
/* Okay. Now determine the cdb size based on the command code */
switch (*byte >> CMD_GROUP_CODE_SHIFT) {
case 0:
atio->cdb_len = 6;
break;
case 1:
case 2:
atio->cdb_len = 10;
break;
case 4:
atio->cdb_len = 16;
break;
case 5:
atio->cdb_len = 12;
break;
case 3:
default:
/* Only copy the opcode. */
atio->cdb_len = 1;
printf("Reserved or VU command code type encountered\n");
break;
}
bcopy(byte, atio->cdb_io.cdb_bytes, atio->cdb_len);
atio->ccb_h.status |= CAM_CDB_RECVD;
if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
/*
* We weren't allowed to disconnect.
* We're hanging on the bus until a
* continue target I/O comes in response
* to this accept tio.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
#if 0
printf("Received Immediate Command %d:%d:%d - %p\n",
initiator, target, lun, ahc->pending_device);
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc->pending_device = lstate;
}
xpt_done((union ccb*)atio);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
return (0);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
struct scb *scb;
struct ahc_devinfo devinfo;
ahc_fetch_devinfo(ahc, &devinfo);
/*
* Clear the upper byte that holds SEQINT status
* codes and clear the SEQINT bit. We will unpause
* the sequencer, if appropriate, after servicing
* the request.
*/
ahc_outb(ahc, CLRINT, CLRSEQINT);
switch (intstat & SEQINT_MASK) {
case NO_MATCH:
{
/* Ensure we don't leave the selection hardware on */
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("%s:%c:%d: no active SCB for reconnecting "
"target - issuing BUS DEVICE RESET\n",
ahc_name(ahc), devinfo.channel, devinfo.target);
printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n",
ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1),
ahc_inb(ahc, SEQ_FLAGS));
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
ahc->msgout_len = 1;
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
ahc_outb(ahc, MSG_OUT, HOST_MSG);
ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
Better workaround for aic7890 chip bug. Use the HS_MAILBOX register to tell the sequencer to pause itself for a target msg variable update. This avoids the pause race entirely as HS_MAILBOX can be accessed without pausing the chip. 3.2 Merge candidate.
1999-05-14 05:07:25 +00:00
case UPDATE_TMSG_REQ:
ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF);
ahc_outb(ahc, TARGET_MSG_REQUEST + 1,
(ahc->targ_msg_req >> 8) & 0xFF);
ahc_outb(ahc, HS_MAILBOX, 0);
break;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
case SEND_REJECT:
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int rejbyte = ahc_inb(ahc, ACCUM);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("%s:%c:%d: Warning - unknown message received from "
"target (0x%x). Rejecting\n",
ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
break;
}
case NO_IDENT:
{
/*
* The reconnecting target either did not send an identify
* message, or did, but we didn't find and SCB to match and
* before it could respond to our ATN/abort, it hit a dataphase.
* The only safe thing to do is to blow it away with a bus
* reset.
*/
int found;
printf("%s:%c:%d: Target did not send an IDENTIFY message. "
"LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n",
ahc_name(ahc), devinfo.channel, devinfo.target,
ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL));
found = ahc_reset_channel(ahc, devinfo.channel,
/*initiate reset*/TRUE);
printf("%s: Issued Channel %c Bus Reset. "
"%d SCBs aborted\n", ahc_name(ahc), devinfo.channel,
found);
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
return;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
case BAD_PHASE:
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
{
u_int lastphase;
lastphase = ahc_inb(ahc, LASTPHASE);
if (lastphase == P_BUSFREE) {
printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n",
ahc_name(ahc), devinfo.channel, devinfo.target,
ahc_inb(ahc, SCSISIGI));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
restart_sequencer(ahc);
return;
} else {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
printf("%s:%c:%d: unknown scsi bus phase %x. "
"Attempting to continue\n",
ahc_name(ahc), devinfo.channel, devinfo.target,
ahc_inb(ahc, SCSISIGI));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
break;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
case BAD_STATUS:
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int scb_index;
struct hardware_scb *hscb;
struct ccb_scsiio *csio;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* The sequencer will notify us when a command
* has an error that would be of interest to
* the kernel. This allows us to leave the sequencer
* running in the common case of command completes
* without error. The sequencer will already have
* dma'd the SCB back up to us, so we can reference
* the in kernel copy directly.
*/
scb_index = ahc_inb(ahc, SCB_TAG);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scb_index];
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Set the default return value to 0 (don't
* send sense). The sense code will change
* this if needed.
*/
ahc_outb(ahc, RETURN_1, 0);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
if (!(scb_index < ahc->scb_data->numscbs
&& (scb->flags & SCB_ACTIVE) != 0)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("%s:%c:%d: ahc_intr - referenced scb "
"not valid during seqint 0x%x scb(%d)\n",
ahc_name(ahc), devinfo.channel,
devinfo.target, intstat, scb_index);
goto unpause;
}
Don't reference our SCB until we have validated that the firmware has returned an SCB that is in range.
1999-05-23 18:55:58 +00:00
hscb = scb->hscb;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Don't want to clobber the original sense code */
if ((scb->flags & SCB_SENSE) != 0) {
/*
* Clear the SCB_SENSE Flag and have
* the sequencer do a normal command
* complete.
*/
scb->flags &= ~SCB_SENSE;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scb->ccb, CAM_AUTOSENSE_FAIL);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scb->ccb, CAM_SCSI_STATUS_ERROR);
Correct an invalid (and unused) #define in 93cx6.c Freeze the transaction queue for any type of scsi status other than "okay".
1999-04-07 23:02:45 +00:00
/* Freeze the queue unit the client sees the error. */
ahc_freeze_devq(ahc, scb->ccb->ccb_h.path);
ahc_freeze_ccb(scb->ccb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
csio = &scb->ccb->csio;
csio->scsi_status = hscb->status;
switch (hscb->status) {
case SCSI_STATUS_OK:
printf("%s: Interrupted for staus of 0???\n",
ahc_name(ahc));
break;
case SCSI_STATUS_CMD_TERMINATED:
case SCSI_STATUS_CHECK_COND:
#ifdef AHC_DEBUG
if (ahc_debug & AHC_SHOWSENSE) {
xpt_print_path(csio->ccb_h.path);
printf("SCB %d: requests Check Status\n",
scb->hscb->tag);
}
#endif
if ((csio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
struct ahc_dma_seg *sg;
struct scsi_sense *sc;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
sg = scb->sg_list;
sc = (struct scsi_sense *)(&hscb->cmdstore);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Save off the residual if there is one.
*/
if (hscb->residual_SG_count != 0)
ahc_calc_residual(scb);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
else
scb->ccb->csio.resid = 0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#ifdef AHC_DEBUG
if (ahc_debug & AHC_SHOWSENSE) {
xpt_print_path(csio->ccb_h.path);
printf("Sending Sense\n");
}
#endif
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
sg->addr = ahc->scb_data->sense_busaddr
+ (hscb->tag*sizeof(struct scsi_sense_data));
sg->len = MIN(sizeof(struct scsi_sense_data),
csio->sense_len);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
sc->opcode = REQUEST_SENSE;
sc->byte2 = SCB_LUN(scb) << 5;
sc->unused[0] = 0;
sc->unused[1] = 0;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
sc->length = sg->len;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
sc->control = 0;
/*
* Would be nice to preserve DISCENB here,
* but due to the way we page SCBs, we can't.
*/
hscb->control = 0;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* This request sense could be because the
* the device lost power or in some other
* way has lost our transfer negotiations.
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
* Renegotiate if appropriate. Unit attention
* errors will be reported before any data
* phases occur.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc_calc_residual(scb);
if (scb->ccb->csio.resid
== scb->ccb->csio.dxfer_len) {
tinfo = ahc_fetch_transinfo(ahc,
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
devinfo.channel,
devinfo.our_scsiid,
devinfo.target,
&tstate);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc_update_target_msg_request(ahc,
&devinfo,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
tinfo,
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
/*force*/TRUE,
/*paused*/TRUE);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
hscb->status = 0;
hscb->SG_count = 1;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
hscb->SG_pointer = scb->sg_list_phys;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
hscb->data = sg->addr;
hscb->datalen = sg->len;
hscb->cmdpointer = hscb->cmdstore_busaddr;
hscb->cmdlen = sizeof(*sc);
scb->sg_count = hscb->SG_count;
scb->flags |= SCB_SENSE;
/*
* Ensure the target is busy since this
* will be an untagged request.
*/
ahc_busy_tcl(ahc, scb);
ahc_outb(ahc, RETURN_1, SEND_SENSE);
/*
* Ensure we have enough time to actually
* retrieve the sense.
*/
untimeout(ahc_timeout, (caddr_t)scb,
scb->ccb->ccb_h.timeout_ch);
scb->ccb->ccb_h.timeout_ch =
timeout(ahc_timeout, (caddr_t)scb, 5 * hz);
}
break;
case SCSI_STATUS_BUSY:
case SCSI_STATUS_QUEUE_FULL:
/*
* Requeue any transactions that haven't been
* sent yet.
*/
ahc_freeze_devq(ahc, scb->ccb->ccb_h.path);
ahc_freeze_ccb(scb->ccb);
break;
}
break;
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
case TRACE_POINT:
{
printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2),
ahc_inb(ahc, DFCNTRL));
printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3),
ahc_inb(ahc, DFSTATUS));
printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n",
ahc_inb(ahc, SSTAT0),
ahc_inb(ahc, SCB_DATACNT));
break;
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
case HOST_MSG_LOOP:
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
/*
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
* The sequencer has encountered a message phase
* that requires host assistance for completion.
* While handling the message phase(s), we will be
* notified by the sequencer after each byte is
* transfered so we can track bus phases.
*
* If this is the first time we've seen a HOST_MSG_LOOP,
* initialize the state of the host message loop.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc->msg_type == MSG_TYPE_NONE) {
u_int bus_phase;
bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (bus_phase != P_MESGIN
&& bus_phase != P_MESGOUT) {
printf("ahc_intr: HOST_MSG_LOOP bad "
"phase 0x%x\n",
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
bus_phase);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/*
* Probably transitioned to bus free before
* we got here. Just punt the message.
*/
ahc_clear_intstat(ahc);
restart_sequencer(ahc);
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (devinfo.role == ROLE_INITIATOR) {
struct scb *scb;
u_int scb_index;
scb_index = ahc_inb(ahc, SCB_TAG);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scb_index];
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (bus_phase == P_MESGOUT)
ahc_setup_initiator_msgout(ahc,
&devinfo,
scb);
else {
ahc->msg_type =
MSG_TYPE_INITIATOR_MSGIN;
ahc->msgin_index = 0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
} else {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (bus_phase == P_MESGOUT) {
ahc->msg_type =
MSG_TYPE_TARGET_MSGOUT;
ahc->msgin_index = 0;
} else
/* XXX Ever executed??? */
ahc_setup_target_msgin(ahc, &devinfo);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* Pass a NULL path so that handlers generate their own */
ahc_handle_message_phase(ahc, /*path*/NULL);
break;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
case PERR_DETECTED:
{
/*
* If we've cleared the parity error interrupt
* but the sequencer still believes that SCSIPERR
* is true, it must be that the parity error is
* for the currently presented byte on the bus,
* and we are not in a phase (data-in) where we will
* eventually ack this byte. Ack the byte and
* throw it away in the hope that the target will
* take us to message out to deliver the appropriate
* error message.
*/
if ((intstat & SCSIINT) == 0
&& (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
u_int curphase;
/*
* The hardware will only let you ack bytes
* if the expected phase in SCSISIGO matches
* the current phase. Make sure this is
* currently the case.
*/
curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
ahc_outb(ahc, LASTPHASE, curphase);
ahc_outb(ahc, SCSISIGO, curphase);
ahc_inb(ahc, SCSIDATL);
}
break;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
case DATA_OVERRUN:
{
/*
* When the sequencer detects an overrun, it
* places the controller in "BITBUCKET" mode
* and allows the target to complete its transfer.
* Unfortunately, none of the counters get updated
* when the controller is in this mode, so we have
* no way of knowing how large the overrun was.
*/
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int scbindex = ahc_inb(ahc, SCB_TAG);
u_int lastphase = ahc_inb(ahc, LASTPHASE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
int i;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scbindex];
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
for (i = 0; i < num_phases; i++) {
if (lastphase == phase_table[i].phase)
break;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_print_path(scb->ccb->ccb_h.path);
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
printf("data overrun detected %s."
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
" Tag == 0x%x.\n",
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
phase_table[i].phasemsg,
scb->hscb->tag);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_print_path(scb->ccb->ccb_h.path);
printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n",
ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
scb->ccb->csio.dxfer_len, scb->sg_count);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (scb->sg_count > 0) {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
for (i = 0; i < scb->sg_count; i++) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
printf("sg[%d] - Addr 0x%x : Length %d\n",
i,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb->sg_list[i].addr,
scb->sg_list[i].len);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
/*
* Set this and it will take affect when the
* target does a command complete.
*/
ahc_freeze_devq(ahc, scb->ccb->ccb_h.path);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scb->ccb, CAM_DATA_RUN_ERR);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_freeze_ccb(scb->ccb);
break;
}
case TRACEPOINT:
{
printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2));
#if 0
printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1));
printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0));
printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI));
printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n",
ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT));
printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG));
printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n",
ahc_inb(ahc, CCHADDR)
| (ahc_inb(ahc, CCHADDR+1) << 8)
| (ahc_inb(ahc, CCHADDR+2) << 16)
| (ahc_inb(ahc, CCHADDR+3) << 24),
ahc_inb(ahc, CCHCNT)
| (ahc_inb(ahc, CCHCNT+1) << 8)
| (ahc_inb(ahc, CCHCNT+2) << 16),
ahc_inb(ahc, SCBPTR));
printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH));
printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG));
#endif
break;
}
#if NOT_YET
/* XXX Fill these in later */
case MESG_BUFFER_BUSY:
break;
case MSGIN_PHASEMIS:
break;
#endif
default:
printf("ahc_intr: seqint, "
"intstat == 0x%x, scsisigi = 0x%x\n",
intstat, ahc_inb(ahc, SCSISIGI));
break;
}
unpause:
/*
* The sequencer is paused immediately on
* a SEQINT, so we should restart it when
* we're done.
*/
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int scb_index;
u_int status;
struct scb *scb;
-Wunused cleanup. Correct a problem where an external bus reset on the 'background' channel of a Twin Channel EISA controller could put the driver into an infinite loop. Noticed by: Twin Channel bug, Joerg Wunsch <joerg@FreeBSD.org> Submitted by: -Wunused, Poul-Henning Kamp <phk@freebsd.org>
1998-10-15 23:49:27 +00:00
char cur_channel;
char intr_channel;
if ((ahc->features & AHC_TWIN) != 0
&& ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
cur_channel = 'B';
else
cur_channel = 'A';
intr_channel = cur_channel;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
status = ahc_inb(ahc, SSTAT1);
-Wunused cleanup. Correct a problem where an external bus reset on the 'background' channel of a Twin Channel EISA controller could put the driver into an infinite loop. Noticed by: Twin Channel bug, Joerg Wunsch <joerg@FreeBSD.org> Submitted by: -Wunused, Poul-Henning Kamp <phk@freebsd.org>
1998-10-15 23:49:27 +00:00
if (status == 0) {
if ((ahc->features & AHC_TWIN) != 0) {
/* Try the other channel */
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
status = ahc_inb(ahc, SSTAT1);
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
intr_channel = (cur_channel == 'A') ? 'B' : 'A';
}
if (status == 0) {
printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
return;
}
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
-Wunused cleanup. Correct a problem where an external bus reset on the 'background' channel of a Twin Channel EISA controller could put the driver into an infinite loop. Noticed by: Twin Channel bug, Joerg Wunsch <joerg@FreeBSD.org> Submitted by: -Wunused, Poul-Henning Kamp <phk@freebsd.org>
1998-10-15 23:49:27 +00:00
scb_index = ahc_inb(ahc, SCB_TAG);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (scb_index < ahc->scb_data->numscbs) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scb_index];
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if ((scb->flags & SCB_ACTIVE) == 0
|| (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scb = NULL;
} else
scb = NULL;
if ((status & SCSIRSTI) != 0) {
printf("%s: Someone reset channel %c\n",
-Wunused cleanup. Correct a problem where an external bus reset on the 'background' channel of a Twin Channel EISA controller could put the driver into an infinite loop. Noticed by: Twin Channel bug, Joerg Wunsch <joerg@FreeBSD.org> Submitted by: -Wunused, Poul-Henning Kamp <phk@freebsd.org>
1998-10-15 23:49:27 +00:00
ahc_name(ahc), intr_channel);
ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
} else if ((status & SCSIPERR) != 0) {
/*
* Determine the bus phase and queue an appropriate message.
* SCSIPERR is latched true as soon as a parity error
* occurs. If the sequencer acked the transfer that
* caused the parity error and the currently presented
* transfer on the bus has correct parity, SCSIPERR will
* be cleared by CLRSCSIPERR. Use this to determine if
* we should look at the last phase the sequencer recorded,
* or the current phase presented on the bus.
*/
u_int mesg_out;
u_int curphase;
u_int errorphase;
u_int lastphase;
int i;
lastphase = ahc_inb(ahc, LASTPHASE);
curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
/*
* For all phases save DATA, the sequencer won't
* automatically ack a byte that has a parity error
* in it. So the only way that the current phase
* could be 'data-in' is if the parity error is for
* an already acked byte in the data phase. During
* synchronous data-in transfers, we may actually
* ack bytes before latching the current phase in
* LASTPHASE, leading to the discrepancy between
* curphase and lastphase.
*/
if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
|| curphase == P_DATAIN)
errorphase = curphase;
else
errorphase = lastphase;
for (i = 0; i < num_phases; i++) {
if (errorphase == phase_table[i].phase)
break;
}
mesg_out = phase_table[i].mesg_out;
if (scb != NULL)
xpt_print_path(scb->ccb->ccb_h.path);
else
printf("%s:%c:%d: ", ahc_name(ahc),
intr_channel,
TCL_TARGET(ahc_inb(ahc, SAVED_TCL)));
printf("parity error detected %s. "
"SEQADDR(0x%x) SCSIRATE(0x%x)\n",
phase_table[i].phasemsg,
ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8),
ahc_inb(ahc, SCSIRATE));
/*
* We've set the hardware to assert ATN if we
* get a parity error on "in" phases, so all we
* need to do is stuff the message buffer with
* the appropriate message. "In" phases have set
* mesg_out to something other than MSG_NOP.
*/
if (mesg_out != MSG_NOOP) {
if (ahc->msg_type != MSG_TYPE_NONE)
ahc->send_msg_perror = TRUE;
else
ahc_outb(ahc, MSG_OUT, mesg_out);
}
ahc_outb(ahc, CLRINT, CLRSCSIINT);
unpause_sequencer(ahc);
} else if ((status & BUSFREE) != 0
&& (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* First look at what phase we were last in.
* If its message out, chances are pretty good
* that the busfree was in response to one of
* our abort requests.
*/
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int lastphase = ahc_inb(ahc, LASTPHASE);
u_int saved_tcl = ahc_inb(ahc, SAVED_TCL);
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
u_int target = TCL_TARGET(saved_tcl);
u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl);
char channel = TCL_CHANNEL(ahc, saved_tcl);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
int printerror = 1;
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
if (lastphase == P_MESGOUT) {
u_int message;
u_int tag;
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
message = ahc->msgout_buf[ahc->msgout_index - 1];
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
tag = SCB_LIST_NULL;
switch (message) {
case MSG_ABORT_TAG:
tag = scb->hscb->tag;
/* FALLTRHOUGH */
case MSG_ABORT:
xpt_print_path(scb->ccb->ccb_h.path);
printf("SCB %d - Abort %s Completed.\n",
Fix compile warnings.
1998-09-16 03:26:10 +00:00
scb->hscb->tag, tag == SCB_LIST_NULL ?
"" : "Tag");
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
ahc_abort_scbs(ahc, target, channel,
TCL_LUN(saved_tcl), tag,
ROLE_INITIATOR,
CAM_REQ_ABORTED);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printerror = 0;
break;
case MSG_BUS_DEV_RESET:
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
{
struct ahc_devinfo devinfo;
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
/*
* Don't mark the user's request for this BDR
* as completing with CAM_BDR_SENT. CAM3
* specifies CAM_REQ_CMP.
*/
if (scb != NULL
&& scb->ccb->ccb_h.func_code == XPT_RESET_DEV
&& ahc_match_scb(scb, target, channel,
TCL_LUN(saved_tcl),
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
SCB_LIST_NULL,
ROLE_INITIATOR)) {
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
ahcsetccbstatus(scb->ccb, CAM_REQ_CMP);
}
Use TCL_CHANNEL/SCSI_ID/etc. macros in more locations. Don't mess with the IRQMS bit in the host control register unless we are an aic7770 chip. Use calling context to determine if the card is already paused when we update the target message request bit field in controller scratch ram. Looking at the paused bit in the HCNTRL register opened up a race condition. Insert delays in the target message request update routine as a temporary work around for what looks like a chip bug. I'm still investigating this one. Fix the Abort/Abort Tag/BDR handler to pull its message from the message buffer in our softc instead of attempting to get it from a register on the controller. The message is never recorded by the controller in the new message scheme. Don't rely on having an SCB when a BDR occurs. We can issue these during invalid reconnects to. Fix a few cases where we were restarting the sequencer but then still falling out of a switch statement to unpause the sequencer again. This could cause us to mess up sequencer state if it generated another pausing interrupt between the time of the restart and unpause. Kill the 'transceiver settle' loop during card initialization. I failed to realize that a controller that is not connected to any cables will never settle or enable the SCSI transceivers at all. The correct solution is to monitor the IOERR interrupt which indicates that the transceiver state has changed (UW<->LVD). Modify the aic7xxx assembler to properly echo input when stdin is not a tty.
1999-03-23 07:24:29 +00:00
ahc_compile_devinfo(&devinfo,
initiator_role_id,
target,
TCL_LUN(saved_tcl),
channel,
ROLE_INITIATOR);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_handle_devreset(ahc, &devinfo,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
CAM_BDR_SENT, AC_SENT_BDR,
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
"Bus Device Reset",
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
/*verbose_level*/0);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printerror = 0;
break;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
default:
break;
}
}
if (printerror != 0) {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
int i;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (scb != NULL) {
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int tag;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((scb->hscb->control & TAG_ENB) != 0)
tag = scb->hscb->tag;
else
tag = SCB_LIST_NULL;
ahc_abort_scbs(ahc, target, channel,
SCB_LUN(scb), tag,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ROLE_INITIATOR,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
CAM_UNEXP_BUSFREE);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
xpt_print_path(scb->ccb->ccb_h.path);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
/*
* We had not fully identified this connection,
* so we cannot abort anything.
*/
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("%s: ", ahc_name(ahc));
}
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
for (i = 0; i < num_phases; i++) {
if (lastphase == phase_table[i].phase)
break;
}
printf("Unexpected busfree %s\n"
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
"SEQADDR == 0x%x\n",
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
| (ahc_inb(ahc, SEQADDR1) << 8));
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_clear_msg_state(ahc);
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, CLRINT, CLRSCSIINT);
restart_sequencer(ahc);
} else if ((status & SELTO) != 0) {
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int scbptr;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scbptr = ahc_inb(ahc, WAITING_SCBH);
ahc_outb(ahc, SCBPTR, scbptr);
scb_index = ahc_inb(ahc, SCB_TAG);
if (scb_index < ahc->scb_data->numscbs) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scb_index];
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((scb->flags & SCB_ACTIVE) == 0)
scb = NULL;
} else
scb = NULL;
if (scb == NULL) {
printf("%s: ahc_intr - referenced scb not "
"valid during SELTO scb(%d, %d)\n",
ahc_name(ahc), scbptr, scb_index);
} else {
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
u_int tag;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
tag = SCB_LIST_NULL;
if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0)
tag = scb->hscb->tag;
ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb),
SCB_LUN(scb), tag,
ROLE_INITIATOR, CAM_SEL_TIMEOUT);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
/* Stop the selection */
ahc_outb(ahc, SCSISEQ, 0);
Clear the SELINGO bit after a selection timeout occurs. SELINGO is usually cleared by a successful selection, but there is no guarantee that a future successful selection will ever occur (e.g. empty bus). The driver never looks at SELINGO, but the busy LED does, so this change has the cosmetic effect of fixing the rare instance where the busy LED was left on, confusing the user.
1999-09-20 19:04:22 +00:00
/* No more pending messages */
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_clear_msg_state(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Clear the SELINGO bit after a selection timeout occurs. SELINGO is usually cleared by a successful selection, but there is no guarantee that a future successful selection will ever occur (e.g. empty bus). The driver never looks at SELINGO, but the busy LED does, so this change has the cosmetic effect of fixing the rare instance where the busy LED was left on, confusing the user.
1999-09-20 19:04:22 +00:00
/*
* Although the driver does not care about the
* 'Selection in Progress' status bit, the busy
* LED does. SELINGO is only cleared by a sucessful
* selection, so we must manually clear it to ensure
* the LED turns off just incase no future successful
* selections occur (e.g. no devices on the bus).
*/
ahc_outb(ahc, CLRSINT0, CLRSELINGO);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Clear the SELINGO bit after a selection timeout occurs. SELINGO is usually cleared by a successful selection, but there is no guarantee that a future successful selection will ever occur (e.g. empty bus). The driver never looks at SELINGO, but the busy LED does, so this change has the cosmetic effect of fixing the rare instance where the busy LED was left on, confusing the user.
1999-09-20 19:04:22 +00:00
/* Clear interrupt state */
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, CLRINT, CLRSCSIINT);
restart_sequencer(ahc);
} else {
xpt_print_path(scb->ccb->ccb_h.path);
printf("Unknown SCSIINT. Status = 0x%x\n", status);
ahc_outb(ahc, CLRSINT1, status);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
}
static void
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
{
/*
* We need to initiate transfer negotiations.
* If our current and goal settings are identical,
* we want to renegotiate due to a check condition.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
int dowide;
int dosync;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
dowide = tinfo->current.width != tinfo->goal.width;
dosync = tinfo->current.period != tinfo->goal.period;
if (!dowide && !dosync) {
dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
dosync = tinfo->goal.period != 0;
}
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
if (dowide) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_construct_wdtr(ahc, tinfo->goal.width);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
} else if (dosync) {
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
struct ahc_syncrate *rate;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
u_int period;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
u_int offset;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
period = tinfo->goal.period;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
rate = ahc_devlimited_syncrate(ahc, &period);
offset = tinfo->goal.offset;
ahc_validate_offset(ahc, rate, &offset,
tinfo->current.width);
ahc_construct_sdtr(ahc, period, offset);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
} else {
panic("ahc_intr: AWAITING_MSG for negotiation, "
"but no negotiation needed\n");
}
}
static void
ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
struct scb *scb)
{
/*
* To facilitate adding multiple messages together,
* each routine should increment the index and len
* variables instead of setting them explicitly.
*/
ahc->msgout_index = 0;
ahc->msgout_len = 0;
if ((scb->flags & SCB_DEVICE_RESET) == 0
&& ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
u_int identify_msg;
identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb);
if ((scb->hscb->control & DISCENB) != 0)
identify_msg |= MSG_IDENTIFY_DISCFLAG;
ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
ahc->msgout_len++;
if ((scb->hscb->control & TAG_ENB) != 0) {
ahc->msgout_buf[ahc->msgout_index++] =
scb->ccb->csio.tag_action;
ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
ahc->msgout_len += 2;
}
}
if (scb->flags & SCB_DEVICE_RESET) {
ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
ahc->msgout_len++;
xpt_print_path(scb->ccb->ccb_h.path);
printf("Bus Device Reset Message Sent\n");
} else if (scb->flags & SCB_ABORT) {
if ((scb->hscb->control & TAG_ENB) != 0)
ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
else
ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
ahc->msgout_len++;
xpt_print_path(scb->ccb->ccb_h.path);
printf("Abort Message Sent\n");
} else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) {
ahc_build_transfer_msg(ahc, devinfo);
} else {
printf("ahc_intr: AWAITING_MSG for an SCB that "
"does not have a waiting message");
panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
"SCB flags = %x", scb->hscb->tag, scb->hscb->control,
ahc_inb(ahc, MSG_OUT), scb->flags);
}
/*
* Clear the MK_MESSAGE flag from the SCB so we aren't
* asked to send this message again.
*/
ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
}
static void
ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
{
/*
* To facilitate adding multiple messages together,
* each routine should increment the index and len
* variables instead of setting them explicitly.
*/
ahc->msgout_index = 0;
ahc->msgout_len = 0;
if ((ahc->targ_msg_req & devinfo->target_mask) != 0)
ahc_build_transfer_msg(ahc, devinfo);
else
panic("ahc_intr: AWAITING target message with no message");
ahc->msgout_index = 0;
ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
}
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
static int
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
{
/*
* What we care about here is if we had an
* outstanding SDTR or WDTR message for this
* target. If we did, this is a signal that
* the target is refusing negotiation.
*/
struct scb *scb;
u_int scb_index;
u_int last_msg;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
int response = 0;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
scb_index = ahc_inb(ahc, SCB_TAG);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scb_index];
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* Might be necessary */
last_msg = ahc_inb(ahc, LAST_MSG);
if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
/* note 8bit xfers */
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
printf("%s:%c:%d: refuses WIDE negotiation. Using "
"8bit transfers\n", ahc_name(ahc),
devinfo->channel, devinfo->target);
ahc_set_width(ahc, devinfo, scb->ccb->ccb_h.path,
MSG_EXT_WDTR_BUS_8_BIT,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
/*paused*/TRUE);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
/*
* No need to clear the sync rate. If the target
* did not accept the command, our syncrate is
* unaffected. If the target started the negotiation,
* but rejected our response, we already cleared the
* sync rate before sending our WDTR.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
devinfo->our_scsiid,
devinfo->target, &tstate);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (tinfo->goal.period) {
u_int period;
/* Start the sync negotiation */
period = tinfo->goal.period;
ahc_devlimited_syncrate(ahc, &period);
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_construct_sdtr(ahc, period, tinfo->goal.offset);
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
ahc->msgout_index = 0;
response = 1;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
}
} else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) {
/* note asynch xfers and clear flag */
ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path,
/*syncrate*/NULL, /*period*/0,
/*offset*/0,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
/*paused*/TRUE);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
printf("%s:%c:%d: refuses synchronous negotiation. "
"Using asynchronous transfers\n",
ahc_name(ahc),
devinfo->channel, devinfo->target);
} else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) {
struct ccb_trans_settings neg;
printf("%s:%c:%d: refuses tagged commands. Performing "
"non-tagged I/O\n", ahc_name(ahc),
devinfo->channel, devinfo->target);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_set_tags(ahc, devinfo, FALSE);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
neg.flags = 0;
neg.valid = CCB_TRANS_TQ_VALID;
xpt_setup_ccb(&neg.ccb_h, scb->ccb->ccb_h.path, /*priority*/1);
xpt_async(AC_TRANSFER_NEG, scb->ccb->ccb_h.path, &neg);
/*
* Resend the identify for this CCB as the target
* may believe that the selection is invalid otherwise.
*/
ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL)
& ~MSG_SIMPLE_Q_TAG);
scb->hscb->control &= ~MSG_SIMPLE_Q_TAG;
scb->ccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO);
/*
* Requeue all tagged commands for this target
* currently in our posession so they can be
* converted to untagged commands.
*/
ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb),
SCB_LUN(scb), /*tag*/SCB_LIST_NULL,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ROLE_INITIATOR, CAM_REQUEUE_REQ,
SEARCH_COMPLETE);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
} else {
/*
* Otherwise, we ignore it.
*/
printf("%s:%c:%d: Message reject for %x -- ignored\n",
ahc_name(ahc), devinfo->channel, devinfo->target,
last_msg);
}
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
return (response);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
}
static void
ahc_clear_msg_state(struct ahc_softc *ahc)
{
ahc->msgout_len = 0;
ahc->msgin_index = 0;
ahc->msg_type = MSG_TYPE_NONE;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
ahc_outb(ahc, MSG_OUT, MSG_NOOP);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
}
static void
ahc_handle_message_phase(struct ahc_softc *ahc, struct cam_path *path)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
struct ahc_devinfo devinfo;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
u_int bus_phase;
int end_session;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_fetch_devinfo(ahc, &devinfo);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
end_session = FALSE;
bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
reswitch:
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
switch (ahc->msg_type) {
case MSG_TYPE_INITIATOR_MSGOUT:
{
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
int lastbyte;
int phasemis;
int msgdone;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc->msgout_len == 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
panic("REQINIT interrupt with no active message");
phasemis = bus_phase != P_MESGOUT;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (phasemis) {
if (bus_phase == P_MESGIN) {
/*
* Change gears and see if
* this messages is of interest to
* us or should be passed back to
* the sequencer.
*/
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
ahc_outb(ahc, CLRSINT1, CLRATNO);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->send_msg_perror = FALSE;
ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
ahc->msgin_index = 0;
goto reswitch;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
end_session = TRUE;
break;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc->send_msg_perror) {
ahc_outb(ahc, CLRSINT1, CLRATNO);
ahc_outb(ahc, CLRSINT1, CLRREQINIT);
ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
break;
}
msgdone = ahc->msgout_index == ahc->msgout_len;
if (msgdone) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
* The target has requested a retry.
* Re-assert ATN, reset our message index to
* 0, and try again.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_index = 0;
ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO);
}
lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
if (lastbyte) {
/* Last byte is signified by dropping ATN */
ahc_outb(ahc, CLRSINT1, CLRATNO);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/*
* Clear our interrupt status and present
* the next byte on the bus.
*/
ahc_outb(ahc, CLRSINT1, CLRREQINIT);
ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
case MSG_TYPE_INITIATOR_MSGIN:
{
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
int phasemis;
int message_done;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
phasemis = bus_phase != P_MESGIN;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (phasemis) {
ahc->msgin_index = 0;
if (bus_phase == P_MESGOUT
&& (ahc->send_msg_perror == TRUE
|| (ahc->msgout_len != 0
&& ahc->msgout_index == 0))) {
ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
goto reswitch;
}
end_session = TRUE;
break;
}
/* Pull the byte in without acking it */
ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
message_done = ahc_parse_msg(ahc, path, &devinfo);
if (message_done) {
/*
* Clear our incoming message buffer in case there
* is another message following this one.
*/
ahc->msgin_index = 0;
/*
* If this message illicited a response,
* assert ATN so the target takes us to the
* message out phase.
*/
if (ahc->msgout_len != 0)
ahc_outb(ahc, SCSISIGO,
ahc_inb(ahc, SCSISIGO) | ATNO);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
} else
ahc->msgin_index++;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* Ack the byte */
ahc_outb(ahc, CLRSINT1, CLRREQINIT);
ahc_inb(ahc, SCSIDATL);
break;
}
case MSG_TYPE_TARGET_MSGIN:
{
int msgdone;
int msgout_request;
if (ahc->msgout_len == 0)
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
panic("Target MSGIN with no active message");
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/*
* If we interrupted a mesgout session, the initiator
* will not know this until our first REQ. So, we
* only honor mesgout requests after we've sent our
* first byte.
*/
if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
&& ahc->msgout_index > 0)
msgout_request = TRUE;
else
msgout_request = FALSE;
if (msgout_request) {
/*
* Change gears and see if
* this messages is of interest to
* us or should be passed back to
* the sequencer.
*/
ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
ahc->msgin_index = 0;
/* Dummy read to REQ for first byte */
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_inb(ahc, SCSIDATL);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | SPIOEN);
break;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
msgdone = ahc->msgout_index == ahc->msgout_len;
if (msgdone) {
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
end_session = TRUE;
break;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/*
* Present the next byte on the bus.
*/
ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
break;
}
case MSG_TYPE_TARGET_MSGOUT:
{
int lastbyte;
int msgdone;
/*
* The initiator signals that this is
* the last byte by dropping ATN.
*/
lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
/*
* Read the latched byte, but turn off SPIOEN first
* so that we don't inadvertantly cause a REQ for the
* next byte.
*/
ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
msgdone = ahc_parse_msg(ahc, path, &devinfo);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (msgdone == MSGLOOP_TERMINATED) {
/*
* The message is *really* done in that it caused
* us to go to bus free. The sequencer has already
* been reset at this point, so pull the ejection
* handle.
*/
return;
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgin_index++;
/*
* XXX Read spec about initiator dropping ATN too soon
* and use msgdone to detect it.
*/
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (msgdone == MSGLOOP_MSGCOMPLETE) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgin_index = 0;
/*
* If this message illicited a response, transition
* to the Message in phase and send it.
*/
if (ahc->msgout_len != 0) {
ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | SPIOEN);
ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
ahc->msgin_index = 0;
break;
}
}
if (lastbyte)
end_session = TRUE;
else {
/* Ask for the next byte. */
ahc_outb(ahc, SXFRCTL0,
ahc_inb(ahc, SXFRCTL0) | SPIOEN);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
default:
panic("Unknown REQINIT message type");
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (end_session) {
ahc_clear_msg_state(ahc);
ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
} else
ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/*
* See if we sent a particular extended message to the target.
* If "full" is true, the target saw the full message.
* If "full" is false, the target saw at least the first
* byte of the message.
*/
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static int
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full)
{
int found;
int index;
found = FALSE;
index = 0;
while (index < ahc->msgout_len) {
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (ahc->msgout_buf[index] == MSG_EXTENDED) {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* Found a candidate */
if (ahc->msgout_buf[index+2] == msgtype) {
u_int end_index;
end_index = index + 1
+ ahc->msgout_buf[index + 1];
if (full) {
if (ahc->msgout_index > end_index)
found = TRUE;
} else if (ahc->msgout_index > index)
found = TRUE;
}
break;
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
} else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG
&& ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
/* Skip tag type and tag id or residue param*/
index += 2;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
} else {
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
/* Single byte message */
index++;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
}
}
return (found);
}
static int
ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
struct ahc_devinfo *devinfo)
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
int reject;
int done;
int response;
u_int targ_scsirate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
done = MSGLOOP_IN_PROG;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
response = FALSE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
reject = FALSE;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
devinfo->target, &tstate);
targ_scsirate = tinfo->scsirate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Parse as much of the message as is availible,
* rejecting it if we don't support it. When
* the entire message is availible and has been
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
* handled, return MSGLOOP_MSGCOMPLETE, indicating
* that we have parsed an entire message.
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
*
* In the case of extended messages, we accept the length
* byte outright and perform more checking once we know the
* extended message type.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
switch (ahc->msgin_buf[0]) {
case MSG_MESSAGE_REJECT:
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
response = ahc_handle_msg_reject(ahc, devinfo);
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
/* FALLTHROUGH */
case MSG_NOOP:
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
done = MSGLOOP_MSGCOMPLETE;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
break;
case MSG_IGN_WIDE_RESIDUE:
{
/* Wait for the whole message */
if (ahc->msgin_index >= 1) {
if (ahc->msgin_buf[1] != 1
|| tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) {
reject = TRUE;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
done = MSGLOOP_MSGCOMPLETE;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
} else
ahc_handle_ign_wide_residue(ahc, devinfo);
}
Add two missing break statements.
1999-01-15 23:24:23 +00:00
break;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
}
case MSG_EXTENDED:
{
/* Wait for enough of the message to begin validation */
if (ahc->msgin_index < 2)
break;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
switch (ahc->msgin_buf[2]) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
case MSG_EXT_SDTR:
{
struct ahc_syncrate *syncrate;
u_int period;
u_int offset;
u_int saved_offset;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
reject = TRUE;
break;
}
/*
* Wait until we have both args before validating
* and acting on this message.
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
*
* Add one to MSG_EXT_SDTR_LEN to account for
* the extended message preamble.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
period = ahc->msgin_buf[3];
saved_offset = offset = ahc->msgin_buf[4];
syncrate = ahc_devlimited_syncrate(ahc, &period);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_validate_offset(ahc, syncrate, &offset,
targ_scsirate & WIDEXFER);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_set_syncrate(ahc, devinfo, path,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
syncrate, period, offset,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
/*paused*/TRUE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* See if we initiated Sync Negotiation
* and didn't have to fall down to async
* transfers.
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* We started it */
if (saved_offset != offset) {
/* Went too low - force async */
reject = TRUE;
}
} else {
/*
* Send our own SDTR in reply
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (bootverbose)
printf("Sending SDTR!\n");
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_construct_sdtr(ahc, period, offset);
ahc->msgout_index = 0;
response = TRUE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
done = MSGLOOP_MSGCOMPLETE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
case MSG_EXT_WDTR:
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int bus_width;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
u_int sending_reply;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
sending_reply = FALSE;
if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
reject = TRUE;
break;
}
/*
* Wait until we have our arg before validating
* and acting on this message.
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
*
* Add one to MSG_EXT_WDTR_LEN to account for
* the extended message preamble.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
bus_width = ahc->msgin_buf[3];
if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Don't send a WDTR back to the
* target, since we asked first.
*/
switch (bus_width){
default:
/*
* How can we do anything greater
* than 16bit transfers on a 16bit
* bus?
*/
reject = TRUE;
printf("%s: target %d requested %dBit "
"transfers. Rejecting...\n",
ahc_name(ahc), devinfo->target,
8 * (0x01 << bus_width));
/* FALLTHROUGH */
case MSG_EXT_WDTR_BUS_8_BIT:
bus_width = MSG_EXT_WDTR_BUS_8_BIT;
break;
case MSG_EXT_WDTR_BUS_16_BIT:
break;
}
} else {
/*
* Send our own WDTR in reply
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (bootverbose)
printf("Sending WDTR!\n");
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
switch (bus_width) {
default:
if (ahc->features & AHC_WIDE) {
/* Respond Wide */
bus_width =
MSG_EXT_WDTR_BUS_16_BIT;
break;
}
/* FALLTHROUGH */
case MSG_EXT_WDTR_BUS_8_BIT:
bus_width = MSG_EXT_WDTR_BUS_8_BIT;
break;
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_index = 0;
ahc->msgout_len = 0;
ahc_construct_wdtr(ahc, bus_width);
ahc->msgout_index = 0;
response = TRUE;
sending_reply = TRUE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_set_width(ahc, devinfo, path, bus_width,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
/*paused*/TRUE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* After a wide message, we are async */
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_set_syncrate(ahc, devinfo, path,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*syncrate*/NULL, /*period*/0,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
/*offset*/0, AHC_TRANS_ACTIVE,
/*paused*/TRUE);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (sending_reply == FALSE && reject == FALSE) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (tinfo->goal.period) {
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
struct ahc_syncrate *rate;
u_int period;
u_int offset;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Start the sync negotiation */
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
period = tinfo->goal.period;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
rate = ahc_devlimited_syncrate(ahc,
&period);
offset = tinfo->goal.offset;
ahc_validate_offset(ahc, rate, &offset,
tinfo->current.width);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_index = 0;
ahc->msgout_len = 0;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
ahc_construct_sdtr(ahc, period, offset);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_index = 0;
response = TRUE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
}
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
done = MSGLOOP_MSGCOMPLETE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
default:
/* Unknown extended message. Reject it. */
reject = TRUE;
break;
}
Add two missing break statements.
1999-01-15 23:24:23 +00:00
break;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
case MSG_BUS_DEV_RESET:
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc_handle_devreset(ahc, devinfo,
CAM_BDR_SENT, AC_SENT_BDR,
"Bus Device Reset Received",
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
/*verbose_level*/0);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
restart_sequencer(ahc);
done = MSGLOOP_TERMINATED;
break;
case MSG_ABORT_TAG:
case MSG_ABORT:
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
case MSG_CLEAR_QUEUE:
/* Target mode messages */
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (devinfo->role != ROLE_TARGET) {
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
reject = TRUE;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
break;
}
ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
devinfo->lun,
ahc->msgin_buf[0] == MSG_ABORT_TAG
? SCB_LIST_NULL
: ahc_inb(ahc, INITIATOR_TAG),
ROLE_TARGET, CAM_REQ_ABORTED);
tstate = ahc->enabled_targets[devinfo->our_scsiid];
if (tstate != NULL) {
struct tmode_lstate* lstate;
lstate = tstate->enabled_luns[devinfo->lun];
if (lstate != NULL) {
ahc_queue_lstate_event(ahc, lstate,
devinfo->our_scsiid,
ahc->msgin_buf[0],
/*arg*/0);
ahc_send_lstate_events(ahc, lstate);
}
}
done = MSGLOOP_MSGCOMPLETE;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
break;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
case MSG_TERM_IO_PROC:
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
default:
reject = TRUE;
break;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (reject) {
/*
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
* Setup to reject the message.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_index = 0;
ahc->msgout_len = 1;
ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
done = MSGLOOP_MSGCOMPLETE;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
response = TRUE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (done != MSGLOOP_IN_PROG && !response)
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* Clear the outgoing message buffer */
ahc->msgout_len = 0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return (done);
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
static void
ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
{
u_int scb_index;
struct scb *scb;
scb_index = ahc_inb(ahc, SCB_TAG);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb = &ahc->scb_data->scbarray[scb_index];
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
|| (scb->ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_IN) {
/*
* Ignore the message if we haven't
* seen an appropriate data phase yet.
*/
} else {
/*
* If the residual occurred on the last
* transfer and the transfer request was
* expected to end on an odd count, do
* nothing. Otherwise, subtract a byte
* and update the residual count accordingly.
*/
u_int resid_sgcnt;
resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT);
if (resid_sgcnt == 0
&& ahc_inb(ahc, DATA_COUNT_ODD) == 1) {
/*
* If the residual occurred on the last
* transfer and the transfer request was
* expected to end on an odd count, do
* nothing.
*/
} else {
u_int data_cnt;
u_int data_addr;
u_int sg_index;
data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16)
| (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8)
| (ahc_inb(ahc, SCB_RESID_DCNT));
data_addr = (ahc_inb(ahc, SHADDR + 3) << 24)
| (ahc_inb(ahc, SHADDR + 2) << 16)
| (ahc_inb(ahc, SHADDR + 1) << 8)
| (ahc_inb(ahc, SHADDR));
data_cnt += 1;
data_addr -= 1;
sg_index = scb->sg_count - resid_sgcnt;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
if (sg_index != 0
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
&& (scb->sg_list[sg_index].len < data_cnt)) {
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
u_int sg_addr;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
sg_index--;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
data_cnt = 1;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
data_addr = scb->sg_list[sg_index].addr
+ scb->sg_list[sg_index].len - 1;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
/*
* The physical address base points to the
* second entry as it is always used for
* calculating the "next S/G pointer".
*/
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
sg_addr = scb->sg_list_phys
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
+ (sg_index* sizeof(*scb->sg_list));
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24);
ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16);
ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8);
ahc_outb(ahc, SG_NEXT, sg_addr);
}
ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16);
ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8);
ahc_outb(ahc, SCB_RESID_DCNT, data_cnt);
ahc_outb(ahc, SHADDR + 3, data_addr >> 24);
ahc_outb(ahc, SHADDR + 2, data_addr >> 16);
ahc_outb(ahc, SHADDR + 1, data_addr >> 8);
ahc_outb(ahc, SHADDR, data_addr);
}
}
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cam_status status, ac_code acode, char *message,
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
int verbose_level)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
struct cam_path *path;
int found;
int error;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
struct tmode_tstate* tstate;
u_int lun;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
error = ahc_create_path(ahc, devinfo, &path);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
status);
aic7xxx.c: Clean out some #if 0'ed debugging cruft. aic7xxx.h: Definitions for the aic7855 and aic7859.
1999-08-30 16:12:39 +00:00
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/*
* Send an immediate notify ccb to all target more peripheral
* drivers affected by this action.
*/
tstate = ahc->enabled_targets[devinfo->our_scsiid];
if (tstate != NULL) {
for (lun = 0; lun <= 7; lun++) {
struct tmode_lstate* lstate;
lstate = tstate->enabled_luns[lun];
if (lstate == NULL)
continue;
ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
MSG_BUS_DEV_RESET, /*arg*/0);
ahc_send_lstate_events(ahc, lstate);
}
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Go back to async/narrow transfers and renegotiate.
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
* ahc_set_width and ahc_set_syncrate can cope with NULL
* paths.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_set_width(ahc, devinfo, path, MSG_EXT_WDTR_BUS_8_BIT,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_CUR, /*paused*/TRUE);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_set_syncrate(ahc, devinfo, path, /*syncrate*/NULL,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
/*period*/0, /*offset*/0, AHC_TRANS_CUR,
/*paused*/TRUE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (error == CAM_REQ_CMP && acode != 0)
xpt_async(AC_SENT_BDR, path, NULL);
if (error == CAM_REQ_CMP)
xpt_free_path(path);
if (message != NULL
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
&& (verbose_level <= bootverbose))
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
message, devinfo->channel, devinfo->target, found);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Add a missing newline.
1998-10-07 03:34:13 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* We have an scb which has been processed by the
* adaptor, now we look to see how the operation
* went.
*/
static void
ahc_done(struct ahc_softc *ahc, struct scb *scb)
{
union ccb *ccb;
CAM_DEBUG(scb->ccb->ccb_h.path, CAM_DEBUG_TRACE,
("ahc_done - scb %d\n", scb->hscb->tag));
ccb = scb->ccb;
LIST_REMOVE(&ccb->ccb_h, sim_links.le);
untimeout(ahc_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch);
if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
bus_dmasync_op_t op;
if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
op = BUS_DMASYNC_POSTREAD;
else
op = BUS_DMASYNC_POSTWRITE;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op);
bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
/*
* Unbusy this target/channel/lun.
* XXX if we are holding two commands per lun,
* send the next command.
*/
ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE);
if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) {
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (ahc_ccb_status(ccb) == CAM_REQ_INPROG)
ccb->ccb_h.status |= CAM_REQ_CMP;
ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcfreescb(ahc, scb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_done(ccb);
return;
}
/*
* If the recovery SCB completes, we have to be
* out of our timeout.
*/
if ((scb->flags & SCB_RECOVERY_SCB) != 0) {
struct ccb_hdr *ccbh;
/*
* We were able to complete the command successfully,
* so reinstate the timeouts for all other pending
* commands.
*/
ccbh = ahc->pending_ccbs.lh_first;
while (ccbh != NULL) {
struct scb *pending_scb;
pending_scb = (struct scb *)ccbh->ccb_scb_ptr;
ccbh->timeout_ch =
timeout(ahc_timeout, pending_scb,
(ccbh->timeout * hz)/1000);
ccbh = LIST_NEXT(ccbh, sim_links.le);
}
/*
* Ensure that we didn't put a second instance of this
* SCB into the QINFIFO.
*/
ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb),
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
SCB_LUN(scb), scb->hscb->tag,
ROLE_INITIATOR, /*status*/0,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
SEARCH_REMOVE);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
if (ahc_ccb_status(ccb) == CAM_BDR_SENT
|| ahc_ccb_status(ccb) == CAM_REQ_ABORTED)
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(ccb, CAM_CMD_TIMEOUT);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_print_path(ccb->ccb_h.path);
printf("no longer in timeout, status = %x\n",
ccb->ccb_h.status);
}
/* Don't clobber any existing error state */
if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) {
ccb->ccb_h.status |= CAM_REQ_CMP;
} else if ((scb->flags & SCB_SENSE) != 0) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*
* We performed autosense retrieval.
*
Update copyright. Correct some whitespace.
1999-05-17 21:53:51 +00:00
* bzero the sense data before having
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
* the drive fill it. The SCSI spec mandates
* that any untransfered data should be
* assumed to be zero. Complete the 'bounce'
* of sense information through buffers accessible
* via bus-space by copying it into the clients
* csio.
*/
bzero(&ccb->csio.sense_data, sizeof(ccb->csio.sense_data));
bcopy(&ahc->scb_data->sense[scb->hscb->tag],
&ccb->csio.sense_data, scb->sg_list->len);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scb->ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
}
ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcfreescb(ahc, scb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_done(ccb);
}
/*
* Determine the number of SCBs available on the controller
*/
int
ahc_probe_scbs(struct ahc_softc *ahc) {
int i;
for (i = 0; i < AHC_SCB_MAX; i++) {
ahc_outb(ahc, SCBPTR, i);
ahc_outb(ahc, SCB_CONTROL, i);
if (ahc_inb(ahc, SCB_CONTROL) != i)
break;
ahc_outb(ahc, SCBPTR, 0);
if (ahc_inb(ahc, SCB_CONTROL) != 0)
break;
}
return (i);
}
/*
* Start the board, ready for normal operation
*/
int
ahc_init(struct ahc_softc *ahc)
{
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
int max_targ = 15;
int i;
int term;
u_int scsi_conf;
u_int scsiseq_template;
u_int ultraenb;
u_int discenable;
u_int tagenable;
size_t driver_data_size;
u_int32_t physaddr;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#ifdef AHC_PRINT_SRAM
printf("Scratch Ram:");
for (i = 0x20; i < 0x5f; i++) {
if (((i % 8) == 0) && (i != 0)) {
printf ("\n ");
}
printf (" 0x%x", ahc_inb(ahc, i));
}
if ((ahc->features & AHC_MORE_SRAM) != 0) {
for (i = 0x70; i < 0x7f; i++) {
if (((i % 8) == 0) && (i != 0)) {
printf ("\n ");
}
printf (" 0x%x", ahc_inb(ahc, i));
}
}
printf ("\n");
#endif
/*
* Assume we have a board at this stage and it has been reset.
*/
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if ((ahc->flags & AHC_USEDEFAULTS) != 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc->our_id = ahc->our_id_b = 7;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/*
* Default to allowing initiator operations.
*/
ahc->flags |= AHC_INITIATORMODE;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* XXX Would be better to use a per device flag, but PCI and EISA
* devices don't have them yet.
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if ((AHC_TMODE_ENABLE & (0x01 << ahc->unit)) != 0) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc->flags |= AHC_TARGETMODE;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
/*
* Although we have space for both the initiator and
* target roles on ULTRA2 chips, we currently disable
* the initiator role to allow multi-scsi-id target mode
* configurations. We can only respond on the same SCSI
* ID as our initiator role if we allow initiator operation.
* At some point, we should add a configuration knob to
* allow both roles to be loaded.
*/
ahc->flags &= ~AHC_INITIATORMODE;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/* DMA tag for mapping buffers into device visible space. */
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*lowaddr*/BUS_SPACE_MAXADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG,
/*maxsegsz*/AHC_MAXTRANSFER_SIZE,
/*flags*/BUS_DMA_ALLOCNOW,
&ahc->buffer_dmat) != 0) {
return (ENOMEM);
}
ahc->init_level++;
/*
* DMA tag for our command fifos and other data in system memory
* the card's sequencer must be able to access. For initiator
* roles, we need to allocate space for the qinfifo, qoutfifo,
* and untagged_scb arrays each of which are composed of 256
* 1 byte elements. When providing for the target mode role,
* we additionally must provide space for the incoming target
* command fifo.
*/
driver_data_size = 3 * 256 * sizeof(u_int8_t);
if ((ahc->flags & AHC_TARGETMODE) != 0)
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
+ /*DMA WideOdd Bug Buffer*/1;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0,
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/*lowaddr*/BUS_SPACE_MAXADDR,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
driver_data_size,
/*nsegments*/1,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, &ahc->shared_data_dmat) != 0) {
return (ENOMEM);
}
ahc->init_level++;
/* Allocation of driver data */
if (bus_dmamem_alloc(ahc->shared_data_dmat, (void **)&ahc->qoutfifo,
BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
return (ENOMEM);
}
ahc->init_level++;
/* And permanently map it in */
bus_dmamap_load(ahc->shared_data_dmat, ahc->shared_data_dmamap,
ahc->qoutfifo, driver_data_size,
ahcdmamapcb, &ahc->shared_data_busaddr, /*flags*/0);
ahc->init_level++;
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
/* Allocate SCB data now that buffer_dmat is initialized */
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
if (ahc->scb_data->maxhscbs == 0)
if (ahcinitscbdata(ahc) != 0)
return (ENOMEM);
ahc->qinfifo = &ahc->qoutfifo[256];
ahc->untagged_scbs = &ahc->qinfifo[256];
/* There are no untagged SCBs active yet. */
for (i = 0; i < 256; i++)
ahc->untagged_scbs[i] = SCB_LIST_NULL;
/* All of our queues are empty */
for (i = 0; i < 256; i++)
ahc->qoutfifo[i] = SCB_LIST_NULL;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if ((ahc->features & AHC_MULTI_TID) != 0) {
ahc_outb(ahc, TARGID, 0);
ahc_outb(ahc, TARGID + 1, 0);
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
if ((ahc->flags & AHC_TARGETMODE) != 0) {
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc->targetcmds = (struct target_cmd *)&ahc->untagged_scbs[256];
ahc->dma_bug_buf = ahc->shared_data_busaddr
+ driver_data_size - 1;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/* All target command blocks start out invalid. */
for (i = 0; i < AHC_TMODE_CMDS; i++)
ahc->targetcmds[i].cmd_valid = 0;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
ahc->tqinfifonext = 1;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
/*
* Allocate a tstate to house information for our
* initiator presence on the bus as well as the user
* data for any target mode initiator.
*/
if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
printf("%s: unable to allocate tmode_tstate. "
"Failing attach\n", ahc_name(ahc));
return (-1);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((ahc->features & AHC_TWIN) != 0) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
printf("%s: unable to allocate tmode_tstate. "
"Failing attach\n", ahc_name(ahc));
return (-1);
}
Bring back support for honoring the primary channel setting for twin channel EISA adapters. This could have caused the system to find the wrong root disk. Reviewed by: J Wunsch <j@ida.interface-business.de>
1998-10-15 18:21:50 +00:00
printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ",
ahc->our_id, ahc->our_id_b,
ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A');
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
if ((ahc->features & AHC_WIDE) != 0) {
printf("Wide ");
} else {
printf("Single ");
}
printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id);
}
ahc_outb(ahc, SEQ_FLAGS, 0);
if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) {
ahc->flags |= AHC_PAGESCBS;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
ahc->flags &= ~AHC_PAGESCBS;
printf("%d SCBs\n", ahc->scb_data->maxhscbs);
}
#ifdef AHC_DEBUG
if (ahc_debug & AHC_SHOWMISC) {
printf("%s: hardware scb %d bytes; kernel scb %d bytes; "
"ahc_dma %d bytes\n",
ahc_name(ahc),
sizeof(struct hardware_scb),
sizeof(struct scb),
sizeof(struct ahc_dma_seg));
}
#endif /* AHC_DEBUG */
/* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
if (ahc->features & AHC_TWIN) {
/*
* The device is gated to channel B after a chip reset,
* so set those values first
*/
term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b);
else
ahc_outb(ahc, SCSIID, ahc->our_id_b);
scsi_conf = ahc_inb(ahc, SCSICONF + 1);
ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
Remove unused variables and functions. In the rejected message handler, it was possible for us to confuse a rejected SDTR or WDTR for a rejected tag.
1998-09-20 23:30:14 +00:00
|term|ENSTIMER|ACTNEGEN);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
if ((scsi_conf & RESET_SCSI) != 0
&& (ahc->flags & AHC_INITIATORMODE) != 0)
ahc->flags |= AHC_RESET_BUS_B;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Select Channel A */
ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
}
term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
if ((ahc->features & AHC_ULTRA2) != 0)
ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
else
ahc_outb(ahc, SCSIID, ahc->our_id);
scsi_conf = ahc_inb(ahc, SCSICONF);
ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
|term
|ENSTIMER|ACTNEGEN);
ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
if ((scsi_conf & RESET_SCSI) != 0
&& (ahc->flags & AHC_INITIATORMODE) != 0)
ahc->flags |= AHC_RESET_BUS_A;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Look at the information that board initialization or
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
* the board bios has left us.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ultraenb = 0;
tagenable = ALL_TARGETS_MASK;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Grab the disconnection disable table and invert it for our needs */
if (ahc->flags & AHC_USEDEFAULTS) {
printf("%s: Host Adapter Bios disabled. Using default SCSI "
"device parameters\n", ahc_name(ahc));
When 'using defaults' ensure that termination is enabled. Removed some unused code.
1998-10-09 17:41:39 +00:00
ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
AHC_TERM_ENB_A|AHC_TERM_ENB_B;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
discenable = ALL_TARGETS_MASK;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((ahc->features & AHC_ULTRA) != 0)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ultraenb = ALL_TARGETS_MASK;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
| ahc_inb(ahc, DISC_DSB));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
| ahc_inb(ahc, ULTRA_ENB);
}
if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
max_targ = 7;
for (i = 0; i <= max_targ; i++) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
u_int our_id;
u_int target_id;
char channel;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
channel = 'A';
our_id = ahc->our_id;
target_id = i;
if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
channel = 'B';
our_id = ahc->our_id_b;
target_id = i % 8;
}
tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
target_id, &tstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Default to async narrow across the board */
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
bzero(tinfo, sizeof(*tinfo));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (ahc->flags & AHC_USEDEFAULTS) {
if ((ahc->features & AHC_WIDE) != 0)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* These will be truncated when we determine the
* connection type we have with the target.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo->user.period = ahc_syncrates->period;
tinfo->user.offset = ~0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
u_int scsirate;
u_int16_t mask;
/* Take the settings leftover in scratch RAM. */
scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
mask = (0x01 << i);
if ((ahc->features & AHC_ULTRA2) != 0) {
u_int offset;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
u_int maxsync;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((scsirate & SOFS) == 0x0F) {
/*
* Haven't negotiated yet,
* so the format is different.
*/
scsirate = (scsirate & SXFR) >> 4
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
| (ultraenb & mask)
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
? 0x08 : 0x0
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
| (scsirate & WIDEXFER);
offset = MAX_OFFSET_ULTRA2;
} else
offset = ahc_inb(ahc, TARG_OFFSET + i);
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
maxsync = AHC_SYNCRATE_ULTRA2;
if ((ahc->features & AHC_DT) != 0)
maxsync = AHC_SYNCRATE_DT;
aic7xxx.c: Honor the 'bus reset at startup' option now that the XPT properly handles transfer negotiation in this scenario. Honor the sync rate settings on Ultra2 controllers. We would always negotiate at the fastest speed. Oops. aic7xxx.h: Whitespace. aic7xxx.seq: Fix a minor nit that would cause the controller to miss the update of the negotiation required bitmask causing the negotiation to be delayed by a command.
1999-05-22 22:04:11 +00:00
tinfo->user.period =
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
ahc_find_period(ahc, scsirate, maxsync);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (offset == 0)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo->user.period = 0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
else
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo->user.offset = ~0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else if ((scsirate & SOFS) != 0) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo->user.period =
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_find_period(ahc, scsirate,
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
(ultraenb & mask)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
? AHC_SYNCRATE_ULTRA
: AHC_SYNCRATE_FAST);
Fix from Justin for transfer negotiations for targets up to target ID 7.
1999-04-26 22:03:44 +00:00
if (tinfo->user.period != 0)
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo->user.offset = ~0;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if ((scsirate & WIDEXFER) != 0
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
&& (ahc->features & AHC_WIDE) != 0)
tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tstate->ultraenb = ultraenb;
tstate->discenable = discenable;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
tstate->tagenable = 0; /* Wait until the XPT says its okay */
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc->user_discenable = discenable;
ahc->user_tagenable = tagenable;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Fix from Justin for transfer negotiations for targets up to target ID 7.
1999-04-26 22:03:44 +00:00
/*
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
* Tell the sequencer where it can find our arrays in memory.
Fix from Justin for transfer negotiations for targets up to target ID 7.
1999-04-26 22:03:44 +00:00
*/
physaddr = ahc->scb_data->hscb_busaddr;
ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
physaddr = ahc->shared_data_busaddr;
ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF);
ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF);
ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF);
ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF);
/* Target mode incomding command fifo */
physaddr += 3 * 256 * sizeof(u_int8_t);
ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF);
ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF);
ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF);
ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF);
/*
* Initialize the group code to command length table.
* This overrides the values in TARG_SCSIRATE, so only
* setup the table after we have processed that information.
*/
ahc_outb(ahc, CMDSIZE_TABLE, 5);
ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
/* Tell the sequencer of our initial queue positions */
ahc_outb(ahc, KERNEL_QINPOS, 0);
ahc_outb(ahc, QINPOS, 0);
ahc_outb(ahc, QOUTPOS, 0);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
/* Don't have any special messages to send to targets */
ahc_outb(ahc, TARGET_MSG_REQUEST, 0);
ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Use the built in queue management registers
* if they are available.
*/
if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
ahc_outb(ahc, SDSCB_QOFF, 0);
ahc_outb(ahc, SNSCB_QOFF, 0);
ahc_outb(ahc, HNSCB_QOFF, 0);
}
/* We don't have any waiting selections */
ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
/* Our disconnection list is empty too */
ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
/* Message out buffer starts empty */
ahc_outb(ahc, MSG_OUT, MSG_NOOP);
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
/*
* Setup the allowed SCSI Sequences based on operational mode.
* If we are a target, we'll enalbe select in operations once
* we've had a lun enabled.
*/
scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
if ((ahc->flags & AHC_INITIATORMODE) != 0)
scsiseq_template |= ENRSELI;
ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Load the Sequencer program and Enable the adapter
* in "fast" mode.
*/
if (bootverbose)
printf("%s: Downloading Sequencer Program...",
ahc_name(ahc));
ahc_loadseq(ahc);
/* We have to wait until after any system dumps... */
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
EVENTHANDLER_REGISTER(shutdown_final, ahc_shutdown,
ahc, SHUTDOWN_PRI_DEFAULT);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return (0);
}
static cam_status
ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
struct tmode_tstate **tstate, struct tmode_lstate **lstate,
int notfound_failure)
{
int our_id;
/*
* If we are not configured for target mode, someone
* is really confused to be sending this to us.
*/
if ((ahc->flags & AHC_TARGETMODE) == 0)
return (CAM_REQ_INVALID);
/* Range check target and lun */
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
/*
* Handle the 'black hole' device that sucks up
* requests to unattached luns on enabled targets.
*/
if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
&& ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
*tstate = NULL;
*lstate = ahc->black_hole;
} else {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
u_int max_id;
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if (cam_sim_bus(sim) == 0)
our_id = ahc->our_id;
else
our_id = ahc->our_id_b;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
if (ccb->ccb_h.target_id > max_id)
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
return (CAM_TID_INVALID);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (ccb->ccb_h.target_lun > 7)
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
return (CAM_LUN_INVALID);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (ccb->ccb_h.target_id != our_id) {
if ((ahc->features & AHC_MULTI_TID) != 0) {
/*
* Only allow additional targets if
* the initiator role is disabled.
* The hardware cannot handle a re-select-in
* on the initiator id during a re-select-out
* on a different target id.
*/
if ((ahc->flags & AHC_INITIATORMODE) != 0)
return (CAM_TID_INVALID);
} else {
/*
* Only allow our target id to change
* if the initiator role is not configured
* and there are no enabled luns which
* are attached to the currently registered
* scsi id.
*/
if ((ahc->flags & AHC_INITIATORMODE) != 0
|| ahc->enabled_luns > 0)
return (CAM_TID_INVALID);
}
}
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
*tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
*lstate = NULL;
if (*tstate != NULL)
*lstate =
(*tstate)->enabled_luns[ccb->ccb_h.target_lun];
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (notfound_failure != 0 && *lstate == NULL)
return (CAM_PATH_INVALID);
return (CAM_REQ_CMP);
}
static void
ahc_action(struct cam_sim *sim, union ccb *ccb)
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_softc *ahc;
struct tmode_lstate *lstate;
u_int target_id;
u_int our_id;
int s;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahc_action\n"));
ahc = (struct ahc_softc *)cam_sim_softc(sim);
target_id = ccb->ccb_h.target_id;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
our_id = SIM_SCSI_ID(ahc, sim);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
switch (ccb->ccb_h.func_code) {
/* Common cases first */
case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
case XPT_CONT_TARGET_IO:/* Continue Host Target I/O Connection*/
{
struct tmode_tstate *tstate;
cam_status status;
status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate,
&lstate, TRUE);
if (status != CAM_REQ_CMP) {
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) {
/* Response from the black hole device */
tstate = NULL;
lstate = ahc->black_hole;
} else {
ccb->ccb_h.status = status;
xpt_done(ccb);
break;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if (ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) {
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
int s;
s = splcam();
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
SLIST_INSERT_HEAD(&lstate->accept_tios, &ccb->ccb_h,
sim_links.sle);
ccb->ccb_h.status = CAM_REQ_INPROG;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((ahc->flags & AHC_TQINFIFO_BLOCKED) != 0)
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
ahc_run_tqinfifo(ahc, /*paused*/FALSE);
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
splx(s);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
/*
* The target_id represents the target we attempt to
* select. In target mode, this is the initiator of
* the original command.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
our_id = target_id;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
target_id = ccb->csio.init_id;
/* FALLTHROUGH */
}
case XPT_SCSI_IO: /* Execute the requested I/O operation */
case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
{
struct scb *scb;
struct hardware_scb *hscb;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
u_int16_t mask;
/*
* get an scb to use.
*/
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
if ((scb = ahcgetscb(ahc)) == NULL) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
int s;
s = splcam();
ahc->flags |= AHC_RESOURCE_SHORTAGE;
splx(s);
xpt_freeze_simq(ahc->sim, /*count*/1);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(ccb, CAM_REQUEUE_REQ);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_done(ccb);
return;
}
hscb = scb->hscb;
CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_SUBTRACE,
("start scb(%p)\n", scb));
scb->ccb = ccb;
/*
* So we can find the SCB when an abort is requested
*/
ccb->ccb_h.ccb_scb_ptr = scb;
ccb->ccb_h.ccb_ahc_ptr = ahc;
/*
* Put all the arguments for the xfer in the scb
*/
hscb->tcl = ((target_id << 4) & 0xF0)
| (SIM_IS_SCSIBUS_B(ahc, sim) ? SELBUSB : 0)
| (ccb->ccb_h.target_lun & 0x07);
mask = SCB_TARGET_MASK(scb);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, sim), our_id,
target_id, &tstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
hscb->scsirate = tinfo->scsirate;
hscb->scsioffset = tinfo->current.offset;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((tstate->ultraenb & mask) != 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
hscb->control |= ULTRAENB;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((tstate->discenable & mask) != 0
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
&& (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0)
hscb->control |= DISCENB;
if (ccb->ccb_h.func_code == XPT_RESET_DEV) {
hscb->cmdpointer = NULL;
scb->flags |= SCB_DEVICE_RESET;
hscb->control |= MK_MESSAGE;
ahc_execute_scb(scb, NULL, 0, 0);
} else {
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (ahc->pending_device == lstate) {
scb->flags |= SCB_TARGET_IMMEDIATE;
ahc->pending_device = NULL;
}
hscb->control |= TARGET_SCB;
hscb->cmdpointer = IDENTIFY_SEEN;
if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) {
hscb->cmdpointer |= SPHASE_PENDING;
hscb->status = ccb->csio.scsi_status;
}
/* Overloaded with tag ID */
hscb->cmdlen = ccb->csio.tag_id;
/*
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
* Overloaded with the value to place
* in SCSIID for reselection.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
hscb->cmdpointer |=
(our_id|(hscb->tcl & 0xF0)) << 16;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if (ccb->ccb_h.flags & CAM_TAG_ACTION_VALID)
hscb->control |= ccb->csio.tag_action;
ahc_setup_data(ahc, &ccb->csio, scb);
}
break;
}
case XPT_NOTIFY_ACK:
case XPT_IMMED_NOTIFY:
{
struct tmode_tstate *tstate;
struct tmode_lstate *lstate;
cam_status status;
status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate,
&lstate, TRUE);
if (status != CAM_REQ_CMP) {
ccb->ccb_h.status = status;
xpt_done(ccb);
break;
}
SLIST_INSERT_HEAD(&lstate->immed_notifies, &ccb->ccb_h,
sim_links.sle);
ccb->ccb_h.status = CAM_REQ_INPROG;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc_send_lstate_events(ahc, lstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
case XPT_EN_LUN: /* Enable LUN as a target */
Add support for routing initiator transactions to disabled luns to the black hole device. The controller will now only accept selections if the black hole device is present and some other target/lun is enabled for target mode. Handle the IGNORE WIDE RESIDUE message. This support has not been tested. Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS, and CLEAR QUEUE messages as a target. Fix a few problems with tagged command handling in target mode. Wait until the sync offset counter falls to 0 before changing phase after a data-in transfer completes as the DMA logic seems to indicate transfer complete as soon as our last REQ is issued. Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
ahc_handle_en_lun(ahc, sim, ccb);
xpt_done(ccb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
case XPT_ABORT: /* Abort the specified CCB */
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
{
ahc_abort_ccb(ahc, sim, ccb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
case XPT_SET_TRAN_SETTINGS:
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_devinfo devinfo;
struct ccb_trans_settings *cts;
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
u_int16_t *discenable;
u_int16_t *tagenable;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
u_int update_type;
int s;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cts = &ccb->cts;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim),
cts->ccb_h.target_id,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
cts->ccb_h.target_lun,
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
SIM_CHANNEL(ahc, sim),
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ROLE_UNKNOWN);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
devinfo.our_scsiid,
devinfo.target, &tstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
update_type = 0;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
update_type |= AHC_TRANS_GOAL;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
discenable = &tstate->discenable;
tagenable = &tstate->tagenable;
} else if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
update_type |= AHC_TRANS_USER;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
discenable = &ahc->user_discenable;
tagenable = &ahc->user_tagenable;
} else {
ccb->ccb_h.status = CAM_REQ_INVALID;
xpt_done(ccb);
break;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
s = splcam();
if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
*discenable |= devinfo.target_mask;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
else
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
*discenable &= ~devinfo.target_mask;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
*tagenable |= devinfo.target_mask;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
else
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
*tagenable &= ~devinfo.target_mask;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) {
switch (cts->bus_width) {
case MSG_EXT_WDTR_BUS_16_BIT:
if ((ahc->features & AHC_WIDE) != 0)
break;
/* FALLTHROUGH to 8bit */
case MSG_EXT_WDTR_BUS_32_BIT:
case MSG_EXT_WDTR_BUS_8_BIT:
default:
cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
break;
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_set_width(ahc, &devinfo, cts->ccb_h.path,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
cts->bus_width, update_type,
/*paused*/FALSE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Add a number of interrelated CAM feature enhancements and bug fixes. NOTE: These changes will require recompilation of any userland applications, like cdrecord, xmcd, etc., that use the CAM passthrough interface. A make world is recommended. camcontrol.[c8]: - We now support two new commands, "tags" and "negotiate". - The tags commands allows users to view the number of tagged openings for a device as well as a number of other related parameters, and it allows users to set tagged openings for a device. - The negotiate command allows users to enable and disable disconnection and tagged queueing, set sync rates, offsets and bus width. Note that not all of those features are available for all controllers. Only the adv, ahc, and ncr drivers fully support all of the features at this point. Some cards do not allow the setting of sync rates, offsets and the like, and some of the drivers don't have any facilities to do so. Some drivers, like the adw driver, only support enabling or disabling sync negotiation, but do not support setting sync rates. - new description in the camcontrol man page of how to format a disk - cleanup of the camcontrol inquiry command - add support in the 'devlist' command for skipping unconfigured devices if -v was not specified on the command line. - make use of the new base_transfer_speed in the path inquiry CCB. - fix CCB bzero cases cam_xpt.c, cam_sim.[ch], cam_ccb.h: - new flags on many CCB function codes to designate whether they're non-immediate, use a user-supplied CCB, and can only be passed from userland programs via the xpt device. Use these flags in the transport layer and pass driver to categorize CCBs. - new flag in the transport layer device matching code for device nodes that indicates whether a device is unconfigured - bump the CAM version from 0x10 to 0x11 - Change the CAM ioctls to use the version as their group code, so we can force users to recompile code even when the CCB size doesn't change. - add + fill in a new value in the path inquiry CCB, base_transfer_speed. Remove a corresponding field from the cam_sim structure, and add code to every SIM to set this field to the proper value. - Fix the set transfer settings code in the transport layer. scsi_cd.c: - make some variables volatile instead of just casting them in various places - fix a race condition in the changer code - attach unless we get a "logical unit not supported" error. This should fix all of the cases where people have devices that return weird errors when they don't have media in the drive. scsi_da.c: - attach unless we get a "logical unit not supported" error scsi_pass.c: - for immediate CCBs, just malloc a CCB to send the user request in. This gets rid of the 'held' count problem in camcontrol tags. scsi_pass.h: - change the CAM ioctls to use the CAM version as their group code. adv driver: - Allow changing the sync rate and offset separately. adw driver - Allow changing the sync rate and offset separately. aha driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. ahc driver: - Allow setting offset and sync rate separately bt driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. NCR driver: - Fix the ultra/ultra 2 negotiation bug - allow setting both the sync rate and offset separately Other HBA drivers: - Put code in to set the base_transfer_speed field for XPT_GET_TRAN_SETTINGS CCBs. Reviewed by: gibbs, mjacob (isp), imp (aha)
1999-05-06 20:16:39 +00:00
if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
|| ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
struct ahc_syncrate *syncrate;
u_int maxsync;
if ((ahc->features & AHC_ULTRA2) != 0)
maxsync = AHC_SYNCRATE_ULTRA2;
else if ((ahc->features & AHC_ULTRA) != 0)
maxsync = AHC_SYNCRATE_ULTRA;
else
maxsync = AHC_SYNCRATE_FAST;
Preserve termination settings across the card reset in our shutdown hook.
1999-04-19 21:28:15 +00:00
if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (update_type & AHC_TRANS_USER)
cts->sync_offset = tinfo->user.offset;
else
cts->sync_offset = tinfo->goal.offset;
Preserve termination settings across the card reset in our shutdown hook.
1999-04-19 21:28:15 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Add a number of interrelated CAM feature enhancements and bug fixes. NOTE: These changes will require recompilation of any userland applications, like cdrecord, xmcd, etc., that use the CAM passthrough interface. A make world is recommended. camcontrol.[c8]: - We now support two new commands, "tags" and "negotiate". - The tags commands allows users to view the number of tagged openings for a device as well as a number of other related parameters, and it allows users to set tagged openings for a device. - The negotiate command allows users to enable and disable disconnection and tagged queueing, set sync rates, offsets and bus width. Note that not all of those features are available for all controllers. Only the adv, ahc, and ncr drivers fully support all of the features at this point. Some cards do not allow the setting of sync rates, offsets and the like, and some of the drivers don't have any facilities to do so. Some drivers, like the adw driver, only support enabling or disabling sync negotiation, but do not support setting sync rates. - new description in the camcontrol man page of how to format a disk - cleanup of the camcontrol inquiry command - add support in the 'devlist' command for skipping unconfigured devices if -v was not specified on the command line. - make use of the new base_transfer_speed in the path inquiry CCB. - fix CCB bzero cases cam_xpt.c, cam_sim.[ch], cam_ccb.h: - new flags on many CCB function codes to designate whether they're non-immediate, use a user-supplied CCB, and can only be passed from userland programs via the xpt device. Use these flags in the transport layer and pass driver to categorize CCBs. - new flag in the transport layer device matching code for device nodes that indicates whether a device is unconfigured - bump the CAM version from 0x10 to 0x11 - Change the CAM ioctls to use the version as their group code, so we can force users to recompile code even when the CCB size doesn't change. - add + fill in a new value in the path inquiry CCB, base_transfer_speed. Remove a corresponding field from the cam_sim structure, and add code to every SIM to set this field to the proper value. - Fix the set transfer settings code in the transport layer. scsi_cd.c: - make some variables volatile instead of just casting them in various places - fix a race condition in the changer code - attach unless we get a "logical unit not supported" error. This should fix all of the cases where people have devices that return weird errors when they don't have media in the drive. scsi_da.c: - attach unless we get a "logical unit not supported" error scsi_pass.c: - for immediate CCBs, just malloc a CCB to send the user request in. This gets rid of the 'held' count problem in camcontrol tags. scsi_pass.h: - change the CAM ioctls to use the CAM version as their group code. adv driver: - Allow changing the sync rate and offset separately. adw driver - Allow changing the sync rate and offset separately. aha driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. ahc driver: - Allow setting offset and sync rate separately bt driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. NCR driver: - Fix the ultra/ultra 2 negotiation bug - allow setting both the sync rate and offset separately Other HBA drivers: - Put code in to set the base_transfer_speed field for XPT_GET_TRAN_SETTINGS CCBs. Reviewed by: gibbs, mjacob (isp), imp (aha)
1999-05-06 20:16:39 +00:00
if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0) {
if (update_type & AHC_TRANS_USER)
cts->sync_period = tinfo->user.period;
else
cts->sync_period = tinfo->goal.period;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
syncrate = ahc_find_syncrate(ahc, &cts->sync_period,
maxsync);
ahc_validate_offset(ahc, syncrate, &cts->sync_offset,
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
MSG_EXT_WDTR_BUS_8_BIT);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* We use a period of 0 to represent async */
if (cts->sync_offset == 0)
cts->sync_period = 0;
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_set_syncrate(ahc, &devinfo, cts->ccb_h.path,
syncrate, cts->sync_period,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
cts->sync_offset, update_type,
/*paused*/FALSE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
splx(s);
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
case XPT_GET_TRAN_SETTINGS:
/* Get default/user set transfer settings for the target */
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_devinfo devinfo;
struct ccb_trans_settings *cts;
struct ahc_initiator_tinfo *targ_info;
struct tmode_tstate *tstate;
struct ahc_transinfo *tinfo;
int s;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cts = &ccb->cts;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim),
cts->ccb_h.target_id,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
cts->ccb_h.target_lun,
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
SIM_CHANNEL(ahc, sim),
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ROLE_UNKNOWN);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
targ_info = ahc_fetch_transinfo(ahc, devinfo.channel,
devinfo.our_scsiid,
devinfo.target, &tstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0)
tinfo = &targ_info->current;
else
tinfo = &targ_info->user;
s = splcam();
cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
if ((ahc->user_discenable & devinfo.target_mask) != 0)
cts->flags |= CCB_TRANS_DISC_ENB;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if ((ahc->user_tagenable & devinfo.target_mask) != 0)
cts->flags |= CCB_TRANS_TAG_ENB;
} else {
if ((tstate->discenable & devinfo.target_mask) != 0)
cts->flags |= CCB_TRANS_DISC_ENB;
if ((tstate->tagenable & devinfo.target_mask) != 0)
cts->flags |= CCB_TRANS_TAG_ENB;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cts->sync_period = tinfo->period;
cts->sync_offset = tinfo->offset;
cts->bus_width = tinfo->width;
splx(s);
cts->valid = CCB_TRANS_SYNC_RATE_VALID
| CCB_TRANS_SYNC_OFFSET_VALID
| CCB_TRANS_BUS_WIDTH_VALID
| CCB_TRANS_DISC_VALID
| CCB_TRANS_TQ_VALID;
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
case XPT_CALC_GEOMETRY:
{
struct ccb_calc_geometry *ccg;
u_int32_t size_mb;
u_int32_t secs_per_cylinder;
int extended;
ccg = &ccb->ccg;
size_mb = ccg->volume_size
/ ((1024L * 1024L) / ccg->block_size);
extended = SIM_IS_SCSIBUS_B(ahc, sim)
? ahc->flags & AHC_EXTENDED_TRANS_B
: ahc->flags & AHC_EXTENDED_TRANS_A;
if (size_mb > 1024 && extended) {
ccg->heads = 255;
ccg->secs_per_track = 63;
} else {
ccg->heads = 64;
ccg->secs_per_track = 32;
}
secs_per_cylinder = ccg->heads * ccg->secs_per_track;
ccg->cylinders = ccg->volume_size / secs_per_cylinder;
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
case XPT_RESET_BUS: /* Reset the specified SCSI bus */
{
int found;
s = splcam();
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
found = ahc_reset_channel(ahc, SIM_CHANNEL(ahc, sim),
/*initiate reset*/TRUE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
splx(s);
if (bootverbose) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
xpt_print_path(SIM_PATH(ahc, sim));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("SCSI bus reset delivered. "
"%d SCBs aborted.\n", found);
}
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
case XPT_TERM_IO: /* Terminate the I/O process */
/* XXX Implement */
ccb->ccb_h.status = CAM_REQ_INVALID;
xpt_done(ccb);
break;
case XPT_PATH_INQ: /* Path routing inquiry */
{
struct ccb_pathinq *cpi = &ccb->cpi;
cpi->version_num = 1; /* XXX??? */
cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE;
if ((ahc->features & AHC_WIDE) != 0)
cpi->hba_inquiry |= PI_WIDE_16;
if ((ahc->flags & AHC_TARGETMODE) != 0) {
cpi->target_sprt = PIT_PROCESSOR
| PIT_DISCONNECT
| PIT_TERM_IO;
} else {
cpi->target_sprt = 0;
}
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
cpi->hba_misc = (ahc->flags & AHC_INITIATORMODE)
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
? 0 : PIM_NOINITIATOR;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cpi->hba_eng_cnt = 0;
cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7;
cpi->max_lun = 7;
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
if (SIM_IS_SCSIBUS_B(ahc, sim)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cpi->initiator_id = ahc->our_id_b;
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
if ((ahc->flags & AHC_RESET_BUS_B) == 0)
cpi->hba_misc |= PIM_NOBUSRESET;
} else {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cpi->initiator_id = ahc->our_id;
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
if ((ahc->flags & AHC_RESET_BUS_A) == 0)
cpi->hba_misc |= PIM_NOBUSRESET;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cpi->bus_id = cam_sim_bus(sim);
Add a number of interrelated CAM feature enhancements and bug fixes. NOTE: These changes will require recompilation of any userland applications, like cdrecord, xmcd, etc., that use the CAM passthrough interface. A make world is recommended. camcontrol.[c8]: - We now support two new commands, "tags" and "negotiate". - The tags commands allows users to view the number of tagged openings for a device as well as a number of other related parameters, and it allows users to set tagged openings for a device. - The negotiate command allows users to enable and disable disconnection and tagged queueing, set sync rates, offsets and bus width. Note that not all of those features are available for all controllers. Only the adv, ahc, and ncr drivers fully support all of the features at this point. Some cards do not allow the setting of sync rates, offsets and the like, and some of the drivers don't have any facilities to do so. Some drivers, like the adw driver, only support enabling or disabling sync negotiation, but do not support setting sync rates. - new description in the camcontrol man page of how to format a disk - cleanup of the camcontrol inquiry command - add support in the 'devlist' command for skipping unconfigured devices if -v was not specified on the command line. - make use of the new base_transfer_speed in the path inquiry CCB. - fix CCB bzero cases cam_xpt.c, cam_sim.[ch], cam_ccb.h: - new flags on many CCB function codes to designate whether they're non-immediate, use a user-supplied CCB, and can only be passed from userland programs via the xpt device. Use these flags in the transport layer and pass driver to categorize CCBs. - new flag in the transport layer device matching code for device nodes that indicates whether a device is unconfigured - bump the CAM version from 0x10 to 0x11 - Change the CAM ioctls to use the version as their group code, so we can force users to recompile code even when the CCB size doesn't change. - add + fill in a new value in the path inquiry CCB, base_transfer_speed. Remove a corresponding field from the cam_sim structure, and add code to every SIM to set this field to the proper value. - Fix the set transfer settings code in the transport layer. scsi_cd.c: - make some variables volatile instead of just casting them in various places - fix a race condition in the changer code - attach unless we get a "logical unit not supported" error. This should fix all of the cases where people have devices that return weird errors when they don't have media in the drive. scsi_da.c: - attach unless we get a "logical unit not supported" error scsi_pass.c: - for immediate CCBs, just malloc a CCB to send the user request in. This gets rid of the 'held' count problem in camcontrol tags. scsi_pass.h: - change the CAM ioctls to use the CAM version as their group code. adv driver: - Allow changing the sync rate and offset separately. adw driver - Allow changing the sync rate and offset separately. aha driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. ahc driver: - Allow setting offset and sync rate separately bt driver: - Don't return CAM_REQ_CMP for SET_TRAN_SETTINGS CCBs. NCR driver: - Fix the ultra/ultra 2 negotiation bug - allow setting both the sync rate and offset separately Other HBA drivers: - Put code in to set the base_transfer_speed field for XPT_GET_TRAN_SETTINGS CCBs. Reviewed by: gibbs, mjacob (isp), imp (aha)
1999-05-06 20:16:39 +00:00
cpi->base_transfer_speed = 3300;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
default:
ccb->ccb_h.status = CAM_REQ_INVALID;
xpt_done(ccb);
break;
}
}
static void
ahc_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
{
struct ahc_softc *ahc;
struct cam_sim *sim;
sim = (struct cam_sim *)callback_arg;
ahc = (struct ahc_softc *)cam_sim_softc(sim);
switch (code) {
case AC_LOST_DEVICE:
{
struct ahc_devinfo devinfo;
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
int s;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim),
xpt_path_target_id(path),
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
xpt_path_lun_id(path),
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
SIM_CHANNEL(ahc, sim),
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ROLE_UNKNOWN);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Revert to async/narrow transfers
* for the next device.
*/
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
s = splcam();
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_GOAL|AHC_TRANS_CUR,
/*paused*/FALSE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL,
/*period*/0, /*offset*/0,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_GOAL|AHC_TRANS_CUR,
/*paused*/FALSE);
Add necessary splcam() protection around target mode setup and teardown routines as well as card access that occurs for the AC_LOST_DEVICE async event.
1999-03-08 22:42:52 +00:00
splx(s);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
break;
}
default:
break;
}
}
static void
ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments,
int error)
{
struct scb *scb;
union ccb *ccb;
struct ahc_softc *ahc;
int s;
scb = (struct scb *)arg;
ccb = scb->ccb;
ahc = (struct ahc_softc *)ccb->ccb_h.ccb_ahc_ptr;
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (error != 0) {
if (error == EFBIG)
ahcsetccbstatus(scb->ccb, CAM_REQ_TOO_BIG);
else
ahcsetccbstatus(scb->ccb, CAM_REQ_CMP_ERR);
if (nsegments != 0)
bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap);
ahcfreescb(ahc, scb);
xpt_done(ccb);
return;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (nsegments != 0) {
struct ahc_dma_seg *sg;
bus_dma_segment_t *end_seg;
bus_dmasync_op_t op;
end_seg = dm_segs + nsegments;
/* Copy the first SG into the data pointer area */
scb->hscb->data = dm_segs->ds_addr;
scb->hscb->datalen = dm_segs->ds_len;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
/* Copy the segments into our SG list */
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
sg = scb->sg_list;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
while (dm_segs < end_seg) {
sg->addr = dm_segs->ds_addr;
sg->len = dm_segs->ds_len;
sg++;
dm_segs++;
}
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
/* Note where to find the SG entries in bus space */
scb->hscb->SG_pointer = scb->sg_list_phys;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
op = BUS_DMASYNC_PREREAD;
else
op = BUS_DMASYNC_PREWRITE;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op);
Correct a race condition where a target mode SCB dma could occur before we finished setting the pending phase information. Use the ALL_TARGETS_MASK #define instead of 0xffff for the default ultraenb mask.
1999-02-11 07:07:27 +00:00
if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) {
scb->hscb->cmdpointer |= DPHASE_PENDING;
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
Correct a race condition where a target mode SCB dma could occur before we finished setting the pending phase information. Use the ALL_TARGETS_MASK #define instead of 0xffff for the default ultraenb mask.
1999-02-11 07:07:27 +00:00
scb->hscb->cmdpointer |= (TARGET_DATA_IN << 8);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
/*
* If the transfer is of an odd length and in the
* "in" direction (scsi->HostBus), then it may
* trigger a bug in the 'WideODD' feature of
* non-Ultra2 chips. Force the total data-length
* to be even by adding an extra, 1 byte, SG,
* element. We do this even if we are not currently
* negotiated wide as negotiation could occur before
* this command is executed.
*/
if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN
&& (ccb->csio.dxfer_len & 0x1) != 0
&& (ahc->features & AHC_TARG_DMABUG) != 0) {
nsegments++;
if (nsegments > AHC_NSEG) {
ahcsetccbstatus(scb->ccb,
CAM_REQ_TOO_BIG);
bus_dmamap_unload(ahc->buffer_dmat,
scb->dmamap);
ahcfreescb(ahc, scb);
xpt_done(ccb);
return;
}
sg->addr = ahc->dma_bug_buf;
sg->len = 1;
}
Correct a race condition where a target mode SCB dma could occur before we finished setting the pending phase information. Use the ALL_TARGETS_MASK #define instead of 0xffff for the default ultraenb mask.
1999-02-11 07:07:27 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
scb->hscb->SG_pointer = 0;
scb->hscb->data = 0;
scb->hscb->datalen = 0;
}
scb->sg_count = scb->hscb->SG_count = nsegments;
s = splcam();
/*
* Last time we need to check if this SCB needs to
* be aborted.
*/
if (ahc_ccb_status(ccb) != CAM_REQ_INPROG) {
if (nsegments != 0)
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap);
ahcfreescb(ahc, scb);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_done(ccb);
splx(s);
return;
}
/* Busy this tcl if we are untagged */
if ((scb->hscb->control & TAG_ENB) == 0)
ahc_busy_tcl(ahc, scb);
LIST_INSERT_HEAD(&ahc->pending_ccbs, &ccb->ccb_h,
sim_links.le);
scb->flags |= SCB_ACTIVE;
ccb->ccb_h.status |= CAM_SIM_QUEUED;
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
if (ccb->ccb_h.timeout != CAM_TIME_INFINITY) {
if (ccb->ccb_h.timeout == CAM_TIME_DEFAULT)
ccb->ccb_h.timeout = 5 * 1000;
ccb->ccb_h.timeout_ch =
timeout(ahc_timeout, (caddr_t)scb,
(ccb->ccb_h.timeout * hz) / 1000);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
#if 0
printf("Continueing Immediate Command %d:%d\n",
ccb->ccb_h.target_id, ccb->ccb_h.target_lun);
#endif
pause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if ((ahc->flags & AHC_PAGESCBS) == 0)
ahc_outb(ahc, SCBPTR, scb->hscb->tag);
ahc_outb(ahc, SCB_TAG, scb->hscb->tag);
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
} else {
pause_sequencer(ahc);
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
}
splx(s);
}
static void
ahc_poll(struct cam_sim *sim)
{
ahc_intr(cam_sim_softc(sim));
}
static void
ahc_setup_data(struct ahc_softc *ahc, struct ccb_scsiio *csio,
struct scb *scb)
{
struct hardware_scb *hscb;
struct ccb_hdr *ccb_h;
hscb = scb->hscb;
ccb_h = &csio->ccb_h;
if (ccb_h->func_code == XPT_SCSI_IO) {
hscb->cmdlen = csio->cdb_len;
if ((ccb_h->flags & CAM_CDB_POINTER) != 0) {
if ((ccb_h->flags & CAM_CDB_PHYS) == 0)
if (hscb->cmdlen <= 16) {
memcpy(hscb->cmdstore,
csio->cdb_io.cdb_ptr,
hscb->cmdlen);
hscb->cmdpointer =
hscb->cmdstore_busaddr;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
} else {
ahcsetccbstatus(scb->ccb,
CAM_REQ_INVALID);
xpt_done(scb->ccb);
ahcfreescb(ahc, scb);
return;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
else
hscb->cmdpointer =
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
((intptr_t)csio->cdb_io.cdb_ptr) & 0xffffffff;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
/*
* CCB CDB Data Storage area is only 16 bytes
* so no additional testing is required
*/
memcpy(hscb->cmdstore, csio->cdb_io.cdb_bytes,
hscb->cmdlen);
hscb->cmdpointer = hscb->cmdstore_busaddr;
}
}
/* Only use S/G if there is a transfer */
if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) {
/* We've been given a pointer to a single buffer */
if ((ccb_h->flags & CAM_DATA_PHYS) == 0) {
int s;
int error;
s = splsoftvm();
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
error = bus_dmamap_load(ahc->buffer_dmat,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scb->dmamap,
csio->data_ptr,
csio->dxfer_len,
ahc_execute_scb,
scb, /*flags*/0);
if (error == EINPROGRESS) {
/*
* So as to maintain ordering,
* freeze the controller queue
* until our mapping is
* returned.
*/
xpt_freeze_simq(ahc->sim,
/*count*/1);
scb->ccb->ccb_h.status |=
CAM_RELEASE_SIMQ;
}
splx(s);
} else {
struct bus_dma_segment seg;
/* Pointer to physical buffer */
if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE)
panic("ahc_setup_data - Transfer size "
"larger than can device max");
seg.ds_addr = (bus_addr_t)csio->data_ptr;
seg.ds_len = csio->dxfer_len;
ahc_execute_scb(scb, &seg, 1, 0);
}
} else {
struct bus_dma_segment *segs;
if ((ccb_h->flags & CAM_DATA_PHYS) != 0)
panic("ahc_setup_data - Physical segment "
"pointers unsupported");
if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0)
panic("ahc_setup_data - Virtual segment "
"addresses unsupported");
/* Just use the segments provided */
segs = (struct bus_dma_segment *)csio->data_ptr;
ahc_execute_scb(scb, segs, csio->sglist_cnt, 0);
}
} else {
ahc_execute_scb(scb, NULL, 0, 0);
}
}
static void
ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path)
{
int target;
char channel;
int lun;
target = xpt_path_target_id(path);
lun = xpt_path_lun_id(path);
channel = xpt_path_sim(path)->bus_id == 0 ? 'A' : 'B';
ahc_search_qinfifo(ahc, target, channel, lun,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
CAM_REQUEUE_REQ, SEARCH_COMPLETE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcallocscbs(struct ahc_softc *ahc)
{
struct scb_data *scb_data;
struct scb *next_scb;
struct sg_map_node *sg_map;
bus_addr_t physaddr;
struct ahc_dma_seg *segs;
int newcount;
int i;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scb_data = ahc->scb_data;
if (scb_data->numscbs >= AHC_SCB_MAX)
/* Can't allocate any more */
return;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
next_scb = &scb_data->scbarray[scb_data->numscbs];
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
if (sg_map == NULL)
return;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
/* Allocate S/G space for the next batch of SCBS */
if (bus_dmamem_alloc(scb_data->sg_dmat, (void **)&sg_map->sg_vaddr,
BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
free(sg_map, M_DEVBUF);
return;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
bus_dmamap_load(scb_data->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr,
PAGE_SIZE, ahcdmamapcb, &sg_map->sg_physaddr,
/*flags*/0);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
segs = sg_map->sg_vaddr;
physaddr = sg_map->sg_physaddr;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) {
int error;
next_scb->sg_list = segs;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
/*
* The sequencer always starts with the second entry.
* The first entry is embedded in the scb.
*/
next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
next_scb->flags = SCB_FREE;
error = bus_dmamap_create(ahc->buffer_dmat, /*flags*/0,
&next_scb->dmamap);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (error != 0)
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
break;
next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
next_scb->hscb->tag = ahc->scb_data->numscbs;
next_scb->hscb->cmdstore_busaddr =
ahc_hscb_busaddr(ahc, next_scb->hscb->tag)
+ offsetof(struct hardware_scb, cmdstore);
SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links);
segs += AHC_NSEG;
physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
next_scb++;
ahc->scb_data->numscbs++;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
}
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
#ifdef AHC_DUMP_SEQ
static void
ahc_dumpseq(struct ahc_softc* ahc)
{
int i;
int max_prog;
if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI)
max_prog = 448;
else if ((ahc->features & AHC_ULTRA2) != 0)
max_prog = 768;
else
max_prog = 512;
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
ahc_outb(ahc, SEQADDR0, 0);
ahc_outb(ahc, SEQADDR1, 0);
for (i = 0; i < max_prog; i++) {
u_int8_t ins_bytes[4];
ahc_insb(ahc, SEQRAM, ins_bytes, 4);
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
printf("0x%08x\n", ins_bytes[0] << 24
| ins_bytes[1] << 16
| ins_bytes[2] << 8
| ins_bytes[3]);
Simplify my copyright license terms. aic7xxx.c: Add a function for sucking firmware out of the controller prior to reset. Remove some inline bloat from functions that should not have been inlined. During initialization, wait 1ms after the chip reset before touching any registers. You can get machine checks on certain architectures (Atari I think?) without the delay. Return CAM_REQ_CMP for external BDR requests instead of CAM_BDR_SENT. Bump some messages to bootverbose levels above 1. Don't clear any negotiated sync rate if the target rejects a WDTR message. The sync rate is only cleared if the target accepts a WDTR message. Fix a small bug in the mesgin handling code that could cause us to believe that we had recieved a message that was actually received by another target. This could only confuse us in some very rare transmission negotiation scenarios. Remove some unecessary cleanup of residual information after a residual is reported. The sequencer does this when the command is queued now.
1999-12-06 18:23:31 +00:00
}
}
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
ahc_loadseq(struct ahc_softc *ahc)
{
struct patch *cur_patch;
int i;
int downloaded;
int skip_addr;
u_int8_t download_consts[4];
/* Setup downloadable constant table */
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
#if 0
/* No downloaded constants are currently defined. */
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds;
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
cur_patch = patches;
downloaded = 0;
skip_addr = 0;
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
ahc_outb(ahc, SEQADDR0, 0);
ahc_outb(ahc, SEQADDR1, 0);
for (i = 0; i < sizeof(seqprog)/4; i++) {
if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
/*
* Don't download this instruction as it
* is in a patch that was removed.
*/
continue;
}
ahc_download_instr(ahc, i, download_consts);
downloaded++;
}
ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
restart_sequencer(ahc);
if (bootverbose)
printf(" %d instructions downloaded\n", downloaded);
}
static int
ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
int start_instr, int *skip_addr)
{
struct patch *cur_patch;
struct patch *last_patch;
int num_patches;
num_patches = sizeof(patches)/sizeof(struct patch);
last_patch = &patches[num_patches];
cur_patch = *start_patch;
while (cur_patch < last_patch && start_instr == cur_patch->begin) {
if (cur_patch->patch_func(ahc) == 0) {
/* Start rejecting code */
*skip_addr = start_instr + cur_patch->skip_instr;
cur_patch += cur_patch->skip_patch;
} else {
/* Accepted this patch. Advance to the next
* one and wait for our intruction pointer to
* hit this point.
*/
cur_patch++;
}
}
*start_patch = cur_patch;
if (start_instr < *skip_addr)
/* Still skipping */
return (0);
return (1);
}
static void
ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts)
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
union ins_formats instr;
struct ins_format1 *fmt1_ins;
struct ins_format3 *fmt3_ins;
u_int opcode;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Structure copy */
instr = *(union ins_formats*)&seqprog[instrptr * 4];
fmt1_ins = &instr.format1;
fmt3_ins = NULL;
/* Pull the opcode */
opcode = instr.format1.opcode;
switch (opcode) {
case AIC_OP_JMP:
case AIC_OP_JC:
case AIC_OP_JNC:
case AIC_OP_CALL:
case AIC_OP_JNE:
case AIC_OP_JNZ:
case AIC_OP_JE:
case AIC_OP_JZ:
{
struct patch *cur_patch;
int address_offset;
u_int address;
int skip_addr;
int i;
fmt3_ins = &instr.format3;
address_offset = 0;
address = fmt3_ins->address;
cur_patch = patches;
skip_addr = 0;
for (i = 0; i < address;) {
ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
if (skip_addr > i) {
int end_addr;
end_addr = MIN(address, skip_addr);
address_offset += end_addr - i;
i = skip_addr;
} else {
i++;
}
}
address -= address_offset;
fmt3_ins->address = address;
/* FALLTHROUGH */
}
case AIC_OP_OR:
case AIC_OP_AND:
case AIC_OP_XOR:
case AIC_OP_ADD:
case AIC_OP_ADC:
case AIC_OP_BMOV:
if (fmt1_ins->parity != 0) {
fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
}
fmt1_ins->parity = 0;
/* FALLTHROUGH */
case AIC_OP_ROL:
if ((ahc->features & AHC_ULTRA2) != 0) {
int i, count;
/* Calculate odd parity for the instruction */
for (i = 0, count = 0; i < 31; i++) {
u_int32_t mask;
mask = 0x01 << i;
if ((instr.integer & mask) != 0)
count++;
}
if ((count & 0x01) == 0)
instr.format1.parity = 1;
} else {
/* Compress the instruction for older sequencers */
if (fmt3_ins != NULL) {
instr.integer =
fmt3_ins->immediate
| (fmt3_ins->source << 8)
| (fmt3_ins->address << 16)
| (fmt3_ins->opcode << 25);
} else {
instr.integer =
fmt1_ins->immediate
| (fmt1_ins->source << 8)
| (fmt1_ins->destination << 16)
| (fmt1_ins->ret << 24)
| (fmt1_ins->opcode << 25);
}
}
ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
break;
default:
panic("Unknown opcode encountered in seq program");
break;
}
}
static void
ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) {
if ((scb->flags & SCB_RECOVERY_SCB) == 0) {
struct ccb_hdr *ccbh;
scb->flags |= SCB_RECOVERY_SCB;
/*
* Take all queued, but not sent SCBs out of the equation.
* Also ensure that no new CCBs are queued to us while we
* try to fix this problem.
*/
if ((scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
xpt_freeze_simq(ahc->sim, /*count*/1);
scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
}
/*
* Go through all of our pending SCBs and remove
* any scheduled timeouts for them. We will reschedule
* them after we've successfully fixed this problem.
*/
ccbh = ahc->pending_ccbs.lh_first;
while (ccbh != NULL) {
struct scb *pending_scb;
pending_scb = (struct scb *)ccbh->ccb_scb_ptr;
untimeout(ahc_timeout, pending_scb, ccbh->timeout_ch);
ccbh = ccbh->sim_links.le.le_next;
}
}
}
static void
ahc_timeout(void *arg)
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
struct scb *scb;
struct ahc_softc *ahc;
int s, found;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
u_int last_phase;
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
int target;
int lun;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
int i;
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
char channel;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scb = (struct scb *)arg;
ahc = (struct ahc_softc *)scb->ccb->ccb_h.ccb_ahc_ptr;
s = splcam();
/*
* Ensure that the card doesn't do anything
* behind our back. Also make sure that we
* didn't "just" miss an interrupt that would
* affect this timeout.
*/
do {
ahc_intr(ahc);
pause_sequencer(ahc);
} while (ahc_inb(ahc, INTSTAT) & INT_PEND);
if ((scb->flags & SCB_ACTIVE) == 0) {
/* Previous timeout took care of me already */
printf("Timedout SCB handled by another timeout\n");
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
splx(s);
return;
}
target = SCB_TARGET(scb);
channel = SCB_CHANNEL(scb);
lun = SCB_LUN(scb);
xpt_print_path(scb->ccb->ccb_h.path);
printf("SCB 0x%x - timed out ", scb->hscb->tag);
/*
* Take a snapshot of the bus state and print out
* some information so we can track down driver bugs.
*/
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
last_phase = ahc_inb(ahc, LASTPHASE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
for (i = 0; i < num_phases; i++) {
if (last_phase == phase_table[i].phase)
break;
}
printf("%s", phase_table[i].phasemsg);
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
printf(", SEQADDR == 0x%x\n",
ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
#if 0
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1));
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3));
printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE));
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET));
printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS));
printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR)
| ahc_inb(ahc, SCB_DATAPTR + 1) << 8
| ahc_inb(ahc, SCB_DATAPTR + 2) << 16
| ahc_inb(ahc, SCB_DATAPTR + 3) << 24);
printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT)
| ahc_inb(ahc, SCB_DATACNT + 1) << 8
| ahc_inb(ahc, SCB_DATACNT + 2) << 16);
printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL));
printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT));
printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL));
printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS));
printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT));
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
if (scb->sg_count > 0) {
for (i = 0; i < scb->sg_count; i++) {
printf("sg[%d] - Addr 0x%x : Length %d\n",
i,
scb->sg_list[i].addr,
scb->sg_list[i].len);
}
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
#endif
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Been down this road before.
* Do a full bus reset.
*/
bus_reset:
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scb->ccb, CAM_CMD_TIMEOUT);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE);
printf("%s: Issued Channel %c Bus Reset. "
"%d SCBs aborted\n", ahc_name(ahc), channel, found);
} else {
/*
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
* If we are a target, transition to bus free and report
* the timeout.
*
* The target/initiator that is holding up the bus may not
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
* be the same as the one that triggered this timeout
* (different commands have different timeout lengths).
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
* If the bus is idle and we are actiing as the initiator
* for this request, queue a BDR message to the timed out
* target. Otherwise, if the timed out transaction is
* active:
* Initiator transaction:
* Stuff the message buffer with a BDR message and assert
* ATN in the hopes that the target will let go of the bus
* and go to the mesgout phase. If this fails, we'll
* get another timeout 2 seconds later which will attempt
* a bus reset.
*
* Target transaction:
* Transition to BUS FREE and report the error.
* It's good to be the target!
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int active_scb_index;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
active_scb_index = ahc_inb(ahc, SCB_TAG);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (last_phase != P_BUSFREE
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
&& (active_scb_index < ahc->scb_data->numscbs)) {
struct scb *active_scb;
/*
* If the active SCB is not from our device,
* assume that another device is hogging the bus
* and wait for it's timeout to expire before
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
* taking additional action.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
active_scb = &ahc->scb_data->scbarray[active_scb_index];
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (active_scb->hscb->tcl != scb->hscb->tcl) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
struct ccb_hdr *ccbh;
u_int newtimeout;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
xpt_print_path(scb->ccb->ccb_h.path);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
printf("Other SCB Timeout%s",
(scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
? " again\n" : "\n");
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
scb->flags |= SCB_OTHERTCL_TIMEOUT;
newtimeout = MAX(active_scb->ccb->ccb_h.timeout,
scb->ccb->ccb_h.timeout);
ccbh = &scb->ccb->ccb_h;
scb->ccb->ccb_h.timeout_ch =
timeout(ahc_timeout, scb,
(newtimeout * hz) / 1000);
splx(s);
return;
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
}
/* It's us */
if ((scb->hscb->control & TARGET_SCB) != 0) {
/*
* Send back any queued up transactions
* and properly record the error condition.
*/
ahc_freeze_devq(ahc, scb->ccb->ccb_h.path);
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scb->ccb, CAM_CMD_TIMEOUT);
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
ahc_freeze_ccb(scb->ccb);
ahc_done(ahc, scb);
/* Will clear us from the bus */
restart_sequencer(ahc);
return;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_set_recoveryscb(ahc, active_scb);
ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
xpt_print_path(active_scb->ccb->ccb_h.path);
printf("BDR message in message buffer\n");
active_scb->flags |= SCB_DEVICE_RESET;
active_scb->ccb->ccb_h.timeout_ch =
timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
int disconnected;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/* XXX Shouldn't panic. Just punt instead */
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((scb->hscb->control & TARGET_SCB) != 0)
panic("Timed-out target SCB but bus idle");
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (last_phase != P_BUSFREE
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
&& (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/* XXX What happened to the SCB? */
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
/* Hung target selection. Goto busfree */
printf("%s: Hung target selection\n",
ahc_name(ahc));
restart_sequencer(ahc);
return;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (ahc_search_qinfifo(ahc, target, channel, lun,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
scb->hscb->tag, ROLE_INITIATOR,
/*status*/0, SEARCH_COUNT) > 0) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
disconnected = FALSE;
} else {
disconnected = TRUE;
}
if (disconnected) {
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
u_int active_scb;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_set_recoveryscb(ahc, scb);
/*
* Simply set the MK_MESSAGE control bit.
*/
scb->hscb->control |= MK_MESSAGE;
scb->flags |= SCB_QUEUED_MSG
| SCB_DEVICE_RESET;
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
/*
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
* Mark the cached copy of this SCB in the
* disconnected list too, so that a reconnect
* at this point causes a BDR or abort.
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
*/
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
active_scb = ahc_inb(ahc, SCBPTR);
if (ahc_search_disc_list(ahc, target,
channel, lun,
scb->hscb->tag,
/*stop_on_first*/TRUE,
/*remove*/FALSE,
/*save_state*/FALSE)) {
u_int scb_control;
scb_control = ahc_inb(ahc, SCB_CONTROL);
scb_control |= MK_MESSAGE;
ahc_outb(ahc, SCB_CONTROL, scb_control);
}
ahc_outb(ahc, SCBPTR, active_scb);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
ahc_index_busy_tcl(ahc, scb->hscb->tcl,
/*unbusy*/TRUE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Actually re-queue this SCB in case we can
* select the device before it reconnects.
* Clear out any entries in the QINFIFO first
* so we are the next SCB for this target
* to run.
*/
ahc_search_qinfifo(ahc, SCB_TARGET(scb),
channel, SCB_LUN(scb),
SCB_LIST_NULL,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ROLE_INITIATOR,
Correct an "argument reversal" bug that could cause commands requed from the input fifo to be returned as successful and frozen. Most, if not all, peripheral drivers do not check the qfrozen bit for successfully completed commands, so the result would not only be lost commands, but devices locked out from receiving commands. This was a bad bug that crept in two or three months ago during some target mode work.
1999-12-20 21:32:32 +00:00
CAM_REQUEUE_REQ,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
SEARCH_COMPLETE);
xpt_print_path(scb->ccb->ccb_h.path);
printf("Queuing a BDR SCB\n");
ahc->qinfifo[ahc->qinfifonext++] =
scb->hscb->tag;
if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, HNSCB_QOFF,
ahc->qinfifonext);
} else {
ahc_outb(ahc, KERNEL_QINPOS,
ahc->qinfifonext);
}
scb->ccb->ccb_h.timeout_ch =
timeout(ahc_timeout, (caddr_t)scb, 2 * hz);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
} else {
/* Go "immediatly" to the bus reset */
/* This shouldn't happen */
ahc_set_recoveryscb(ahc, scb);
xpt_print_path(scb->ccb->ccb_h.path);
printf("SCB %d: Immediate reset. "
"Flags = 0x%x\n", scb->hscb->tag,
scb->flags);
goto bus_reset;
}
}
}
splx(s);
}
static int
ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
int lun, u_int tag, role_t role, u_int32_t status,
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_search_action action)
{
struct scb *scbp;
u_int8_t qinpos;
u_int8_t qintail;
int found;
qinpos = ahc_inb(ahc, QINPOS);
qintail = ahc->qinfifonext;
found = 0;
/*
* Start with an empty queue. Entries that are not chosen
* for removal will be re-added to the queue as we go.
*/
ahc->qinfifonext = qinpos;
while (qinpos != qintail) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]];
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (ahc_match_scb(scbp, target, channel, lun, tag, role)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* We found an scb that needs to be removed.
*/
switch (action) {
case SEARCH_COMPLETE:
if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG)
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scbp->ccb, status);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_freeze_ccb(scbp->ccb);
ahc_done(ahc, scbp);
break;
case SEARCH_COUNT:
ahc->qinfifo[ahc->qinfifonext++] =
scbp->hscb->tag;
break;
case SEARCH_REMOVE:
break;
}
found++;
} else {
ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag;
}
qinpos++;
}
if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
} else {
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
}
return (found);
}
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
static void
ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
{
union ccb *abort_ccb;
abort_ccb = ccb->cab.abort_ccb;
switch (abort_ccb->ccb_h.func_code) {
case XPT_ACCEPT_TARGET_IO:
case XPT_IMMED_NOTIFY:
case XPT_CONT_TARGET_IO:
{
struct tmode_tstate *tstate;
struct tmode_lstate *lstate;
struct ccb_hdr_slist *list;
cam_status status;
status = ahc_find_tmode_devs(ahc, sim, abort_ccb, &tstate,
&lstate, TRUE);
if (status != CAM_REQ_CMP) {
ccb->ccb_h.status = status;
break;
}
if (abort_ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO)
list = &lstate->accept_tios;
else if (abort_ccb->ccb_h.func_code == XPT_IMMED_NOTIFY)
list = &lstate->immed_notifies;
else
list = NULL;
if (list != NULL) {
struct ccb_hdr *curelm;
int found;
curelm = SLIST_FIRST(list);
found = 0;
if (curelm == &abort_ccb->ccb_h) {
found = 1;
SLIST_REMOVE_HEAD(list, sim_links.sle);
} else {
while(curelm != NULL) {
struct ccb_hdr *nextelm;
nextelm =
SLIST_NEXT(curelm, sim_links.sle);
if (nextelm == &abort_ccb->ccb_h) {
found = 1;
SLIST_NEXT(curelm,
sim_links.sle) =
SLIST_NEXT(nextelm,
sim_links.sle);
break;
}
curelm = nextelm;
}
}
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (found) {
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
abort_ccb->ccb_h.status = CAM_REQ_ABORTED;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
xpt_done(abort_ccb);
ccb->ccb_h.status = CAM_REQ_CMP;
} else {
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
printf("Not found\n");
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
ccb->ccb_h.status = CAM_PATH_INVALID;
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
}
Perform a save data pointers operation if a data transfer was performed in target mode, but we are not completing the command. Use a template of allowed bus arbitration phases to selectively and dynamically enable/disable initiator or target (re)selection. Properly handle timeouts for target role transactions - just go to the bus free state and report the error to the peripheral driver. Checkpoint support for the XPT_ABORT_CCB function code. This currently handles the accept tio and immediate notify ccb types, but does not handle the continue target I/O or SCSI I/O ccb types. This is enough to handle dynamic target enable/disable events. Clean up the SCSI reset code so that we perform at most 1 SCSI bus reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
break;
}
/* FALLTHROUGH */
}
case XPT_SCSI_IO:
/* XXX Fully implement the hard ones */
ccb->ccb_h.status = CAM_UA_ABORT;
break;
default:
ccb->ccb_h.status = CAM_REQ_INVALID;
break;
}
xpt_done(ccb);
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Abort all SCBs that match the given description (target/channel/lun/tag),
* setting their status to the passed in status if the status has not already
* been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
* is paused before it is called.
*/
static int
ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
int lun, u_int tag, role_t role, u_int32_t status)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
struct scb *scbp;
u_int active_scb;
int i;
int found;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* restore this when we're done */
active_scb = ahc_inb(ahc, SCBPTR);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
Correct an "argument reversal" bug that could cause commands requed from the input fifo to be returned as successful and frozen. Most, if not all, peripheral drivers do not check the qfrozen bit for successfully completed commands, so the result would not only be lost commands, but devices locked out from receiving commands. This was a bad bug that crept in two or three months ago during some target mode work.
1999-12-20 21:32:32 +00:00
role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Search waiting for selection list.
*/
{
u_int8_t next, prev;
next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
prev = SCB_LIST_NULL;
while (next != SCB_LIST_NULL) {
u_int8_t scb_index;
ahc_outb(ahc, SCBPTR, next);
scb_index = ahc_inb(ahc, SCB_TAG);
if (scb_index >= ahc->scb_data->numscbs) {
panic("Waiting List inconsistency. "
"SCB index == %d, yet numscbs == %d.",
scb_index, ahc->scb_data->numscbs);
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scbp = &ahc->scb_data->scbarray[scb_index];
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (ahc_match_scb(scbp, target, channel,
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
lun, SCB_LIST_NULL, role)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
next = ahc_abort_wscb(ahc, next, prev);
} else {
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
}
}
}
/*
* Go through the disconnected list and remove any entries we
* have queued for completion, 0'ing their control byte too.
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
* We save the active SCB and restore it ourselves, so there
* is no reason for this search to restore it too.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
ahc_search_disc_list(ahc, target, channel, lun, tag,
/*stop_on_first*/FALSE, /*remove*/TRUE,
/*save_state*/FALSE);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Go through the hardware SCB array looking for commands that
* were active but not on any list.
*/
for(i = 0; i < ahc->scb_data->maxhscbs; i++) {
Remove unused variables and functions. In the rejected message handler, it was possible for us to confuse a rejected SDTR or WDTR for a rejected tag.
1998-09-20 23:30:14 +00:00
u_int scbid;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SCBPTR, i);
scbid = ahc_inb(ahc, SCB_TAG);
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
scbp = &ahc->scb_data->scbarray[scbid];
if (scbid < ahc->scb_data->numscbs
&& ahc_match_scb(scbp, target, channel, lun, tag, role))
ahc_add_curscb_to_free_list(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Go through the pending CCB list and look for
* commands for this target that are still active.
* These are other tagged commands that were
* disconnected when the reset occured.
*/
{
struct ccb_hdr *ccb_h;
ccb_h = ahc->pending_ccbs.lh_first;
while (ccb_h != NULL) {
scbp = (struct scb *)ccb_h->ccb_scb_ptr;
ccb_h = ccb_h->sim_links.le.le_next;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (ahc_match_scb(scbp, target, channel,
lun, tag, role)) {
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG)
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
ahcsetccbstatus(scbp->ccb, status);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_freeze_ccb(scbp->ccb);
ahc_done(ahc, scbp);
found++;
}
}
}
ahc_outb(ahc, SCBPTR, active_scb);
return found;
}
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static int
ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
int lun, u_int tag, int stop_on_first, int remove,
int save_state)
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
{
struct scb *scbp;
u_int next;
u_int prev;
u_int count;
u_int active_scb;
count = 0;
next = ahc_inb(ahc, DISCONNECTED_SCBH);
prev = SCB_LIST_NULL;
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (save_state) {
/* restore this when we're done */
active_scb = ahc_inb(ahc, SCBPTR);
} else
/* Silence compiler */
active_scb = SCB_LIST_NULL;
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
while (next != SCB_LIST_NULL) {
u_int scb_index;
ahc_outb(ahc, SCBPTR, next);
scb_index = ahc_inb(ahc, SCB_TAG);
if (scb_index >= ahc->scb_data->numscbs) {
panic("Disconnected List inconsistency. "
"SCB index == %d, yet numscbs == %d.",
scb_index, ahc->scb_data->numscbs);
}
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
scbp = &ahc->scb_data->scbarray[scb_index];
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (ahc_match_scb(scbp, target, channel, lun,
tag, ROLE_INITIATOR)) {
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
count++;
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (remove) {
next =
ahc_rem_scb_from_disc_list(ahc, prev, next);
} else {
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
}
if (stop_on_first)
break;
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
} else {
prev = next;
next = ahc_inb(ahc, SCB_NEXT);
}
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
if (save_state)
ahc_outb(ahc, SCBPTR, active_scb);
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
return (count);
}
static u_int
ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int next;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SCBPTR, scbptr);
next = ahc_inb(ahc, SCB_NEXT);
ahc_outb(ahc, SCB_CONTROL, 0);
ahc_add_curscb_to_free_list(ahc);
if (prev != SCB_LIST_NULL) {
ahc_outb(ahc, SCBPTR, prev);
ahc_outb(ahc, SCB_NEXT, next);
} else
ahc_outb(ahc, DISCONNECTED_SCBH, next);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
return (next);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
{
/* Invalidate the tag so that ahc_find_scb doesn't think it's active */
ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
}
/*
* Manipulate the waiting for selection list and return the
* scb that follows the one that we remove.
*/
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
static u_int
ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
u_int curscb, next;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Select the SCB we want to abort and
* pull the next pointer out of it.
*/
curscb = ahc_inb(ahc, SCBPTR);
ahc_outb(ahc, SCBPTR, scbpos);
next = ahc_inb(ahc, SCB_NEXT);
/* Clear the necessary fields */
ahc_outb(ahc, SCB_CONTROL, 0);
ahc_add_curscb_to_free_list(ahc);
/* update the waiting list */
if (prev == SCB_LIST_NULL) {
/* First in the list */
ahc_outb(ahc, WAITING_SCBH, next);
/*
* Ensure we aren't attempting to perform
* selection for this entry.
*/
ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
} else {
/*
* Select the scb that pointed to us
* and update its next pointer.
*/
ahc_outb(ahc, SCBPTR, prev);
ahc_outb(ahc, SCB_NEXT, next);
}
/*
* Point us back at the original scb position.
*/
ahc_outb(ahc, SCBPTR, curscb);
return next;
}
static void
ahc_clear_intstat(struct ahc_softc *ahc)
{
/* Clear any interrupt conditions this may have caused */
ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
|CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
CLRREQINIT);
ahc_outb(ahc, CLRINT, CLRSCSIINT);
}
static void
ahc_reset_current_bus(struct ahc_softc *ahc)
{
u_int8_t scsiseq;
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
scsiseq = ahc_inb(ahc, SCSISEQ);
ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
DELAY(AHC_BUSRESET_DELAY);
/* Turn off the bus reset */
ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
ahc_clear_intstat(ahc);
/* Re-enable reset interrupts */
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
}
static int
ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
{
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct cam_path *path;
u_int initiator, target, max_scsiid;
u_int sblkctl;
u_int our_id;
int found;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
int restart_needed;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
char cur_channel;
ahc->pending_device = NULL;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
pause_sequencer(ahc);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/*
* Run our command complete fifos to ensure that we perform
* completion processing on any commands that 'completed'
* before the reset occurred.
*/
ahc_run_qoutfifo(ahc);
if ((ahc->flags & AHC_TARGETMODE) != 0) {
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
ahc_run_tqinfifo(ahc, /*paused*/TRUE);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
}
/*
* Reset the bus if we are initiating this reset
*/
sblkctl = ahc_inb(ahc, SBLKCTL);
cur_channel = 'A';
if ((ahc->features & AHC_TWIN) != 0
&& ((sblkctl & SELBUSB) != 0))
cur_channel = 'B';
if (cur_channel != channel) {
/* Case 1: Command for another bus is active
* Stealthily reset the other bus without
* upsetting the current bus.
*/
ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
if (initiate_reset)
ahc_reset_current_bus(ahc);
ahc_clear_intstat(ahc);
ahc_outb(ahc, SBLKCTL, sblkctl);
restart_needed = FALSE;
} else {
/* Case 2: A command from this bus is active or we're idle */
ahc_clear_msg_state(ahc);
ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
ahc_outb(ahc, SCSISEQ,
ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
if (initiate_reset)
ahc_reset_current_bus(ahc);
ahc_clear_intstat(ahc);
/*
* Since we are going to restart the sequencer, avoid
* a race in the sequencer that could cause corruption
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
* of our Q pointers by starting over from index 1.
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
*/
ahc->qoutfifonext = 0;
if ((ahc->features & AHC_QUEUE_REGS) != 0)
ahc_outb(ahc, SDSCB_QOFF, 0);
else
ahc_outb(ahc, QOUTPOS, 0);
if ((ahc->flags & AHC_TARGETMODE) != 0) {
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
ahc->tqinfifonext = 1;
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
if ((ahc->features & AHC_HS_MAILBOX) != 0) {
u_int hs_mailbox;
hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
hs_mailbox &= ~HOST_TQINPOS;
ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
}
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
}
restart_needed = TRUE;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/*
* Clean up all the state information for the
* pending transactions on this bus.
*/
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
CAM_LUN_WILDCARD, SCB_LIST_NULL,
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (channel == 'B') {
path = ahc->path_b;
our_id = ahc->our_id_b;
} else {
path = ahc->path;
our_id = ahc->our_id;
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
/*
* Send an immediate notify ccb to all target more peripheral
* drivers affected by this action.
*/
for (target = 0; target <= max_scsiid; target++) {
struct tmode_tstate* tstate;
u_int lun;
tstate = ahc->enabled_targets[target];
if (tstate == NULL)
continue;
for (lun = 0; lun <= 7; lun++) {
struct tmode_lstate* lstate;
lstate = tstate->enabled_luns[lun];
if (lstate == NULL)
continue;
ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
EVENT_TYPE_BUS_RESET, /*arg*/0);
ahc_send_lstate_events(ahc, lstate);
}
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Notify the XPT that a bus reset occurred */
xpt_async(AC_BUS_RESET, path, NULL);
/*
* Revert to async/narrow transfers until we renegotiate.
*/
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
for (target = 0; target <= max_scsiid; target++) {
if (ahc->enabled_targets[target] == NULL)
continue;
for (initiator = 0; initiator <= max_scsiid; initiator++) {
struct ahc_devinfo devinfo;
ahc_compile_devinfo(&devinfo, target, initiator,
CAM_LUN_WILDCARD,
channel, ROLE_UNKNOWN);
ahc_set_width(ahc, &devinfo, path,
MSG_EXT_WDTR_BUS_8_BIT,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
AHC_TRANS_CUR, /*paused*/TRUE);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ahc_set_syncrate(ahc, &devinfo, path,
/*syncrate*/NULL, /*period*/0,
Correct a bug where the chip could be unpaused in the middle of a bus or device reset error recovery operation.
1999-05-18 03:58:49 +00:00
/*offset*/0, AHC_TRANS_CUR,
/*paused*/TRUE);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
}
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (restart_needed)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
restart_sequencer(ahc);
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
else
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
unpause_sequencer(ahc);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return found;
}
static int
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
ahc_match_scb(struct scb *scb, int target, char channel,
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
int lun, u_int tag, role_t role)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
int targ = SCB_TARGET(scb);
char chan = SCB_CHANNEL(scb);
int slun = SCB_LUN(scb);
int match;
match = ((chan == channel) || (channel == ALL_CHANNELS));
if (match != 0)
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
if (match != 0)
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
if (match != 0) {
int group;
group = XPT_FC_GROUP(scb->ccb->ccb_h.func_code);
if (role == ROLE_INITIATOR) {
match = (group == XPT_FC_GROUP_COMMON)
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
&& ((tag == scb->hscb->tag)
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
|| (tag == SCB_LIST_NULL));
} else if (role == ROLE_TARGET) {
match = (group == XPT_FC_GROUP_TMODE)
&& ((tag == scb->ccb->csio.tag_id)
|| (tag == SCB_LIST_NULL));
}
}
Kill the "unpause_always" argument to unpause_sequencer(). The reasons for optimizing the unpause operation no-longer exist, and this is much safer. When restarting the sequencer, reconstitute the free SCB list on the card. This deals with a single instruction gap between marking the SCB as free and actually getting it onto the free list. Reduce the number of transfer negotiations that occur. In the past, we renegotiated after every reported check condition status. This ensures that we catch devices that have unexpectidly reset. In this situation, the target will always report the check condition before performing a data-phase. The new behavior is to renegotiate for any check-condition where the residual matches the orginal data-length of the command (including 0 length transffers). This avoids renegotiations during things like variable tape block reads, where the check condition is reported only to indicate the residual of the read. Revamp the parity error detection logic. We now properly report and handle injected parity errors in all phases. The old code used to hang on message-in parity errors. Correct the reporting of selection timeout errors to the XPT. When a selection timeout occurs, only the currently selecting command is flagged with SELTO status instead of aborting all currently active commands to that target. Fix flipped arguments in ahc_match_scb and in some of the callers of this routine. I wish that gcc allowed you to request warnings for enums passed as ints. Make ahc_find_msg generically handle all message types. Work around the target mode data-in wideodd bug in all non-U2 chips. We can now do sync-wide target mode transfers in target mode across the hole product line. Use lastphase exclusively for handling timeouts. The current phase doesn't take the bus free state into account. Fix a bug in the timeout handler that could cause corruption of the disconnected list. When sending an embedded cdb to a target, ensure that we start on a quad word boundary in the data-fifo. It seems that unaligned stores do not work correctly.
2000-02-09 21:25:00 +00:00
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
return match;
}
static void
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
ahc->msgout_buf[ahc->msgout_index++] = period;
ahc->msgout_buf[ahc->msgout_index++] = offset;
ahc->msgout_len += 5;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
Correct a bug in the timeout handler. When queuing a BDR response to a timeout, we must remove the pending SCB from the disconnected list or risk list corruption when our BDR request using the same SCB is placed on the waiting list. Eradicate some silly uses of u_int8_t that just serve to slow the code down.
1998-09-20 05:06:10 +00:00
ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
ahc->msgout_buf[ahc->msgout_index++] = bus_width;
ahc->msgout_len += 4;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
static void
ahc_calc_residual(struct scb *scb)
{
struct hardware_scb *hscb;
hscb = scb->hscb;
/*
* If the disconnected flag is still set, this is bogus
* residual information left over from a sequencer
* pagin/pageout, so ignore this case.
*/
if ((scb->hscb->control & DISCONNECTED) == 0) {
u_int32_t resid;
int resid_sgs;
int sg;
/*
* Remainder of the SG where the transfer
* stopped.
*/
resid = (hscb->residual_data_count[2] << 16)
| (hscb->residual_data_count[1] <<8)
| (hscb->residual_data_count[0]);
/*
* Add up the contents of all residual
* SG segments that are after the SG where
* the transfer stopped.
*/
resid_sgs = scb->hscb->residual_SG_count - 1/*current*/;
Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ.
2000-01-07 23:08:20 +00:00
sg = scb->sg_count - resid_sgs;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
while (resid_sgs > 0) {
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
resid += scb->sg_list[sg].len;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
sg++;
resid_sgs--;
}
if ((scb->flags & SCB_SENSE) == 0) {
scb->ccb->csio.resid = resid;
} else {
scb->ccb->csio.sense_resid = resid;
}
o Correct the offsets into the syncrate table for paritcular negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets where not properly updated when the DT entry was added and so the driver could attempt to negotiate a speed faster than that supported by the target device or even requested by the user via SCSI-Select settings. * o Update the target mode incoming command queue kernel index value ever 128 commands instead of 32. This means that the kernel will always try to keep its index (as seen on the card - the kernel may actually have cleared more space) 128 commands ahead of where the sequencer is adding entries. o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location in SRAM to indicate the kernel's target queue possition on Ultra2 cards. This avoids the "pause bug" on these cards and also turns out to be much more efficient. o When enabling or disabling a particular target id for target mode, make sure that the taret id in the SCSIID register does not reference an ID that is not to receive target selections. This is only an issue on chips that support the multiple target id feature where the value in SCSIID will still affect selection behavior regardless of the values in the target id bit field registers. o Remove some target mode debugging printfs. o Make sure that the sense length reported in ATIO commands is always zero. This driver does not, yet, report HBA generated sense information for accepted commands. o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for the CCB timeout field. o Make the driver compile with AHC_DEBUG again. * Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
2000-03-18 22:28:20 +00:00
#ifdef AHC_DEBUG
if (ahc_debug & AHC_SHOWMISC) {
xpt_print_path(scb->ccb->ccb_h.path);
printf("Handled Residual of %d bytes\n", resid);
}
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
}
/*
* Clean out the residual information in this SCB for its
* next consumer.
*/
hscb->residual_SG_count = 0;
}
static void
ahc_update_pending_syncrates(struct ahc_softc *ahc)
{
struct ccb_hdr *ccbh;
int pending_ccb_count;
int i;
u_int saved_scbptr;
/*
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
* Traverse the pending SCB list and ensure that all of the
* SCBs there have the proper settings.
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
*/
ccbh = LIST_FIRST(&ahc->pending_ccbs);
pending_ccb_count = 0;
while (ccbh != NULL) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_devinfo devinfo;
union ccb *ccb;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
struct scb *pending_scb;
struct hardware_scb *pending_hscb;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
u_int our_id, remote_id;
ccb = (union ccb*)ccbh;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
pending_scb = (struct scb *)ccbh->ccb_scb_ptr;
pending_hscb = pending_scb->hscb;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (ccbh->func_code == XPT_CONT_TARGET_IO) {
our_id = ccb->ccb_h.target_id;
remote_id = ccb->ctio.init_id;
} else {
our_id = SCB_IS_SCSIBUS_B(pending_scb)
? ahc->our_id_b : ahc->our_id;
remote_id = ccb->ccb_h.target_id;
}
ahc_compile_devinfo(&devinfo, our_id, remote_id,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
SCB_LUN(pending_scb),
SCB_CHANNEL(pending_scb),
ROLE_UNKNOWN);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
our_id, remote_id, &tstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
pending_hscb->control &= ~ULTRAENB;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((tstate->ultraenb & devinfo.target_mask) != 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
pending_hscb->control |= ULTRAENB;
pending_hscb->scsirate = tinfo->scsirate;
pending_hscb->scsioffset = tinfo->current.offset;
pending_ccb_count++;
ccbh = LIST_NEXT(ccbh, sim_links.le);
}
if (pending_ccb_count == 0)
return;
saved_scbptr = ahc_inb(ahc, SCBPTR);
/* Ensure that the hscbs down on the card match the new information */
for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
u_int scb_tag;
ahc_outb(ahc, SCBPTR, i);
scb_tag = ahc_inb(ahc, SCB_TAG);
if (scb_tag != SCB_LIST_NULL) {
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_devinfo devinfo;
union ccb *ccb;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
struct scb *pending_scb;
struct hardware_scb *pending_hscb;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
struct ahc_initiator_tinfo *tinfo;
struct tmode_tstate *tstate;
u_int our_id, remote_id;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
u_int control;
Complete conversion to bus dma. This driver now works on the alpha. aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
1999-04-23 23:27:31 +00:00
pending_scb = &ahc->scb_data->scbarray[scb_tag];
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if (pending_scb->flags == SCB_FREE)
continue;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
pending_hscb = pending_scb->hscb;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
ccb = pending_scb->ccb;
if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) {
our_id = ccb->ccb_h.target_id;
remote_id = ccb->ctio.init_id;
} else {
our_id = SCB_IS_SCSIBUS_B(pending_scb)
? ahc->our_id_b : ahc->our_id;
remote_id = ccb->ccb_h.target_id;
}
ahc_compile_devinfo(&devinfo, our_id, remote_id,
Revamp the way that exceptional message handling is performed so that it is more robust and common code can be used for both the target and iniator roles. The mechanism for tracking negotiation state has also been simplified. Add support for sync/wide negotiation in target mode and fix many of the target mode bugs running at higher speeds uncovered. Make a first stab at getting all of the bus skew delays correct. Sync+Wide dataout transfers still cause problems, but this may be an initiator problem. Ensure that we exit BITBUCKET mode if the controller is restarted. Add support for target mode only firmware downloads. This has been tested on the aic7880, but should mean that we can perform target mode on any aic7xxx controller. Mixed mode (initiator and target roles in the same firmware load) is currently only supported on the aic7890, but with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
SCB_LUN(pending_scb),
SCB_CHANNEL(pending_scb),
ROLE_UNKNOWN);
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
our_id, remote_id, &tstate);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
control = ahc_inb(ahc, SCB_CONTROL);
control &= ~ULTRAENB;
Keep track of negotiated transfer parameters for each initiator<->target connection. Clean up support for devices featuring the multiple target SCSI ID feature. On aic7890/91/96/97 chips, we can now assume the target role on multiple target ids simultaneously. Although these chips also have sufficient instruction space to hold to support the initiator and target role at the same time, the initiator role is currently disabled as it will conflict (chip design restriction) with the multi-tid feature. I'll probably add a nob to enable the initiator (there-by disabling multi-tid) some time in the future. Return queue full or busy, depending on the tagged nature of the incoming request, if our command input queue fills up in host memeory. Deal with accept target I/O resource shortages. If we get an underrun on a transaction that wasn't supposed to transmit any data, don't attempt to print out the S/G list. The code would run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
if ((tstate->ultraenb & devinfo.target_mask) != 0)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
control |= ULTRAENB;
ahc_outb(ahc, SCB_CONTROL, control);
ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate);
ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset);
}
}
ahc_outb(ahc, SCBPTR, saved_scbptr);
}
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
#if UNUSED
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
ahc_dump_targcmd(struct target_cmd *cmd)
{
u_int8_t *byte;
u_int8_t *last_byte;
int i;
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
byte = &cmd->initiator_channel;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
/* Debugging info for received commands */
Change the delivery mechanism for incoming target commands. We now use a 256 entry ring buffer of descriptersfor this purpose. This allows the use of a simple 8bit counter in the sequencer code for tracking start location. Entries in the ring buffer now contain a "cmd_valid" byte at their tail. As an entry is serviced, this byte is cleared by the kernel and set by the sequencer during its dma of a new entry. Since this byte is the last portion of the command touched during a dma, the kernel can use this byte to ensure the command it processes is completely valid. The new command format requires a fixed sized DMA from the controller to deliver which allowed for additional simplification of the sequencer code. The hack that required 1 SCB slot to be stolen for incoming command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
last_byte = &cmd[1].initiator_channel;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
i = 0;
while (byte < last_byte) {
if (i == 0)
printf("\t");
printf("%#x", *byte++);
i++;
if (i == 8) {
printf("\n");
i = 0;
} else {
printf(", ");
}
}
}
Fix a few problems with handling rejected transfer negotiation messages. Use the host message loop for any unknown message types instead of performing a reject message in the sequencer. Pass reject messages to the host message loop too which frees up a sequencer interrupt type slot. Default to issuing a bus reset if initiator mode is enabled. It seems that the reset scsi bus bit is not defined in the same location for all aic78xx BIOSes, so attempting to honor this setting will have to wait until I get more information on how to detect it. Nuke some unused variables.
1998-12-17 00:06:52 +00:00
#endif
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
static void
Implement a new generic mechanism for attaching handler functions to events, in order to pave the way for removing a number of the ad-hoc implementations currently in use. Retire the at_shutdown family of functions and replace them with new event handler lists. Rework kern_shutdown.c to take greater advantage of the use of event handlers. Reviewed by: green
1999-08-21 06:24:40 +00:00
ahc_shutdown(void *arg, int howto)
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
{
struct ahc_softc *ahc;
int i;
Preserve termination settings across the card reset in our shutdown hook.
1999-04-19 21:28:15 +00:00
u_int sxfrctl1_a, sxfrctl1_b;
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc = (struct ahc_softc *)arg;
Preserve termination settings across the card reset in our shutdown hook.
1999-04-19 21:28:15 +00:00
pause_sequencer(ahc);
/*
* Preserve the value of the SXFRCTL1 register for all channels.
* It contains settings that affect termination and we don't want
* to disturb the integrity of the bus during shutdown in case
* we are in a multi-initiator setup.
*/
sxfrctl1_b = 0;
if ((ahc->features & AHC_TWIN) != 0) {
u_int sblkctl;
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
}
sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
/* This will reset most registers to 0, but not all */
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_reset(ahc);
Preserve termination settings across the card reset in our shutdown hook.
1999-04-19 21:28:15 +00:00
if ((ahc->features & AHC_TWIN) != 0) {
u_int sblkctl;
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
}
ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
Massive overhaul of the aic7xxx driver: - Convert to CAM - Use a new DMA based queuing and paging scheme - Add preliminary target mode support - Add support for the aic789X chips - Take advantage of external SRAM on more controllers. - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
ahc_outb(ahc, SCSISEQ, 0);
ahc_outb(ahc, SXFRCTL0, 0);
ahc_outb(ahc, DSPCISTATUS, 0);
for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++)
ahc_outb(ahc, i, 0);
}
Add support for issuing immediate notify event ccbs for bus resets, bdr messages, abort messages, and abort tag messages. Fix a bug in how default transfer negotiations are handled if the user had disabled initial bus resets. Support multi-targetid on the aic7895C.
1999-08-16 22:49:29 +00:00
/*
* Add a target mode event to this lun's queue
*/
static void
ahc_queue_lstate_event(struct ahc_softc *ahc, struct tmode_lstate *lstate,
u_int initiator_id, u_int event_type, u_int event_arg)
{
struct ahc_tmode_event *event;
int pending;
xpt_freeze_devq(lstate->path, /*count*/1);
if (lstate->event_w_idx >= lstate->event_r_idx)
pending = lstate->event_w_idx - lstate->event_r_idx;
else
pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
- (lstate->event_r_idx - lstate->event_w_idx);
if (event_type == EVENT_TYPE_BUS_RESET
|| event_type == MSG_BUS_DEV_RESET) {
/*
* Any earlier events are irrelevant, so reset our buffer.
* This has the effect of allowing us to deal with reset
* floods (an external device holding down the reset line)
* without losing the event that is really interesting.
*/
lstate->event_r_idx = 0;
lstate->event_w_idx = 0;
xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
}
if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
xpt_print_path(lstate->path);
printf("immediate event %x:%x lost\n",
lstate->event_buffer[lstate->event_r_idx].event_type,
lstate->event_buffer[lstate->event_r_idx].event_arg);
lstate->event_r_idx++;
if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
lstate->event_r_idx = 0;
xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
}
event = &lstate->event_buffer[lstate->event_w_idx];
event->initiator_id = initiator_id;
event->event_type = event_type;
event->event_arg = event_arg;
lstate->event_w_idx++;
if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
lstate->event_w_idx = 0;
}
/*
* Send any target mode events queued up waiting
* for immediate notify resources.
*/
static void
ahc_send_lstate_events(struct ahc_softc *ahc, struct tmode_lstate *lstate)
{
struct ccb_hdr *ccbh;
struct ccb_immed_notify *inot;
while (lstate->event_r_idx != lstate->event_w_idx
&& (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
struct ahc_tmode_event *event;
event = &lstate->event_buffer[lstate->event_r_idx];
SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
inot = (struct ccb_immed_notify *)ccbh;
switch (event->event_type) {
case EVENT_TYPE_BUS_RESET:
ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
break;
default:
ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
inot->message_args[0] = event->event_type;
inot->message_args[1] = event->event_arg;
break;
}
inot->initiator_id = event->initiator_id;
inot->sense_len = 0;
xpt_done((union ccb *)inot);
lstate->event_r_idx++;
if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
lstate->event_r_idx = 0;
}
}
Reference in New Issue Copy Permalink