700 lines
20 KiB
Plaintext
700 lines
20 KiB
Plaintext
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/*
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* Device Tree Source for the SH73A0 SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/sh73a0-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,sh73a0";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <1196000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <1196000000>;
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};
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};
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gic: interrupt-controller@f0001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xf0001000 0x1000>,
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<0xf0000100 0x100>;
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};
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sbsc2: memory-controller@fb400000 {
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compatible = "renesas,sbsc-sh73a0";
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reg = <0xfb400000 0x400>;
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 38 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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};
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sbsc1: memory-controller@fe400000 {
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compatible = "renesas,sbsc-sh73a0";
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reg = <0xfe400000 0x400>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
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<0 56 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
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reg = <0xe6138000 0x200>;
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interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
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renesas,channels-mask = <0x3f>;
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clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
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clock-names = "fck";
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status = "disabled";
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};
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irqpin0: irqpin@e6900000 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900000 4>,
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<0xe6900010 4>,
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<0xe6900020 1>,
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<0xe6900040 1>,
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<0xe6900060 1>;
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interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
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0 2 IRQ_TYPE_LEVEL_HIGH
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0 3 IRQ_TYPE_LEVEL_HIGH
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0 4 IRQ_TYPE_LEVEL_HIGH
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0 5 IRQ_TYPE_LEVEL_HIGH
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0 6 IRQ_TYPE_LEVEL_HIGH
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0 7 IRQ_TYPE_LEVEL_HIGH
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0 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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irqpin1: irqpin@e6900004 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900004 4>,
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<0xe6900014 4>,
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<0xe6900024 1>,
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<0xe6900044 1>,
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<0xe6900064 1>;
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
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0 10 IRQ_TYPE_LEVEL_HIGH
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0 11 IRQ_TYPE_LEVEL_HIGH
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0 12 IRQ_TYPE_LEVEL_HIGH
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0 13 IRQ_TYPE_LEVEL_HIGH
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0 14 IRQ_TYPE_LEVEL_HIGH
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0 15 IRQ_TYPE_LEVEL_HIGH
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0 16 IRQ_TYPE_LEVEL_HIGH>;
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control-parent;
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};
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irqpin2: irqpin@e6900008 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900008 4>,
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<0xe6900018 4>,
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<0xe6900028 1>,
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<0xe6900048 1>,
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<0xe6900068 1>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
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0 18 IRQ_TYPE_LEVEL_HIGH
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0 19 IRQ_TYPE_LEVEL_HIGH
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0 20 IRQ_TYPE_LEVEL_HIGH
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0 21 IRQ_TYPE_LEVEL_HIGH
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0 22 IRQ_TYPE_LEVEL_HIGH
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0 23 IRQ_TYPE_LEVEL_HIGH
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0 24 IRQ_TYPE_LEVEL_HIGH>;
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};
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irqpin3: irqpin@e690000c {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe690000c 4>,
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<0xe690001c 4>,
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<0xe690002c 1>,
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<0xe690004c 1>,
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<0xe690006c 1>;
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interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
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0 26 IRQ_TYPE_LEVEL_HIGH
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0 27 IRQ_TYPE_LEVEL_HIGH
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0 28 IRQ_TYPE_LEVEL_HIGH
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0 29 IRQ_TYPE_LEVEL_HIGH
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0 30 IRQ_TYPE_LEVEL_HIGH
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0 31 IRQ_TYPE_LEVEL_HIGH
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0 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c0: i2c@e6820000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6820000 0x425>;
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interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
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0 168 IRQ_TYPE_LEVEL_HIGH
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0 169 IRQ_TYPE_LEVEL_HIGH
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0 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
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status = "disabled";
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};
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i2c1: i2c@e6822000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6822000 0x425>;
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interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
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0 52 IRQ_TYPE_LEVEL_HIGH
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0 53 IRQ_TYPE_LEVEL_HIGH
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0 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
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status = "disabled";
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};
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i2c2: i2c@e6824000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6824000 0x425>;
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interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
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0 172 IRQ_TYPE_LEVEL_HIGH
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0 173 IRQ_TYPE_LEVEL_HIGH
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0 174 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
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status = "disabled";
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};
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i2c3: i2c@e6826000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6826000 0x425>;
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interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
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0 184 IRQ_TYPE_LEVEL_HIGH
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0 185 IRQ_TYPE_LEVEL_HIGH
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0 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
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status = "disabled";
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};
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i2c4: i2c@e6828000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6828000 0x425>;
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interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
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0 188 IRQ_TYPE_LEVEL_HIGH
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0 189 IRQ_TYPE_LEVEL_HIGH
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0 190 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
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status = "disabled";
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};
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mmcif: mmc@e6bd0000 {
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compatible = "renesas,sh-mmcif";
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reg = <0xe6bd0000 0x100>;
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interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
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0 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
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reg-io-width = <4>;
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status = "disabled";
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};
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sdhi0: sd@ee100000 {
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compatible = "renesas,sdhi-sh73a0";
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reg = <0xee100000 0x100>;
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
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0 84 IRQ_TYPE_LEVEL_HIGH
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0 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
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cap-sd-highspeed;
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status = "disabled";
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};
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/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
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sdhi1: sd@ee120000 {
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compatible = "renesas,sdhi-sh73a0";
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reg = <0xee120000 0x100>;
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interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
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0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
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toshiba,mmc-wrprotect-disable;
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cap-sd-highspeed;
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status = "disabled";
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};
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sdhi2: sd@ee140000 {
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compatible = "renesas,sdhi-sh73a0";
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reg = <0xee140000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
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0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
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toshiba,mmc-wrprotect-disable;
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cap-sd-highspeed;
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status = "disabled";
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c40000 0x100>;
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interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c50000 0x100>;
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interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c60000 0x100>;
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interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c70000 0x100>;
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interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa4: serial@e6c80000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c80000 0x100>;
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interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa5: serial@e6cb0000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cb0000 0x100>;
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa6: serial@e6cc0000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cc0000 0x100>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa7: serial@e6cd0000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cd0000 0x100>;
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interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifb8: serial@e6c30000 {
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compatible = "renesas,scifb-sh73a0", "renesas,scifb";
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reg = <0xe6c30000 0x100>;
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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|
|
clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
|
||
|
|
clock-names = "sci_ick";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
pfc: pfc@e6050000 {
|
||
|
|
compatible = "renesas,pfc-sh73a0";
|
||
|
|
reg = <0xe6050000 0x8000>,
|
||
|
|
<0xe605801c 0x1c>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupts-extended =
|
||
|
|
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
|
||
|
|
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
|
||
|
|
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
|
||
|
|
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
|
||
|
|
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
|
||
|
|
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
|
||
|
|
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
|
||
|
|
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sh_fsi2: sound@ec230000 {
|
||
|
|
#sound-dai-cells = <1>;
|
||
|
|
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
|
||
|
|
reg = <0xec230000 0x400>;
|
||
|
|
interrupts = <0 146 0x4>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
clocks {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
/* External root clocks */
|
||
|
|
extalr_clk: extalr_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <32768>;
|
||
|
|
clock-output-names = "extalr";
|
||
|
|
};
|
||
|
|
extal1_clk: extal1_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <26000000>;
|
||
|
|
clock-output-names = "extal1";
|
||
|
|
};
|
||
|
|
extal2_clk: extal2_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "extal2";
|
||
|
|
};
|
||
|
|
extcki_clk: extcki_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "extcki";
|
||
|
|
};
|
||
|
|
fsiack_clk: fsiack_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <0>;
|
||
|
|
clock-output-names = "fsiack";
|
||
|
|
};
|
||
|
|
fsibck_clk: fsibck_clk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <0>;
|
||
|
|
clock-output-names = "fsibck";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Special CPG clocks */
|
||
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
||
|
|
compatible = "renesas,sh73a0-cpg-clocks";
|
||
|
|
reg = <0xe6150000 0x10000>;
|
||
|
|
clocks = <&extal1_clk>, <&extal2_clk>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||
|
|
"pll3", "dsi0phy", "dsi1phy",
|
||
|
|
"zg", "m3", "b", "m1", "m2",
|
||
|
|
"z", "zx", "hp";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Variable factor clocks (DIV6) */
|
||
|
|
vclk1_clk: vclk1_clk@e6150008 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150008 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "vclk1";
|
||
|
|
};
|
||
|
|
vclk2_clk: vclk2_clk@e615000c {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe615000c 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "vclk2";
|
||
|
|
};
|
||
|
|
vclk3_clk: vclk3_clk@e615001c {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe615001c 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "vclk3";
|
||
|
|
};
|
||
|
|
zb_clk: zb_clk@e6150010 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150010 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "zb";
|
||
|
|
};
|
||
|
|
flctl_clk: flctl_clk@e6150014 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150014 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "flctlck";
|
||
|
|
};
|
||
|
|
sdhi0_clk: sdhi0_clk@e6150074 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150074 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "sdhi0ck";
|
||
|
|
};
|
||
|
|
sdhi1_clk: sdhi1_clk@e6150078 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150078 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "sdhi1ck";
|
||
|
|
};
|
||
|
|
sdhi2_clk: sdhi2_clk@e615007c {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe615007c 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "sdhi2ck";
|
||
|
|
};
|
||
|
|
fsia_clk: fsia_clk@e6150018 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150018 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "fsia";
|
||
|
|
};
|
||
|
|
fsib_clk: fsib_clk@e6150090 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150090 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "fsib";
|
||
|
|
};
|
||
|
|
sub_clk: sub_clk@e6150080 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150080 4>;
|
||
|
|
clocks = <&extal2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "sub";
|
||
|
|
};
|
||
|
|
spua_clk: spua_clk@e6150084 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150084 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "spua";
|
||
|
|
};
|
||
|
|
spuv_clk: spuv_clk@e6150094 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150094 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "spuv";
|
||
|
|
};
|
||
|
|
msu_clk: msu_clk@e6150088 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150088 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "msu";
|
||
|
|
};
|
||
|
|
hsi_clk: hsi_clk@e615008c {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe615008c 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "hsi";
|
||
|
|
};
|
||
|
|
mfg1_clk: mfg1_clk@e6150098 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150098 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "mfg1";
|
||
|
|
};
|
||
|
|
mfg2_clk: mfg2_clk@e615009c {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe615009c 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "mfg2";
|
||
|
|
};
|
||
|
|
dsit_clk: dsit_clk@e6150060 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150060 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "dsit";
|
||
|
|
};
|
||
|
|
dsi0p_clk: dsi0p_clk@e6150064 {
|
||
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
||
|
|
reg = <0xe6150064 4>;
|
||
|
|
clocks = <&pll1_div2_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "dsi0pck";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Fixed factor clocks */
|
||
|
|
main_div2_clk: main_div2_clk {
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-div = <2>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
clock-output-names = "main_div2";
|
||
|
|
};
|
||
|
|
pll1_div2_clk: pll1_div2_clk {
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-div = <2>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
clock-output-names = "pll1_div2";
|
||
|
|
};
|
||
|
|
pll1_div7_clk: pll1_div7_clk {
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-div = <7>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
clock-output-names = "pll1_div7";
|
||
|
|
};
|
||
|
|
pll1_div13_clk: pll1_div13_clk {
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-div = <13>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
clock-output-names = "pll1_div13";
|
||
|
|
};
|
||
|
|
twd_clk: twd_clk {
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_Z>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-div = <4>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
clock-output-names = "twd";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Gate clocks */
|
||
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
||
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||
|
|
reg = <0xe6150130 4>, <0xe6150030 4>;
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_HP>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-indices = <
|
||
|
|
SH73A0_CLK_IIC2
|
||
|
|
>;
|
||
|
|
clock-output-names =
|
||
|
|
"iic2";
|
||
|
|
};
|
||
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
||
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||
|
|
reg = <0xe6150134 4>, <0xe6150038 4>;
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_B>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_B>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_B>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_B>,
|
||
|
|
<&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_ZG>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_B>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-indices = <
|
||
|
|
SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
|
||
|
|
SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
|
||
|
|
SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
|
||
|
|
SH73A0_CLK_IIC0 SH73A0_CLK_SGX
|
||
|
|
SH73A0_CLK_LCDC0
|
||
|
|
>;
|
||
|
|
clock-output-names =
|
||
|
|
"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
|
||
|
|
"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
|
||
|
|
};
|
||
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
||
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||
|
|
reg = <0xe6150138 4>, <0xe6150040 4>;
|
||
|
|
clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
|
||
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
|
||
|
|
<&sub_clk>, <&sub_clk>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-indices = <
|
||
|
|
SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
|
||
|
|
SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
|
||
|
|
SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
|
||
|
|
SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
|
||
|
|
SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
|
||
|
|
>;
|
||
|
|
clock-output-names =
|
||
|
|
"scifa7", "sy_dmac", "mp_dmac", "scifa5",
|
||
|
|
"scifb", "scifa0", "scifa1", "scifa2",
|
||
|
|
"scifa3", "scifa4";
|
||
|
|
};
|
||
|
|
mstp3_clks: mstp3_clks@e615013c {
|
||
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||
|
|
reg = <0xe615013c 4>, <0xe6150048 4>;
|
||
|
|
clocks = <&sub_clk>, <&extalr_clk>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
|
||
|
|
<&sdhi0_clk>, <&sdhi1_clk>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
|
||
|
|
<&main_div2_clk>, <&main_div2_clk>,
|
||
|
|
<&main_div2_clk>, <&main_div2_clk>,
|
||
|
|
<&main_div2_clk>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-indices = <
|
||
|
|
SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
|
||
|
|
SH73A0_CLK_FSI SH73A0_CLK_IRDA
|
||
|
|
SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
|
||
|
|
SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
|
||
|
|
SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
|
||
|
|
SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
|
||
|
|
SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
|
||
|
|
SH73A0_CLK_TPU4
|
||
|
|
>;
|
||
|
|
clock-output-names =
|
||
|
|
"scifa6", "cmt1", "fsi", "irda", "iic1",
|
||
|
|
"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
|
||
|
|
"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
|
||
|
|
};
|
||
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
||
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||
|
|
reg = <0xe6150140 4>, <0xe615004c 4>;
|
||
|
|
clocks = <&cpg_clocks SH73A0_CLK_HP>,
|
||
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
clock-indices = <
|
||
|
|
SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
|
||
|
|
SH73A0_CLK_KEYSC
|
||
|
|
>;
|
||
|
|
clock-output-names =
|
||
|
|
"iic3", "iic4", "keysc";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|