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freebsd-dev/sys/i386/isa/atpic.c

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Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/*-
* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_auto_eoi.h"
#include "opt_isa.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/interrupt.h>
#include <sys/kernel.h>
#include <sys/lock.h>
Add some missing <sys/module.h> includes which are masked by the one on death-row in <sys/kernel.h>
2004-05-30 17:57:46 +00:00
#include <sys/module.h>
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#include <sys/mutex.h>
#include <machine/cpufunc.h>
#include <machine/frame.h>
#include <machine/intr_machdep.h>
#include <machine/md_var.h>
#include <machine/resource.h>
#include <machine/segments.h>
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#include <dev/ic/i8259.h>
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#include <i386/isa/icu.h>
Fix to support pc98.
2003-11-04 13:13:04 +00:00
#ifdef PC98
Change a directory layout for pc98. - Move MD files into <arch>/<arch>. - Move bus dependent files into <arch>/<bus>. Rename some files to more suitable names. Repo-copied by: peter Discussed with: imp
2005-05-10 12:02:18 +00:00
#include <pc98/cbus/cbus.h>
Fix to support pc98.
2003-11-04 13:13:04 +00:00
#else
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#include <i386/isa/isa.h>
Fix to support pc98.
2003-11-04 13:13:04 +00:00
#endif
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#include <isa/isavar.h>
#define MASTER 0
#define SLAVE 1
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
/*
* PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
* PC-AT machines wire the slave PIC to pin 2 on the master PIC.
*/
#ifdef PC98
#define ICU_SLAVEID 7
#else
#define ICU_SLAVEID 2
#endif
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
/*
* Determine the base master and slave modes not including auto EOI support.
* All machines that FreeBSD supports use 8086 mode.
*/
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#ifdef PC98
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
/*
* PC-98 machines do not support auto EOI on the second PIC. Also, it
* seems that PC-98 machine PICs use buffered mode, and the master PIC
* uses special fully nested mode.
*/
#define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
#define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#else
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#define BASE_MASTER_MODE ICW4_8086
#define BASE_SLAVE_MODE ICW4_8086
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
/* Enable automatic EOI if requested. */
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#ifdef AUTO_EOI_1
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#else
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#define MASTER_MODE BASE_MASTER_MODE
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif
#ifdef AUTO_EOI_2
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#else
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#define SLAVE_MODE BASE_SLAVE_MODE
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
#define IRQ_MASK(irq) (1 << (irq))
#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
#define NUM_ISA_IRQS 16
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void atpic_init(void *dummy);
unsigned int imen; /* XXX */
inthand_t
IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
IDTVEC(atpic_intr15);
#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
#define ATPIC(io, base, eoi, imenptr) \
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
{ { atpic_enable_source, atpic_disable_source, (eoi), \
atpic_enable_intr, atpic_vector, atpic_source_pending, NULL, \
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
atpic_resume, atpic_config_intr }, (io), (base), \
IDT_IO_INTS + (base), (imenptr) }
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#define INTSRC(irq) \
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
{ { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
(irq) % 8 }
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
struct atpic {
struct pic at_pic;
int at_ioaddr;
int at_irqbase;
uint8_t at_intbase;
uint8_t *at_imen;
};
struct atpic_intsrc {
struct intsrc at_intsrc;
inthand_t *at_intr;
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
int at_irq; /* Relative to PIC base. */
enum intr_trigger at_trigger;
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
u_long at_count;
u_long at_straycount;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
};
static void atpic_enable_source(struct intsrc *isrc);
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
static void atpic_disable_source(struct intsrc *isrc, int eoi);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void atpic_eoi_master(struct intsrc *isrc);
static void atpic_eoi_slave(struct intsrc *isrc);
static void atpic_enable_intr(struct intsrc *isrc);
static int atpic_vector(struct intsrc *isrc);
static void atpic_resume(struct intsrc *isrc);
static int atpic_source_pending(struct intsrc *isrc);
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
enum intr_polarity pol);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void i8259_init(struct atpic *pic, int slave);
static struct atpic atpics[] = {
ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
};
static struct atpic_intsrc atintrs[] = {
INTSRC(0),
INTSRC(1),
INTSRC(2),
INTSRC(3),
INTSRC(4),
INTSRC(5),
INTSRC(6),
INTSRC(7),
INTSRC(8),
INTSRC(9),
INTSRC(10),
INTSRC(11),
INTSRC(12),
INTSRC(13),
INTSRC(14),
INTSRC(15),
};
- Simplify the sizeof expression in the CTASSERT() for NUM_ISA_IRQS. - Fixup grammar in a comment. Submitted by: bde (1)
2004-05-10 18:33:52 +00:00
CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
static __inline void
_atpic_eoi_master(struct intsrc *isrc)
{
KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
("%s: mismatched pic", __func__));
#ifndef AUTO_EOI_1
outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
#endif
}
/*
* The data sheet says no auto-EOI on slave, but it sometimes works.
* So, if AUTO_EOI_2 is enabled, we use it.
*/
static __inline void
_atpic_eoi_slave(struct intsrc *isrc)
{
KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
("%s: mismatched pic", __func__));
#ifndef AUTO_EOI_2
outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
#ifndef AUTO_EOI_1
outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
#endif
#endif
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void
atpic_enable_source(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
mtx_lock_spin(&icu_lock);
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
if (*ap->at_imen & IMEN_MASK(ai)) {
*ap->at_imen &= ~IMEN_MASK(ai);
outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
mtx_unlock_spin(&icu_lock);
}
static void
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
atpic_disable_source(struct intsrc *isrc, int eoi)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
mtx_lock_spin(&icu_lock);
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
if (ai->at_trigger != INTR_TRIGGER_EDGE) {
*ap->at_imen |= IMEN_MASK(ai);
outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
}
/*
* Take care to call these functions directly instead of through
* a function pointer. All of the referenced variables should
* still be hot in the cache.
*/
if (eoi == PIC_EOI) {
if (isrc->is_pic == &atpics[MASTER].at_pic)
_atpic_eoi_master(isrc);
else
_atpic_eoi_slave(isrc);
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
mtx_unlock_spin(&icu_lock);
}
static void
atpic_eoi_master(struct intsrc *isrc)
{
#ifndef AUTO_EOI_1
mtx_lock_spin(&icu_lock);
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
_atpic_eoi_master(isrc);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
mtx_unlock_spin(&icu_lock);
#endif
}
static void
atpic_eoi_slave(struct intsrc *isrc)
{
#ifndef AUTO_EOI_2
mtx_lock_spin(&icu_lock);
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
_atpic_eoi_slave(isrc);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
mtx_unlock_spin(&icu_lock);
#endif
}
static void
atpic_enable_intr(struct intsrc *isrc)
{
}
static int
atpic_vector(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
return (IRQ(ap, ai));
}
static int
atpic_source_pending(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
static void
atpic_resume(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
if (ai->at_irq == 0) {
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
i8259_init(ap, ap == &atpics[SLAVE]);
Fixed PC98 support. - Disable an ELCR on PC98. - Correct IRQs.
2004-05-06 13:48:34 +00:00
#ifndef PC98
Tweak the ELCR support slightly. Explicitly probe the ELCR during boot instead of burying that in the atpic(4) code as atpic(4) is not the only user of elcr(4). Change the elcr(4) code to export a global elcr_found variable that other code can check to see if a valid ELCR was found. MFC after: 1 month
2005-01-18 20:24:47 +00:00
if (ap == &atpics[SLAVE] && elcr_found)
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
elcr_resume();
Fixed PC98 support. - Disable an ELCR on PC98. - Correct IRQs.
2004-05-06 13:48:34 +00:00
#endif
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
static int
atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
enum intr_polarity pol)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
u_int vector;
/* Map conforming values to edge/hi and sanity check the values. */
if (trig == INTR_TRIGGER_CONFORM)
trig = INTR_TRIGGER_EDGE;
if (pol == INTR_POLARITY_CONFORM)
pol = INTR_POLARITY_HIGH;
vector = atpic_vector(isrc);
if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
(trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
printf(
"atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
pol == INTR_POLARITY_HIGH ? "high" : "low");
return (EINVAL);
}
/* If there is no change, just return. */
if (ai->at_trigger == trig)
return (0);
Fixed PC98 support. - Disable an ELCR on PC98. - Correct IRQs.
2004-05-06 13:48:34 +00:00
#ifdef PC98
if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
trig == INTR_TRIGGER_LEVEL) {
if (bootverbose)
printf(
"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
vector);
return (EINVAL);
}
return (ENXIO);
#else
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
/*
* Certain IRQs can never be level/lo, so don't try to set them
* that way if asked. At least some ELCR registers ignore setting
* these bits as well.
*/
if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
trig == INTR_TRIGGER_LEVEL) {
if (bootverbose)
printf(
"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
vector);
return (EINVAL);
}
Tweak the ELCR support slightly. Explicitly probe the ELCR during boot instead of burying that in the atpic(4) code as atpic(4) is not the only user of elcr(4). Change the elcr(4) code to export a global elcr_found variable that other code can check to see if a valid ELCR was found. MFC after: 1 month
2005-01-18 20:24:47 +00:00
if (!elcr_found) {
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
if (bootverbose)
printf("atpic: No ELCR to configure IRQ%u as %s\n",
vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
"level/low");
return (ENXIO);
}
if (bootverbose)
printf("atpic: Programming IRQ%u as %s\n", vector,
trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
mtx_lock_spin(&icu_lock);
elcr_write_trigger(atpic_vector(isrc), trig);
ai->at_trigger = trig;
mtx_unlock_spin(&icu_lock);
return (0);
Fixed PC98 support. - Disable an ELCR on PC98. - Correct IRQs.
2004-05-06 13:48:34 +00:00
#endif /* PC98 */
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void
i8259_init(struct atpic *pic, int slave)
{
int imr_addr;
/* Reset the PIC and program with next four bytes. */
mtx_lock_spin(&icu_lock);
#ifdef DEV_MCA
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
/* MCA uses level triggered interrupts. */
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
if (MCA_system)
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
else
#endif
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
/* Start vector. */
outb(imr_addr, pic->at_intbase);
/*
* Setup slave links. For the master pic, indicate what line
* the slave is configured on. For the slave indicate
* which line on the master we are connected to.
*/
if (slave)
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
outb(imr_addr, ICU_SLAVEID);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
else
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/* Set mode. */
if (slave)
outb(imr_addr, SLAVE_MODE);
else
outb(imr_addr, MASTER_MODE);
/* Set interrupt enable mask. */
outb(imr_addr, *pic->at_imen);
/* Reset is finished, default to IRR on read. */
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#ifndef PC98
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
/* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
if (!slave)
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif
mtx_unlock_spin(&icu_lock);
}
void
atpic_startup(void)
{
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
struct atpic_intsrc *ai;
int i;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/* Start off with all interrupts disabled. */
imen = 0xffff;
i8259_init(&atpics[MASTER], 0);
i8259_init(&atpics[SLAVE], 1);
atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
/* Install low-level interrupt handlers for all of our IRQs. */
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
if (i == ICU_SLAVEID)
continue;
ai->at_intsrc.is_count = &ai->at_count;
ai->at_intsrc.is_straycount = &ai->at_straycount;
setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
ai->at_irq, ai->at_intr, SDT_SYS386IGT, SEL_KPL,
GSEL(GCODE_SEL, SEL_KPL));
}
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
#ifdef DEV_MCA
/* For MCA systems, all interrupts are level triggered. */
if (MCA_system)
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
ai->at_trigger = INTR_TRIGGER_LEVEL;
else
#endif
Fixed PC98 support. - Disable an ELCR on PC98. - Correct IRQs.
2004-05-06 13:48:34 +00:00
#ifdef PC98
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
switch (i) {
case 0:
case 1:
case 7:
case 8:
ai->at_trigger = INTR_TRIGGER_EDGE;
break;
default:
ai->at_trigger = INTR_TRIGGER_LEVEL;
break;
}
#else
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
/*
* Look for an ELCR. If we find one, update the trigger modes.
* If we don't find one, assume that IRQs 0, 1, 2, and 13 are
* edge triggered and that everything else is level triggered.
* We only use the trigger information to reprogram the ELCR if
* we have one and as an optimization to avoid masking edge
* triggered interrupts. For the case that we don't have an ELCR,
* it doesn't hurt to mask an edge triggered interrupt, so we
- Simplify the sizeof expression in the CTASSERT() for NUM_ISA_IRQS. - Fixup grammar in a comment. Submitted by: bde (1)
2004-05-10 18:33:52 +00:00
* assume level trigger for any interrupt that we aren't sure is
* edge triggered.
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
*/
Tweak the ELCR support slightly. Explicitly probe the ELCR during boot instead of burying that in the atpic(4) code as atpic(4) is not the only user of elcr(4). Change the elcr(4) code to export a global elcr_found variable that other code can check to see if a valid ELCR was found. MFC after: 1 month
2005-01-18 20:24:47 +00:00
if (elcr_found) {
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
ai->at_trigger = elcr_read_trigger(i);
} else {
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
switch (i) {
case 0:
case 1:
case 2:
case 8:
case 13:
ai->at_trigger = INTR_TRIGGER_EDGE;
break;
default:
ai->at_trigger = INTR_TRIGGER_LEVEL;
break;
}
}
Fixed PC98 support. - Disable an ELCR on PC98. - Correct IRQs.
2004-05-06 13:48:34 +00:00
#endif /* PC98 */
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
static void
atpic_init(void *dummy __unused)
{
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
struct atpic_intsrc *ai;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
int i;
/* Loop through all interrupt sources and add them. */
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
if (i == ICU_SLAVEID)
continue;
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
intr_register_source(&ai->at_intsrc);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
}
SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL)
void
- Move manipulation of td_intr_nesting_level out of assembly interrupt vector stubs and into the C functions they call. - Move disabling and EOIing of interrupt sources out of PIC driver entry points and into intr_execute_handlers(). Intr_execute_handlers() only disables a source for an interrupt if it is a stray interrupt or has threaded handlers. Sources with fast handlers no longer disable (mask) the source while executing the handlers. - Move the setting of clkintr_pending into intr_execute_handlers() and set the variable for any interrupt source with a vector of 0. (Should only be true for IRQ 0.) This fixes clkintr_pending in the NO_MIXED_MODE case. - Implement lapic_eoi() and use it to implement ioapic_eoi_source(). - Rename atpic_sched_ithd() to atpic_handle_intr() since it is used to handle all atpic interrupts and not just threaded ones. Inspired by: peter's changes to amd64 in p4 (1) Requested by: bde (2)
2003-11-12 18:13:57 +00:00
atpic_handle_intr(struct intrframe iframe)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
{
struct intsrc *isrc;
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
KASSERT((u_int)iframe.if_vec < NUM_ISA_IRQS,
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
("unknown int %d\n", iframe.if_vec));
isrc = &atintrs[iframe.if_vec].at_intsrc;
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
/*
Reorganize the interrupt handling code a bit to make a few things cleaner and increase flexibility to allow various different approaches to be tried in the future. - Split struct ithd up into two pieces. struct intr_event holds the list of interrupt handlers associated with interrupt sources. struct intr_thread contains the data relative to an interrupt thread. Currently we still provide a 1:1 relationship of events to threads with the exception that events only have an associated thread if there is at least one threaded interrupt handler attached to the event. This means that on x86 we no longer have 4 bazillion interrupt threads with no handlers. It also means that interrupt events with only INTR_FAST handlers no longer have an associated thread either. - Renamed struct intrhand to struct intr_handler to follow the struct intr_foo naming convention. This did require renaming the powerpc MD struct intr_handler to struct ppc_intr_handler. - INTR_FAST no longer implies INTR_EXCL on all architectures except for powerpc. This means that multiple INTR_FAST handlers can attach to the same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach to the same interrupt. Sharing INTR_FAST handlers may not always be desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun either. Drivers can always still use INTR_EXCL to ask for an interrupt exclusively. The way this sharing works is that when an interrupt comes in, all the INTR_FAST handlers are executed first, and if any threaded handlers exist, the interrupt thread is scheduled afterwards. This type of layout also makes it possible to investigate using interrupt filters ala OS X where the filter determines whether or not its companion threaded handler should run. - Aside from the INTR_FAST changes above, the impact on MD interrupt code is mostly just 's/ithread/intr_event/'. - A new MI ddb command 'show intrs' walks the list of interrupt events dumping their state. It also has a '/v' verbose switch which dumps info about all of the handlers attached to each event. - We currently don't destroy an interrupt thread when the last threaded handler is removed because it would suck for things like ppbus(8)'s braindead behavior. The code is present, though, it is just under #if 0 for now. - Move the code to actually execute the threaded handlers for an interrrupt event into a separate function so that ithread_loop() becomes more readable. Previously this code was all in the middle of ithread_loop() and indented halfway across the screen. - Made struct intr_thread private to kern_intr.c and replaced td_ithd with a thread private flag TDP_ITHREAD. - In statclock, check curthread against idlethread directly rather than curthread's proc against idlethread's proc. (Not really related to intr changes) Tested on: alpha, amd64, i386, sparc64 Tested on: arm, ia64 (older version of patch by cognet and marcel)
2005-10-25 19:48:48 +00:00
* If we don't have an event, see if this is a spurious
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
* interrupt.
*/
Reorganize the interrupt handling code a bit to make a few things cleaner and increase flexibility to allow various different approaches to be tried in the future. - Split struct ithd up into two pieces. struct intr_event holds the list of interrupt handlers associated with interrupt sources. struct intr_thread contains the data relative to an interrupt thread. Currently we still provide a 1:1 relationship of events to threads with the exception that events only have an associated thread if there is at least one threaded interrupt handler attached to the event. This means that on x86 we no longer have 4 bazillion interrupt threads with no handlers. It also means that interrupt events with only INTR_FAST handlers no longer have an associated thread either. - Renamed struct intrhand to struct intr_handler to follow the struct intr_foo naming convention. This did require renaming the powerpc MD struct intr_handler to struct ppc_intr_handler. - INTR_FAST no longer implies INTR_EXCL on all architectures except for powerpc. This means that multiple INTR_FAST handlers can attach to the same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach to the same interrupt. Sharing INTR_FAST handlers may not always be desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun either. Drivers can always still use INTR_EXCL to ask for an interrupt exclusively. The way this sharing works is that when an interrupt comes in, all the INTR_FAST handlers are executed first, and if any threaded handlers exist, the interrupt thread is scheduled afterwards. This type of layout also makes it possible to investigate using interrupt filters ala OS X where the filter determines whether or not its companion threaded handler should run. - Aside from the INTR_FAST changes above, the impact on MD interrupt code is mostly just 's/ithread/intr_event/'. - A new MI ddb command 'show intrs' walks the list of interrupt events dumping their state. It also has a '/v' verbose switch which dumps info about all of the handlers attached to each event. - We currently don't destroy an interrupt thread when the last threaded handler is removed because it would suck for things like ppbus(8)'s braindead behavior. The code is present, though, it is just under #if 0 for now. - Move the code to actually execute the threaded handlers for an interrrupt event into a separate function so that ithread_loop() becomes more readable. Previously this code was all in the middle of ithread_loop() and indented halfway across the screen. - Made struct intr_thread private to kern_intr.c and replaced td_ithd with a thread private flag TDP_ITHREAD. - In statclock, check curthread against idlethread directly rather than curthread's proc against idlethread's proc. (Not really related to intr changes) Tested on: alpha, amd64, i386, sparc64 Tested on: arm, ia64 (older version of patch by cognet and marcel)
2005-10-25 19:48:48 +00:00
if (isrc->is_event == NULL &&
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
(iframe.if_vec == 7 || iframe.if_vec == 15)) {
int port, isr;
/*
* Read the ISR register to see if IRQ 7/15 is really
* pending. Reset read register back to IRR when done.
*/
port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
mtx_lock_spin(&icu_lock);
outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
isr = inb(port);
outb(port, OCW3_SEL | OCW3_RR);
mtx_unlock_spin(&icu_lock);
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
if ((isr & IRQ_MASK(7)) == 0)
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
return;
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
intr_execute_handlers(isrc, &iframe);
}
#ifdef DEV_ISA
/*
* Bus attachment for the ISA PIC.
*/
static struct isa_pnp_id atpic_ids[] = {
{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
{ 0 }
};
static int
atpic_probe(device_t dev)
{
int result;
result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
if (result <= 0)
device_quiet(dev);
return (result);
}
/*
* We might be granted IRQ 2, as this is typically consumed by chaining
* between the two PIC components. If we're using the APIC, however,
* this may not be the case, and as such we should free the resource.
* (XXX untested)
*
* The generic ISA attachment code will handle allocating any other resources
* that we don't explicitly claim here.
*/
static int
atpic_attach(device_t dev)
{
struct resource *res;
int rid;
/* Try to allocate our IRQ and then free it. */
rid = 0;
Convert callers to the new bus_alloc_resource_any(9) API. Submitted by: Mark Santcroos <marks@ripe.net> Reviewed by: imp, dfr, bde
2004-03-17 17:50:55 +00:00
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
if (res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
return (0);
}
static device_method_t atpic_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, atpic_probe),
DEVMETHOD(device_attach, atpic_attach),
DEVMETHOD(device_detach, bus_generic_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
{ 0, 0 }
};
static driver_t atpic_driver = {
"atpic",
atpic_methods,
1, /* no softc */
};
static devclass_t atpic_devclass;
DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
Fix to support pc98.
2003-11-04 13:13:04 +00:00
#ifndef PC98
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
Fix to support pc98.
2003-11-04 13:13:04 +00:00
#endif
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/*
* Return a bitmap of the current interrupt requests. This is 8259-specific
* and is only suitable for use at probe time.
*/
intrmask_t
isa_irq_pending(void)
{
u_char irr1;
u_char irr2;
irr1 = inb(IO_ICU1);
irr2 = inb(IO_ICU2);
return ((irr2 << 8) | irr1);
}
#endif /* DEV_ISA */
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