2005-01-06 22:18:23 +00:00
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/*-
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2017-11-20 19:43:44 +00:00
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* SPDX-License-Identifier: BSD-3-Clause
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*
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1993-06-12 14:58:17 +00:00
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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2017-02-28 23:42:47 +00:00
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* 3. Neither the name of the University nor the names of its contributors
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1993-06-12 14:58:17 +00:00
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*
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1993-10-15 10:07:45 +00:00
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* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
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* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
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1999-08-28 01:08:13 +00:00
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* $FreeBSD$
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1993-06-12 14:58:17 +00:00
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*/
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1994-11-14 14:12:24 +00:00
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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1993-06-12 14:58:17 +00:00
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1996-05-02 22:25:18 +00:00
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/*
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2005-12-06 21:09:01 +00:00
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* Page-directory and page-table entries follow this format, with a few
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1996-05-02 22:25:18 +00:00
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* of the fields not present here and there, depending on a lot of things.
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*/
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/* ---- Intel Nomenclature ---- */
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#define PG_V 0x001 /* P Valid */
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#define PG_RW 0x002 /* R/W Read/Write */
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#define PG_U 0x004 /* U/S User/Supervisor */
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#define PG_NC_PWT 0x008 /* PWT Write through */
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#define PG_NC_PCD 0x010 /* PCD Cache disable */
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#define PG_A 0x020 /* A Accessed */
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#define PG_M 0x040 /* D Dirty */
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#define PG_PS 0x080 /* PS Page size (0=4k,1=4M) */
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2006-05-01 22:07:00 +00:00
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#define PG_PTE_PAT 0x080 /* PAT PAT index */
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1996-05-02 22:25:18 +00:00
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#define PG_G 0x100 /* G Global */
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#define PG_AVAIL1 0x200 /* / Available for system */
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#define PG_AVAIL2 0x400 /* < programmers use */
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#define PG_AVAIL3 0x800 /* \ */
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2006-05-01 22:07:00 +00:00
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#define PG_PDE_PAT 0x1000 /* PAT PAT index */
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2007-04-06 18:15:03 +00:00
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#define PG_NX (1ull<<63) /* No-execute */
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1996-05-02 22:25:18 +00:00
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/* Our various interpretations of the above */
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#define PG_W PG_AVAIL1 /* "Wired" pseudoflag */
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1996-05-18 03:38:05 +00:00
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#define PG_MANAGED PG_AVAIL2
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2017-02-26 19:54:02 +00:00
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#define PG_PROMOTED PG_AVAIL3 /* PDE only */
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i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
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1996-05-02 22:25:18 +00:00
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#define PG_PROT (PG_RW|PG_U) /* all protection bits . */
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#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */
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1993-06-12 14:58:17 +00:00
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2009-08-31 17:42:52 +00:00
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/* Page level cache control fields used to determine the PAT type */
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#define PG_PDE_CACHE (PG_PDE_PAT | PG_NC_PWT | PG_NC_PCD)
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#define PG_PTE_CACHE (PG_PTE_PAT | PG_NC_PWT | PG_NC_PCD)
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MFamd64 with few changes:
1. Add support for automatic promotion of 4KB page mappings to 2MB page
mappings. Automatic promotion can be enabled by setting the tunable
"vm.pmap.pg_ps_enabled" to a non-zero value. By default, automatic
promotion is disabled. Tested by: kris
2. To date, we have assumed that the TLB will only set the PG_M bit in a
PTE if that PTE has the PG_RW bit set. However, this assumption does
not hold on recent processors from Intel. For example, consider a PTE
that has the PG_RW bit set but the PG_M bit clear. Suppose this PTE
is cached in the TLB and later the PG_RW bit is cleared in the PTE,
but the corresponding TLB entry is not (yet) invalidated.
Historically, upon a write access using this (stale) TLB entry, the
TLB would observe that the PG_RW bit had been cleared and initiate a
page fault, aborting the setting of the PG_M bit in the PTE. Now,
however, P4- and Core2-family processors will set the PG_M bit before
observing that the PG_RW bit is clear and initiating a page fault. In
other words, the write does not occur but the PG_M bit is still set.
The real impact of this difference is not that great. Specifically,
we should no longer assert that any PTE with the PG_M bit set must
also have the PG_RW bit set, and we should ignore the state of the
PG_M bit unless the PG_RW bit is set.
2008-03-27 04:34:17 +00:00
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/*
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* Promotion to a 2 or 4MB (PDE) page mapping requires that the corresponding
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* 4KB (PTE) page mappings have identical settings for the following fields:
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*/
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#define PG_PTE_PROMOTE (PG_MANAGED | PG_W | PG_G | PG_PTE_PAT | \
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PG_M | PG_A | PG_NC_PCD | PG_NC_PWT | PG_U | PG_RW | PG_V)
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1996-05-02 14:21:14 +00:00
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/*
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* Page Protection Exception bits
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*/
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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2007-04-12 17:00:56 +00:00
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#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
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2007-04-06 18:15:03 +00:00
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#define PGEX_I 0x10 /* during an instruction fetch */
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1996-05-02 14:21:14 +00:00
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/*
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* Pte related macros
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*/
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#define VADDR(pdi, pti) ((vm_offset_t)(((pdi)<<PDRSHIFT)|((pti)<<PAGE_SHIFT)))
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1993-06-12 14:58:17 +00:00
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1994-01-14 16:25:31 +00:00
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#ifndef NKPDE
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2003-04-07 14:27:19 +00:00
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#define NKPDE (KVA_PAGES) /* number of page tables/pde's */
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2001-09-21 06:23:03 +00:00
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#endif
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1994-01-14 16:25:31 +00:00
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i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
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#define PDRSHIFT_PAE 21 /* LOG2(NBPDR) */
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#define PG_FRAME_PAE (0x000ffffffffff000ull)
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#define PG_PS_FRAME_PAE (0x000fffffffe00000ull)
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#define PDRSHIFT_NOPAE 22
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#define PG_FRAME_NOPAE (~PAGE_MASK)
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#define PG_PS_FRAME_NOPAE (0xffc00000)
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1993-10-12 13:58:01 +00:00
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/*
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* The *PTDI values control the layout of virtual memory
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*/
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i386 4/4G split.
The change makes the user and kernel address spaces on i386
independent, giving each almost the full 4G of usable virtual addresses
except for one PDE at top used for trampoline and per-CPU trampoline
stacks, and system structures that must be always mapped, namely IDT,
GDT, common TSS and LDT, and process-private TSS and LDT if allocated.
By using 1:1 mapping for the kernel text and data, it appeared
possible to eliminate assembler part of the locore.S which bootstraps
initial page table and KPTmap. The code is rewritten in C and moved
into the pmap_cold(). The comment in vmparam.h explains the KVA
layout.
There is no PCID mechanism available in protected mode, so each
kernel/user switch forth and back completely flushes the TLB, except
for the trampoline PTD region. The TLB invalidations for userspace
becomes trivial, because IPI handlers switch page tables. On the other
hand, context switches no longer need to reload %cr3.
copyout(9) was rewritten to use vm_fault_quick_hold(). An issue for
new copyout(9) is compatibility with wiring user buffers around sysctl
handlers. This explains two kind of locks for copyout ptes and
accounting of the vslock() calls. The vm_fault_quick_hold() AKA slow
path, is only tried after the 'fast path' failed, which temporary
changes mapping to the userspace and copies the data to/from small
per-cpu buffer in the trampoline. If a page fault occurs during the
copy, it is short-circuit by exception.s to not even reach C code.
The change was motivated by the need to implement the Meltdown
mitigation, but instead of KPTI the full split is done. The i386
architecture already shows the sizing problems, in particular, it is
impossible to link clang and lld with debugging. I expect that the
issues due to the virtual address space limits would only exaggerate
and the split gives more liveness to the platform.
Tested by: pho
Discussed with: bde
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
Differential revision: https://reviews.freebsd.org/D14633
2018-04-13 20:30:49 +00:00
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#define KPTDI 0 /* start of kernel virtual pde's */
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i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
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/* ptd entry that points to ptd */
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#define PTDPTDI (NPDEPTD - NTRPPTD - NPGPTD)
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#define TRPTDI (NPDEPTD - NTRPPTD) /* u/k trampoline ptd */
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First steps in rewriting locore.s, and making info useful
when the machine panics.
i386/i386/locore.s:
1) got rid of most .set directives that were being used like
#define's, and replaced them with appropriate #define's in
the appropriate header files (accessed via genassym).
2) added comments to header inclusions and global definitions,
and global variables
3) replaced some hardcoded constants with cpp defines (such as
PDESIZE and others)
4) aligned all comments to the same column to make them easier to
read
5) moved macro definitions for ENTRY, ALIGN, NOP, etc. to
/sys/i386/include/asmacros.h
6) added #ifdef BDE_DEBUGGER around all of Bruce's debugger code
7) added new global '_KERNend' to store last location+1 of kernel
8) cleaned up zeroing of bss so that only bss is zeroed
9) fix zeroing of page tables so that it really does zero them all
- not just if they follow the bss.
10) rewrote page table initialization code so that 1) works correctly
and 2) write protects the kernel text by default
11) properly initialize the kernel page directory, upages, p0stack PT,
and page tables. The previous scheme was more than a bit
screwy.
12) change allocation of virtual area of IO hole so that it is
fixed at KERNBASE + 0xa0000. The previous scheme put it
right after the kernel page tables and then later expected
it to be at KERNBASE +0xa0000
13) change multiple bogus settings of user read/write of various
areas of kernel VM - including the IO hole; we should never
be accessing the IO hole in user mode through the kernel
page tables
14) split kernel support routines such as bcopy, bzero, copyin,
copyout, etc. into a seperate file 'support.s'
15) split swtch and related routines into a seperate 'swtch.s'
16) split routines related to traps, syscalls, and interrupts
into a seperate file 'exception.s'
17) remove some unused global variables from locore that got
inserted by Garrett when he pulled them out of some .h
files.
i386/isa/icu.s:
1) clean up global variable declarations
2) move in declaration of astpending and netisr
i386/i386/pmap.c:
1) fix calculation of virtual_avail. It previously was calculated
to be right in the middle of the kernel page tables - not
a good place to start allocating kernel VM.
2) properly allocate kernel page dir/tables etc out of kernel map
- previously only took out 2 pages.
i386/i386/machdep.c:
1) modify boot() to print a warning that the system will reboot in
PANIC_REBOOT_WAIT_TIME amount of seconds, and let the user
abort with a key on the console. The machine will wait for
ever if a key is typed before the reboot. The default is
15 seconds, but can be set to 0 to mean don't wait at all,
-1 to mean wait forever, or any positive value to wait for
that many seconds.
2) print "Rebooting..." just before doing it.
kern/subr_prf.c:
1) remove PANICWAIT as it is deprecated by the change to machdep.c
i386/i386/trap.c:
1) add table of trap type strings and use it to print a real trap/
panic message rather than just a number. Lot's of work to
be done here, but this is the first step. Symbolic traceback
is in the TODO.
i386/i386/Makefile.i386:
1) add support in to build support.s, exception.s and swtch.s
...and various changes to various header files to make all of the
above happen.
1993-11-13 02:25:21 +00:00
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1996-05-02 22:25:18 +00:00
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/*
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* XXX doesn't really belong here I guess...
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*/
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#define ISA_HOLE_START 0xa0000
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#define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
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1996-05-02 14:21:14 +00:00
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#ifndef LOCORE
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1996-09-08 16:57:53 +00:00
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2004-06-20 00:33:14 +00:00
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#include <sys/queue.h>
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Commit the support for removing cpumask_t and replacing it directly with
cpuset_t objects.
That is going to offer the underlying support for a simple bump of
MAXCPU and then support for number of cpus > 32 (as it is today).
Right now, cpumask_t is an int, 32 bits on all our supported architecture.
cpumask_t on the other side is implemented as an array of longs, and
easilly extendible by definition.
The architectures touched by this commit are the following:
- amd64
- i386
- pc98
- arm
- ia64
- XEN
while the others are still missing.
Userland is believed to be fully converted with the changes contained
here.
Some technical notes:
- This commit may be considered an ABI nop for all the architectures
different from amd64 and ia64 (and sparc64 in the future)
- per-cpu members, which are now converted to cpuset_t, needs to be
accessed avoiding migration, because the size of cpuset_t should be
considered unknown
- size of cpuset_t objects is different from kernel and userland (this is
primirally done in order to leave some more space in userland to cope
with KBI extensions). If you need to access kernel cpuset_t from the
userland please refer to example in this patch on how to do that
correctly (kgdb may be a good source, for example).
- Support for other architectures is going to be added soon
- Only MAXCPU for amd64 is bumped now
The patch has been tested by sbruno and Nicholas Esborn on opteron
4 x 12 pack CPUs. More testing on big SMP is expected to came soon.
pluknet tested the patch with his 8-ways on both amd64 and i386.
Tested by: pluknet, sbruno, gianni, Nicholas Esborn
Reviewed by: jeff, jhb, sbruno
2011-05-05 14:39:14 +00:00
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#include <sys/_cpuset.h>
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2004-06-16 07:03:15 +00:00
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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1996-09-08 16:57:53 +00:00
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Sync back vmcontention branch into HEAD:
Replace the per-object resident and cached pages splay tree with a
path-compressed multi-digit radix trie.
Along with this, switch also the x86-specific handling of idle page
tables to using the radix trie.
This change is supposed to do the following:
- Allowing the acquisition of read locking for lookup operations of the
resident/cached pages collections as the per-vm_page_t splay iterators
are now removed.
- Increase the scalability of the operations on the page collections.
The radix trie does rely on the consumers locking to ensure atomicity of
its operations. In order to avoid deadlocks the bisection nodes are
pre-allocated in the UMA zone. This can be done safely because the
algorithm needs at maximum one new node per insert which means the
maximum number of the desired nodes is the number of available physical
frames themselves. However, not all the times a new bisection node is
really needed.
The radix trie implements path-compression because UFS indirect blocks
can lead to several objects with a very sparse trie, increasing the number
of levels to usually scan. It also helps in the nodes pre-fetching by
introducing the single node per-insert property.
This code is not generalized (yet) because of the possible loss of
performance by having much of the sizes in play configurable.
However, efforts to make this code more general and then reusable in
further different consumers might be really done.
The only KPI change is the removal of the function vm_page_splay() which
is now reaped.
The only KBI change, instead, is the removal of the left/right iterators
from struct vm_page, which are now reaped.
Further technical notes broken into mealpieces can be retrieved from the
svn branch:
http://svn.freebsd.org/base/user/attilio/vmcontention/
Sponsored by: EMC / Isilon storage division
In collaboration with: alc, jeff
Tested by: flo, pho, jhb, davide
Tested by: ian (arm)
Tested by: andreast (powerpc)
2013-03-18 00:25:02 +00:00
|
|
|
#include <vm/_vm_radix.h>
|
|
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
2009-03-22 18:56:26 +00:00
|
|
|
* Address of current address space page table maps and directories.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
1999-12-29 04:46:21 +00:00
|
|
|
#ifdef _KERNEL
|
2010-10-05 17:06:51 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Translate a virtual address to its physical address.
|
|
|
|
|
*
|
|
|
|
|
* This macro may be used before pmap_bootstrap() is called.
|
|
|
|
|
*/
|
2005-12-06 21:09:01 +00:00
|
|
|
#define vtophys(va) pmap_kextract((vm_offset_t)(va))
|
1993-06-12 14:58:17 +00:00
|
|
|
|
2019-01-04 17:33:07 +00:00
|
|
|
#define pte_clear(ptep) pte_store(ptep, 0)
|
|
|
|
|
|
|
|
|
|
#define pde_store(pdep, pde) pte_store(pdep, pde)
|
|
|
|
|
|
2003-04-28 20:35:36 +00:00
|
|
|
#endif /* _KERNEL */
|
1997-07-17 04:34:03 +00:00
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
|
|
|
|
* Pmap stuff
|
|
|
|
|
*/
|
1996-09-08 16:57:53 +00:00
|
|
|
struct pv_entry;
|
MFamd64: shrink pv entries from 24 bytes to about 12 bytes. (336 pv entries
per page = effectively 12.19 bytes per pv entry after overheads).
Instead of using a shared UMA zone for 24 byte pv entries (two 8-byte tailq
nodes, a 4 byte pointer, and a 4 byte address), we allocate a page at a
time per process. This provides 336 pv entries per process (actually, per
pmap address space) and eliminates one of the 8-byte tailq entries since
we now can track per-process pv entries implicitly. The pointer to
the pmap can be eliminated by doing address arithmetic to find the metadata
on the page headers to find a single pointer shared by all 336 entries.
There is an 11-int bitmap for the freelist of those 336 entries.
This is mostly a mechanical conversion from amd64, except:
* i386 has to allocate kvm and map the pages, amd64 has them outside of kvm
* native word size is smaller, so bitmaps etc become 32 bit instead of 64
* no dump_add_page() etc stuff because they are in kvm always.
* various pmap internals tweaks because pmap uses direct map on amd64 but
on i386 it has to use sched_pin and temporary mappings.
Also, sysctl vm.pmap.pv_entry_max and vm.pmap.shpgperproc are now
dynamic sysctls. Like on amd64, i386 can now tune the pv entry limits
without a recompile or reboot.
This is important because of the following scenario. If you have a 1GB
file (262144 pages) mmap()ed into 50 processes, that requires 13 million
pv entries. At 24 bytes per pv entry, that is 314MB of ram and kvm, while
at 12 bytes it is 157MB. A 157MB saving is significant.
Test-run by: scottl (Thanks!)
2006-04-26 21:49:20 +00:00
|
|
|
struct pv_chunk;
|
2000-05-21 12:50:18 +00:00
|
|
|
|
|
|
|
|
struct md_page {
|
2000-05-26 02:09:24 +00:00
|
|
|
TAILQ_HEAD(,pv_entry) pv_list;
|
2009-07-12 23:31:20 +00:00
|
|
|
int pat_mode;
|
2000-05-21 12:50:18 +00:00
|
|
|
};
|
1993-06-12 14:58:17 +00:00
|
|
|
|
|
|
|
|
struct pmap {
|
2020-01-07 15:59:31 +00:00
|
|
|
cpuset_t pm_active; /* active on cpus */
|
|
|
|
|
struct mtx pm_mtx;
|
|
|
|
|
struct pmap_statistics pm_stats; /* pmap statistics */
|
|
|
|
|
uint32_t *pm_pdir_nopae; /* KVA of page directory */
|
|
|
|
|
uint64_t *pm_pdir_pae;
|
MFamd64: shrink pv entries from 24 bytes to about 12 bytes. (336 pv entries
per page = effectively 12.19 bytes per pv entry after overheads).
Instead of using a shared UMA zone for 24 byte pv entries (two 8-byte tailq
nodes, a 4 byte pointer, and a 4 byte address), we allocate a page at a
time per process. This provides 336 pv entries per process (actually, per
pmap address space) and eliminates one of the 8-byte tailq entries since
we now can track per-process pv entries implicitly. The pointer to
the pmap can be eliminated by doing address arithmetic to find the metadata
on the page headers to find a single pointer shared by all 336 entries.
There is an 11-int bitmap for the freelist of those 336 entries.
This is mostly a mechanical conversion from amd64, except:
* i386 has to allocate kvm and map the pages, amd64 has them outside of kvm
* native word size is smaller, so bitmaps etc become 32 bit instead of 64
* no dump_add_page() etc stuff because they are in kvm always.
* various pmap internals tweaks because pmap uses direct map on amd64 but
on i386 it has to use sched_pin and temporary mappings.
Also, sysctl vm.pmap.pv_entry_max and vm.pmap.shpgperproc are now
dynamic sysctls. Like on amd64, i386 can now tune the pv entry limits
without a recompile or reboot.
This is important because of the following scenario. If you have a 1GB
file (262144 pages) mmap()ed into 50 processes, that requires 13 million
pv entries. At 24 bytes per pv entry, that is 314MB of ram and kvm, while
at 12 bytes it is 157MB. A 157MB saving is significant.
Test-run by: scottl (Thanks!)
2006-04-26 21:49:20 +00:00
|
|
|
TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
|
2000-08-16 21:24:44 +00:00
|
|
|
LIST_ENTRY(pmap) pm_list; /* List of all pmaps */
|
2020-01-07 15:59:31 +00:00
|
|
|
uint64_t *pm_pdpt_pae;
|
Sync back vmcontention branch into HEAD:
Replace the per-object resident and cached pages splay tree with a
path-compressed multi-digit radix trie.
Along with this, switch also the x86-specific handling of idle page
tables to using the radix trie.
This change is supposed to do the following:
- Allowing the acquisition of read locking for lookup operations of the
resident/cached pages collections as the per-vm_page_t splay iterators
are now removed.
- Increase the scalability of the operations on the page collections.
The radix trie does rely on the consumers locking to ensure atomicity of
its operations. In order to avoid deadlocks the bisection nodes are
pre-allocated in the UMA zone. This can be done safely because the
algorithm needs at maximum one new node per insert which means the
maximum number of the desired nodes is the number of available physical
frames themselves. However, not all the times a new bisection node is
really needed.
The radix trie implements path-compression because UFS indirect blocks
can lead to several objects with a very sparse trie, increasing the number
of levels to usually scan. It also helps in the nodes pre-fetching by
introducing the single node per-insert property.
This code is not generalized (yet) because of the possible loss of
performance by having much of the sizes in play configurable.
However, efforts to make this code more general and then reusable in
further different consumers might be really done.
The only KPI change is the removal of the function vm_page_splay() which
is now reaped.
The only KBI change, instead, is the removal of the left/right iterators
from struct vm_page, which are now reaped.
Further technical notes broken into mealpieces can be retrieved from the
svn branch:
http://svn.freebsd.org/base/user/attilio/vmcontention/
Sponsored by: EMC / Isilon storage division
In collaboration with: alc, jeff
Tested by: flo, pho, jhb, davide
Tested by: ian (arm)
Tested by: andreast (powerpc)
2013-03-18 00:25:02 +00:00
|
|
|
struct vm_radix pm_root; /* spare page table pages */
|
2020-01-07 15:59:31 +00:00
|
|
|
vm_page_t pm_ptdpg[4]; /* PAE NPGPTD */
|
1993-06-12 14:58:17 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
typedef struct pmap *pmap_t;
|
|
|
|
|
|
1999-12-29 04:46:21 +00:00
|
|
|
#ifdef _KERNEL
|
2002-04-29 07:43:16 +00:00
|
|
|
extern struct pmap kernel_pmap_store;
|
|
|
|
|
#define kernel_pmap (&kernel_pmap_store)
|
2004-06-16 07:03:15 +00:00
|
|
|
|
|
|
|
|
#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
|
|
|
|
|
#define PMAP_LOCK_ASSERT(pmap, type) \
|
|
|
|
|
mtx_assert(&(pmap)->pm_mtx, (type))
|
|
|
|
|
#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
|
|
|
|
|
#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
|
2004-09-29 19:20:40 +00:00
|
|
|
NULL, MTX_DEF | MTX_DUPOK)
|
2004-06-16 07:03:15 +00:00
|
|
|
#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
|
|
|
|
|
#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
|
|
|
|
|
#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
|
|
|
|
|
#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
|
1993-06-12 14:58:17 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* For each vm_page_t, there is a list of all currently valid virtual
|
2006-11-13 06:26:57 +00:00
|
|
|
* mappings of that page. An entry is a pv_entry_t, the list is pv_list.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
|
|
|
|
typedef struct pv_entry {
|
|
|
|
|
vm_offset_t pv_va; /* virtual address for mapping */
|
2013-03-02 14:19:08 +00:00
|
|
|
TAILQ_ENTRY(pv_entry) pv_next;
|
1993-06-12 14:58:17 +00:00
|
|
|
} *pv_entry_t;
|
|
|
|
|
|
MFamd64: shrink pv entries from 24 bytes to about 12 bytes. (336 pv entries
per page = effectively 12.19 bytes per pv entry after overheads).
Instead of using a shared UMA zone for 24 byte pv entries (two 8-byte tailq
nodes, a 4 byte pointer, and a 4 byte address), we allocate a page at a
time per process. This provides 336 pv entries per process (actually, per
pmap address space) and eliminates one of the 8-byte tailq entries since
we now can track per-process pv entries implicitly. The pointer to
the pmap can be eliminated by doing address arithmetic to find the metadata
on the page headers to find a single pointer shared by all 336 entries.
There is an 11-int bitmap for the freelist of those 336 entries.
This is mostly a mechanical conversion from amd64, except:
* i386 has to allocate kvm and map the pages, amd64 has them outside of kvm
* native word size is smaller, so bitmaps etc become 32 bit instead of 64
* no dump_add_page() etc stuff because they are in kvm always.
* various pmap internals tweaks because pmap uses direct map on amd64 but
on i386 it has to use sched_pin and temporary mappings.
Also, sysctl vm.pmap.pv_entry_max and vm.pmap.shpgperproc are now
dynamic sysctls. Like on amd64, i386 can now tune the pv entry limits
without a recompile or reboot.
This is important because of the following scenario. If you have a 1GB
file (262144 pages) mmap()ed into 50 processes, that requires 13 million
pv entries. At 24 bytes per pv entry, that is 314MB of ram and kvm, while
at 12 bytes it is 157MB. A 157MB saving is significant.
Test-run by: scottl (Thanks!)
2006-04-26 21:49:20 +00:00
|
|
|
/*
|
|
|
|
|
* pv_entries are allocated in chunks per-process. This avoids the
|
|
|
|
|
* need to track per-pmap assignments.
|
|
|
|
|
*/
|
|
|
|
|
#define _NPCM 11
|
|
|
|
|
#define _NPCPV 336
|
|
|
|
|
struct pv_chunk {
|
|
|
|
|
pmap_t pc_pmap;
|
|
|
|
|
TAILQ_ENTRY(pv_chunk) pc_list;
|
|
|
|
|
uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */
|
2012-05-26 06:10:25 +00:00
|
|
|
TAILQ_ENTRY(pv_chunk) pc_lru;
|
MFamd64: shrink pv entries from 24 bytes to about 12 bytes. (336 pv entries
per page = effectively 12.19 bytes per pv entry after overheads).
Instead of using a shared UMA zone for 24 byte pv entries (two 8-byte tailq
nodes, a 4 byte pointer, and a 4 byte address), we allocate a page at a
time per process. This provides 336 pv entries per process (actually, per
pmap address space) and eliminates one of the 8-byte tailq entries since
we now can track per-process pv entries implicitly. The pointer to
the pmap can be eliminated by doing address arithmetic to find the metadata
on the page headers to find a single pointer shared by all 336 entries.
There is an 11-int bitmap for the freelist of those 336 entries.
This is mostly a mechanical conversion from amd64, except:
* i386 has to allocate kvm and map the pages, amd64 has them outside of kvm
* native word size is smaller, so bitmaps etc become 32 bit instead of 64
* no dump_add_page() etc stuff because they are in kvm always.
* various pmap internals tweaks because pmap uses direct map on amd64 but
on i386 it has to use sched_pin and temporary mappings.
Also, sysctl vm.pmap.pv_entry_max and vm.pmap.shpgperproc are now
dynamic sysctls. Like on amd64, i386 can now tune the pv entry limits
without a recompile or reboot.
This is important because of the following scenario. If you have a 1GB
file (262144 pages) mmap()ed into 50 processes, that requires 13 million
pv entries. At 24 bytes per pv entry, that is 314MB of ram and kvm, while
at 12 bytes it is 157MB. A 157MB saving is significant.
Test-run by: scottl (Thanks!)
2006-04-26 21:49:20 +00:00
|
|
|
struct pv_entry pc_pventry[_NPCPV];
|
|
|
|
|
};
|
|
|
|
|
|
1999-12-29 04:46:21 +00:00
|
|
|
#ifdef _KERNEL
|
1993-06-12 14:58:17 +00:00
|
|
|
|
1997-11-20 19:30:35 +00:00
|
|
|
extern char *ptvmmap; /* poor name! */
|
1995-03-16 18:17:34 +00:00
|
|
|
extern vm_offset_t virtual_avail;
|
|
|
|
|
extern vm_offset_t virtual_end;
|
1993-06-12 14:58:17 +00:00
|
|
|
|
2009-07-12 23:31:20 +00:00
|
|
|
#define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
|
2019-12-10 18:14:50 +00:00
|
|
|
#define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0)
|
2006-08-11 19:22:57 +00:00
|
|
|
#define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz))
|
2004-06-13 03:44:11 +00:00
|
|
|
|
2019-02-20 09:51:13 +00:00
|
|
|
static inline int
|
|
|
|
|
pmap_vmspace_copy(pmap_t dst_pmap __unused, pmap_t src_pmap __unused)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
struct sf_buf;
|
|
|
|
|
|
2010-10-05 17:06:51 +00:00
|
|
|
/*
|
|
|
|
|
* Only the following functions or macros may be used before pmap_bootstrap()
|
|
|
|
|
* is called: pmap_kenter(), pmap_kextract(), pmap_kremove(), vtophys(), and
|
|
|
|
|
* vtopte().
|
|
|
|
|
*/
|
2018-08-25 15:21:28 +00:00
|
|
|
void pmap_activate_boot(pmap_t pmap);
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
void pmap_basemem_setup(u_int basemem);
|
|
|
|
|
void *pmap_bios16_enter(void);
|
|
|
|
|
void pmap_bios16_leave(void *handle);
|
2007-03-17 19:42:06 +00:00
|
|
|
void pmap_bootstrap(vm_paddr_t);
|
2018-08-01 18:45:51 +00:00
|
|
|
int pmap_cache_bits(pmap_t, int mode, boolean_t is_pde);
|
2006-08-11 19:22:57 +00:00
|
|
|
int pmap_change_attr(vm_offset_t, vm_size_t, int);
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
caddr_t pmap_cmap3(vm_paddr_t pa, u_int pte_bits);
|
|
|
|
|
void pmap_cp_slow0_map(vm_offset_t kaddr, int plen, vm_page_t *ma);
|
|
|
|
|
void pmap_flush_page(vm_page_t m);
|
|
|
|
|
u_int pmap_get_kcr3(void);
|
|
|
|
|
u_int pmap_get_cr3(pmap_t);
|
|
|
|
|
vm_offset_t pmap_get_map_low(void);
|
|
|
|
|
vm_offset_t pmap_get_vm_maxuser_address(void);
|
2006-05-01 22:07:00 +00:00
|
|
|
void pmap_init_pat(void);
|
2003-03-25 00:07:06 +00:00
|
|
|
void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
|
2004-04-10 23:28:49 +00:00
|
|
|
void *pmap_kenter_temporary(vm_paddr_t pa, int i);
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
vm_paddr_t pmap_kextract(vm_offset_t va);
|
2003-03-16 04:16:03 +00:00
|
|
|
void pmap_kremove(vm_offset_t);
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
void pmap_ksetrw(vm_offset_t va);
|
2006-08-11 19:22:57 +00:00
|
|
|
void *pmap_mapbios(vm_paddr_t, vm_size_t);
|
2003-03-25 00:07:06 +00:00
|
|
|
void *pmap_mapdev(vm_paddr_t, vm_size_t);
|
2006-08-11 19:22:57 +00:00
|
|
|
void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
|
MFamd64 with few changes:
1. Add support for automatic promotion of 4KB page mappings to 2MB page
mappings. Automatic promotion can be enabled by setting the tunable
"vm.pmap.pg_ps_enabled" to a non-zero value. By default, automatic
promotion is disabled. Tested by: kris
2. To date, we have assumed that the TLB will only set the PG_M bit in a
PTE if that PTE has the PG_RW bit set. However, this assumption does
not hold on recent processors from Intel. For example, consider a PTE
that has the PG_RW bit set but the PG_M bit clear. Suppose this PTE
is cached in the TLB and later the PG_RW bit is cleared in the PTE,
but the corresponding TLB entry is not (yet) invalidated.
Historically, upon a write access using this (stale) TLB entry, the
TLB would observe that the PG_RW bit had been cleared and initiate a
page fault, aborting the setting of the PG_M bit in the PTE. Now,
however, P4- and Core2-family processors will set the PG_M bit before
observing that the PG_RW bit is clear and initiating a page fault. In
other words, the write does not occur but the PG_M bit is still set.
The real impact of this difference is not that great. Specifically,
we should no longer assert that any PTE with the PG_M bit set must
also have the PG_RW bit set, and we should ignore the state of the
PG_M bit unless the PG_RW bit is set.
2008-03-27 04:34:17 +00:00
|
|
|
boolean_t pmap_page_is_mapped(vm_page_t m);
|
2009-07-12 23:31:20 +00:00
|
|
|
void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
vm_paddr_t pmap_pg_frame(vm_paddr_t pa);
|
Add support for pmap_enter(..., psind=1) to the i386 pmap. In other words,
add support for explicitly requesting that pmap_enter() create a 2 or 4 MB
page mapping. (Essentially, this feature allows the machine-independent
layer to create superpage mappings preemptively, and not wait for automatic
promotion to occur.)
Export pmap_ps_enabled() to the machine-independent layer.
Add a flag to pmap_pv_insert_pde() that specifies whether it should fail or
reclaim a PV entry when one is not available.
Refactor pmap_enter_pde() into two functions, one by the same name, that is
a general-purpose function for creating PDE PG_PS mappings, and another,
pmap_enter_4mpage(), that is used to prefault 2 or 4 MB read- and/or
execute-only mappings for execve(2), mmap(2), and shmat(2).
Reviewed by: kib
Tested by: pho
Differential Revision: https://reviews.freebsd.org/D16246
2018-07-14 17:20:27 +00:00
|
|
|
bool pmap_ps_enabled(pmap_t pmap);
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
void pmap_remap_lower(bool);
|
|
|
|
|
void pmap_remap_lowptdi(bool);
|
|
|
|
|
void pmap_set_nx(void);
|
|
|
|
|
void pmap_sf_buf_map(struct sf_buf *sf);
|
2002-03-20 05:48:58 +00:00
|
|
|
void pmap_unmapdev(vm_offset_t, vm_size_t);
|
2002-07-12 07:56:11 +00:00
|
|
|
void pmap_invalidate_page(pmap_t, vm_offset_t);
|
|
|
|
|
void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
|
|
|
|
|
void pmap_invalidate_all(pmap_t);
|
2006-05-01 21:36:47 +00:00
|
|
|
void pmap_invalidate_cache(void);
|
2011-04-18 21:24:42 +00:00
|
|
|
void pmap_invalidate_cache_pages(vm_page_t *pages, int count);
|
2018-09-19 19:35:02 +00:00
|
|
|
void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
|
|
|
|
|
void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
|
i386 4/4G split.
The change makes the user and kernel address spaces on i386
independent, giving each almost the full 4G of usable virtual addresses
except for one PDE at top used for trampoline and per-CPU trampoline
stacks, and system structures that must be always mapped, namely IDT,
GDT, common TSS and LDT, and process-private TSS and LDT if allocated.
By using 1:1 mapping for the kernel text and data, it appeared
possible to eliminate assembler part of the locore.S which bootstraps
initial page table and KPTmap. The code is rewritten in C and moved
into the pmap_cold(). The comment in vmparam.h explains the KVA
layout.
There is no PCID mechanism available in protected mode, so each
kernel/user switch forth and back completely flushes the TLB, except
for the trampoline PTD region. The TLB invalidations for userspace
becomes trivial, because IPI handlers switch page tables. On the other
hand, context switches no longer need to reload %cr3.
copyout(9) was rewritten to use vm_fault_quick_hold(). An issue for
new copyout(9) is compatibility with wiring user buffers around sysctl
handlers. This explains two kind of locks for copyout ptes and
accounting of the vslock() calls. The vm_fault_quick_hold() AKA slow
path, is only tried after the 'fast path' failed, which temporary
changes mapping to the userspace and copies the data to/from small
per-cpu buffer in the trampoline. If a page fault occurs during the
copy, it is short-circuit by exception.s to not even reach C code.
The change was motivated by the need to implement the Meltdown
mitigation, but instead of KPTI the full split is done. The i386
architecture already shows the sizing problems, in particular, it is
impossible to link clang and lld with debugging. I expect that the
issues due to the virtual address space limits would only exaggerate
and the split gives more liveness to the platform.
Tested by: pho
Discussed with: bde
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
Differential revision: https://reviews.freebsd.org/D14633
2018-04-13 20:30:49 +00:00
|
|
|
void *pmap_trm_alloc(size_t size, int flags);
|
|
|
|
|
void pmap_trm_free(void *addr, size_t size);
|
1993-12-19 00:55:01 +00:00
|
|
|
|
For amd64 non-PCID machines, and for i386 machines with support for
the PG_G global pte flag, pmap_invalidate_all() fails to flush global
TLB entries [*]. This is because TLB shootdown handler for such
configs reloads CR3, and on i386 pmap_invalidate_all() does the same
for the initiating CPU. Note that current code does not issue total
invalidation requests for the kernel_pmap.
Rename amd64 function invltlb_globpcid() to invltlb_glob(), it is not
specific for PCID for quite some time, and implement the same
functionality for i386. Use the function instead of invltlb() in
shootdown handlers and in i386 pmap_invalidate_all(), but only for the
kernel pmap (which maps pages with the PG_G attribute set), which
takes care of PG_G TLB entries on flush.
To detect the affected pmap in i386 TLB shootdown handler, pmap should
be passed to the smp_masked_invltlb() function, which makes amd64 and
i386 TLB shootdown code almost identical. Merge the code under x86/.
Noted by: jhb [*]
Reviewed by: cem, jhb, pho
Tested by: pho
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D4346
2015-12-03 11:14:14 +00:00
|
|
|
void invltlb_glob(void);
|
|
|
|
|
|
i386: Merge PAE and non-PAE pmaps into same kernel.
Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.
Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.
Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.
i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.
The PAE_TABLES kernel config option is retired.
In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2019-01-30 02:07:13 +00:00
|
|
|
struct thread;
|
|
|
|
|
|
|
|
|
|
extern int pae_mode;
|
|
|
|
|
extern int i386_pmap_VM_NFREEORDER;
|
|
|
|
|
extern int i386_pmap_VM_LEVEL_0_ORDER;
|
|
|
|
|
extern int i386_pmap_PDRSHIFT;
|
|
|
|
|
|
1999-12-29 04:46:21 +00:00
|
|
|
#endif /* _KERNEL */
|
1996-10-12 20:36:15 +00:00
|
|
|
|
1996-05-02 14:21:14 +00:00
|
|
|
#endif /* !LOCORE */
|
1993-06-12 14:58:17 +00:00
|
|
|
|
1994-11-14 14:12:24 +00:00
|
|
|
#endif /* !_MACHINE_PMAP_H_ */
|
