2005-01-06 01:43:34 +00:00
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/*-
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2004-05-11 18:21:38 +00:00
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* Copyright (c) 2004 Texas A&M University
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* All rights reserved.
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*
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* Developer: Wm. Daryl Hawkins
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ICHWD_H_
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2017-09-10 11:57:02 +00:00
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#define _ICHWD_H_
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2004-05-11 18:21:38 +00:00
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struct ichwd_device {
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uint16_t device;
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char *desc;
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2015-08-18 14:54:29 +00:00
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unsigned int ich_version;
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unsigned int tco_version;
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2004-05-11 18:21:38 +00:00
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};
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struct ichwd_softc {
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device_t device;
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2007-08-13 18:52:37 +00:00
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device_t ich;
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2007-12-31 11:42:31 +00:00
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int ich_version;
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2015-08-18 14:54:29 +00:00
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int tco_version;
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2004-05-11 18:21:38 +00:00
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int active;
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unsigned int timeout;
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2011-04-25 14:10:33 +00:00
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int smi_enabled;
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2004-05-11 18:21:38 +00:00
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int smi_rid;
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struct resource *smi_res;
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int tco_rid;
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struct resource *tco_res;
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2007-08-13 18:52:37 +00:00
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int gcs_rid;
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struct resource *gcs_res;
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2004-05-11 18:21:38 +00:00
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eventhandler_tag ev_tag;
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};
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2017-09-10 11:57:02 +00:00
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#define VENDORID_INTEL 0x8086
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#define DEVICEID_BAYTRAIL 0x0f1c
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#define DEVICEID_CPT0 0x1c40
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#define DEVICEID_CPT1 0x1c41
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#define DEVICEID_CPT2 0x1c42
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#define DEVICEID_CPT3 0x1c43
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#define DEVICEID_CPT4 0x1c44
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#define DEVICEID_CPT5 0x1c45
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#define DEVICEID_CPT6 0x1c46
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#define DEVICEID_CPT7 0x1c47
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#define DEVICEID_CPT8 0x1c48
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#define DEVICEID_CPT9 0x1c49
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#define DEVICEID_CPT10 0x1c4a
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#define DEVICEID_CPT11 0x1c4b
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#define DEVICEID_CPT12 0x1c4c
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#define DEVICEID_CPT13 0x1c4d
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#define DEVICEID_CPT14 0x1c4e
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#define DEVICEID_CPT15 0x1c4f
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#define DEVICEID_CPT16 0x1c50
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#define DEVICEID_CPT17 0x1c51
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#define DEVICEID_CPT18 0x1c52
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#define DEVICEID_CPT19 0x1c53
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#define DEVICEID_CPT20 0x1c54
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#define DEVICEID_CPT21 0x1c55
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#define DEVICEID_CPT22 0x1c56
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#define DEVICEID_CPT23 0x1c57
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#define DEVICEID_CPT24 0x1c58
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#define DEVICEID_CPT25 0x1c59
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#define DEVICEID_CPT26 0x1c5a
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#define DEVICEID_CPT27 0x1c5b
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#define DEVICEID_CPT28 0x1c5c
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#define DEVICEID_CPT29 0x1c5d
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#define DEVICEID_CPT30 0x1c5e
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#define DEVICEID_CPT31 0x1c5f
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#define DEVICEID_PATSBURG_LPC1 0x1d40
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#define DEVICEID_PATSBURG_LPC2 0x1d41
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#define DEVICEID_PPT0 0x1e40
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#define DEVICEID_PPT1 0x1e41
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#define DEVICEID_PPT2 0x1e42
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#define DEVICEID_PPT3 0x1e43
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#define DEVICEID_PPT4 0x1e44
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#define DEVICEID_PPT5 0x1e45
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#define DEVICEID_PPT6 0x1e46
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#define DEVICEID_PPT7 0x1e47
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#define DEVICEID_PPT8 0x1e48
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#define DEVICEID_PPT9 0x1e49
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#define DEVICEID_PPT10 0x1e4a
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#define DEVICEID_PPT11 0x1e4b
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#define DEVICEID_PPT12 0x1e4c
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#define DEVICEID_PPT13 0x1e4d
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#define DEVICEID_PPT14 0x1e4e
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#define DEVICEID_PPT15 0x1e4f
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#define DEVICEID_PPT16 0x1e50
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#define DEVICEID_PPT17 0x1e51
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#define DEVICEID_PPT18 0x1e52
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#define DEVICEID_PPT19 0x1e53
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#define DEVICEID_PPT20 0x1e54
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#define DEVICEID_PPT21 0x1e55
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#define DEVICEID_PPT22 0x1e56
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#define DEVICEID_PPT23 0x1e57
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#define DEVICEID_PPT24 0x1e58
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#define DEVICEID_PPT25 0x1e59
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#define DEVICEID_PPT26 0x1e5a
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#define DEVICEID_PPT27 0x1e5b
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#define DEVICEID_PPT28 0x1e5c
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#define DEVICEID_PPT29 0x1e5d
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#define DEVICEID_PPT30 0x1e5e
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#define DEVICEID_PPT31 0x1e5f
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#define DEVICEID_AVN0 0x1f38
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#define DEVICEID_AVN1 0x1f39
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#define DEVICEID_AVN2 0x1f3a
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#define DEVICEID_AVN3 0x1f3b
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#define DEVICEID_BRASWELL 0x229c
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#define DEVICEID_DH89XXCC_LPC 0x2310
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#define DEVICEID_COLETOCRK_LPC 0x2390
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#define DEVICEID_82801AA 0x2410
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#define DEVICEID_82801AB 0x2420
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#define DEVICEID_82801BA 0x2440
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#define DEVICEID_82801BAM 0x244c
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#define DEVICEID_82801CA 0x2480
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#define DEVICEID_82801CAM 0x248c
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#define DEVICEID_82801DB 0x24c0
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#define DEVICEID_82801DBM 0x24cc
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#define DEVICEID_82801E 0x2450
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#define DEVICEID_82801EB 0x24dc
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#define DEVICEID_82801EBR 0x24d0
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#define DEVICEID_6300ESB 0x25a1
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#define DEVICEID_82801FBR 0x2640
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#define DEVICEID_ICH6M 0x2641
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#define DEVICEID_ICH6W 0x2642
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#define DEVICEID_63XXESB 0x2670
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#define DEVICEID_ICH7 0x27b8
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#define DEVICEID_ICH7DH 0x27b0
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#define DEVICEID_ICH7M 0x27b9
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#define DEVICEID_NM10 0x27bc
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#define DEVICEID_ICH7MDH 0x27bd
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#define DEVICEID_ICH8 0x2810
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#define DEVICEID_ICH8DH 0x2812
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#define DEVICEID_ICH8DO 0x2814
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#define DEVICEID_ICH8M 0x2815
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#define DEVICEID_ICH8ME 0x2811
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#define DEVICEID_ICH9 0x2918
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#define DEVICEID_ICH9DH 0x2912
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#define DEVICEID_ICH9DO 0x2914
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#define DEVICEID_ICH9M 0x2919
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#define DEVICEID_ICH9ME 0x2917
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#define DEVICEID_ICH9R 0x2916
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#define DEVICEID_ICH10 0x3a18
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#define DEVICEID_ICH10D 0x3a1a
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#define DEVICEID_ICH10DO 0x3a14
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#define DEVICEID_ICH10R 0x3a16
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#define DEVICEID_PCH 0x3b00
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#define DEVICEID_PCHM 0x3b01
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#define DEVICEID_P55 0x3b02
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#define DEVICEID_PM55 0x3b03
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#define DEVICEID_H55 0x3b06
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#define DEVICEID_QM57 0x3b07
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#define DEVICEID_H57 0x3b08
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#define DEVICEID_HM55 0x3b09
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#define DEVICEID_Q57 0x3b0a
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#define DEVICEID_HM57 0x3b0b
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#define DEVICEID_PCHMSFF 0x3b0d
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#define DEVICEID_QS57 0x3b0f
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#define DEVICEID_3400 0x3b12
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#define DEVICEID_3420 0x3b14
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#define DEVICEID_3450 0x3b16
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#define DEVICEID_LPT0 0x8c40
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#define DEVICEID_LPT1 0x8c41
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#define DEVICEID_LPT2 0x8c42
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#define DEVICEID_LPT3 0x8c43
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#define DEVICEID_LPT4 0x8c44
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#define DEVICEID_LPT5 0x8c45
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#define DEVICEID_LPT6 0x8c46
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#define DEVICEID_LPT7 0x8c47
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#define DEVICEID_LPT8 0x8c48
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#define DEVICEID_LPT9 0x8c49
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#define DEVICEID_LPT10 0x8c4a
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#define DEVICEID_LPT11 0x8c4b
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#define DEVICEID_LPT12 0x8c4c
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#define DEVICEID_LPT13 0x8c4d
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#define DEVICEID_LPT14 0x8c4e
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#define DEVICEID_LPT15 0x8c4f
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#define DEVICEID_LPT16 0x8c50
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#define DEVICEID_LPT17 0x8c51
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#define DEVICEID_LPT18 0x8c52
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#define DEVICEID_LPT19 0x8c53
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#define DEVICEID_LPT20 0x8c54
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#define DEVICEID_LPT21 0x8c55
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#define DEVICEID_LPT22 0x8c56
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#define DEVICEID_LPT23 0x8c57
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#define DEVICEID_LPT24 0x8c58
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#define DEVICEID_LPT25 0x8c59
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#define DEVICEID_LPT26 0x8c5a
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#define DEVICEID_LPT27 0x8c5b
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#define DEVICEID_LPT28 0x8c5c
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#define DEVICEID_LPT29 0x8c5d
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#define DEVICEID_LPT30 0x8c5e
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#define DEVICEID_LPT31 0x8c5f
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#define DEVICEID_WCPT1 0x8cc1
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#define DEVICEID_WCPT2 0x8cc2
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#define DEVICEID_WCPT3 0x8cc3
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#define DEVICEID_WCPT4 0x8cc4
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#define DEVICEID_WCPT6 0x8cc6
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#define DEVICEID_WBG0 0x8d40
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#define DEVICEID_WBG1 0x8d41
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#define DEVICEID_WBG2 0x8d42
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#define DEVICEID_WBG3 0x8d43
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#define DEVICEID_WBG4 0x8d44
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#define DEVICEID_WBG5 0x8d45
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#define DEVICEID_WBG6 0x8d46
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#define DEVICEID_WBG7 0x8d47
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#define DEVICEID_WBG8 0x8d48
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#define DEVICEID_WBG9 0x8d49
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#define DEVICEID_WBG10 0x8d4a
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#define DEVICEID_WBG11 0x8d4b
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#define DEVICEID_WBG12 0x8d4c
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#define DEVICEID_WBG13 0x8d4d
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#define DEVICEID_WBG14 0x8d4e
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#define DEVICEID_WBG15 0x8d4f
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#define DEVICEID_WBG16 0x8d50
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#define DEVICEID_WBG17 0x8d51
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#define DEVICEID_WBG18 0x8d52
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#define DEVICEID_WBG19 0x8d53
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#define DEVICEID_WBG20 0x8d54
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#define DEVICEID_WBG21 0x8d55
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#define DEVICEID_WBG22 0x8d56
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#define DEVICEID_WBG23 0x8d57
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#define DEVICEID_WBG24 0x8d58
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#define DEVICEID_WBG25 0x8d59
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#define DEVICEID_WBG26 0x8d5a
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#define DEVICEID_WBG27 0x8d5b
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#define DEVICEID_WBG28 0x8d5c
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#define DEVICEID_WBG29 0x8d5d
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#define DEVICEID_WBG30 0x8d5e
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#define DEVICEID_WBG31 0x8d5f
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#define DEVICEID_LPT_LP0 0x9c40
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#define DEVICEID_LPT_LP1 0x9c41
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#define DEVICEID_LPT_LP2 0x9c42
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#define DEVICEID_LPT_LP3 0x9c43
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#define DEVICEID_LPT_LP4 0x9c44
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#define DEVICEID_LPT_LP5 0x9c45
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#define DEVICEID_LPT_LP6 0x9c46
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#define DEVICEID_LPT_LP7 0x9c47
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#define DEVICEID_WCPT_LP1 0x9cc1
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#define DEVICEID_WCPT_LP2 0x9cc2
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#define DEVICEID_WCPT_LP3 0x9cc3
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#define DEVICEID_WCPT_LP5 0x9cc5
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#define DEVICEID_WCPT_LP6 0x9cc6
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#define DEVICEID_WCPT_LP7 0x9cc7
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#define DEVICEID_WCPT_LP9 0x9cc9
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2007-08-13 18:52:37 +00:00
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/* ICH LPC Interface Bridge Registers (ICH5 and older) */
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2017-09-10 11:57:02 +00:00
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#define ICH_GEN_STA 0xd4
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#define ICH_GEN_STA_NO_REBOOT 0x02
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#define ICH_PMBASE 0x40 /* ACPI base address register */
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#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */
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2004-05-11 18:21:38 +00:00
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2007-08-13 18:52:37 +00:00
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/* ICH Chipset Configuration Registers (ICH6 and newer) */
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2017-09-10 11:57:02 +00:00
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#define ICH_RCBA 0xf0
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#define ICH_GCS_OFFSET 0x3410
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#define ICH_GCS_SIZE 0x4
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#define ICH_GCS_NO_REBOOT 0x20
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2007-08-13 18:52:37 +00:00
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2015-08-18 14:54:29 +00:00
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/* SoC Power Management Configuration Registers */
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2017-09-10 11:57:02 +00:00
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#define ICH_PBASE 0x44
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#define ICH_PMC_OFFSET 0x08
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#define ICH_PMC_SIZE 0x4
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#define ICH_PMC_NO_REBOOT 0x10
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2015-08-18 14:54:29 +00:00
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2004-05-11 18:21:38 +00:00
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/* register names and locations (relative to PMBASE) */
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2017-09-10 11:57:02 +00:00
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#define SMI_BASE 0x30 /* base address for SMI registers */
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#define SMI_LEN 0x08
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#define SMI_EN 0x00 /* SMI Control and Enable Register */
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#define SMI_STS 0x04 /* SMI Status Register */
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#define TCO_BASE 0x60 /* base address for TCO registers */
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#define TCO_LEN 0x20
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#define TCO_RLD 0x00 /* TCO Reload and Current Value */
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#define TCO_TMR1 0x01 /* TCO Timer Initial Value
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2007-08-13 18:52:37 +00:00
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(ICH5 and older, 8 bits) */
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2017-09-10 11:57:02 +00:00
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#define TCO_TMR2 0x12 /* TCO Timer Initial Value
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2007-08-13 18:52:37 +00:00
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(ICH6 and newer, 16 bits) */
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2017-09-10 11:57:02 +00:00
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#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */
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#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */
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#define TCO1_STS 0x04 /* TCO Status 1 */
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#define TCO2_STS 0x06 /* TCO Status 2 */
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#define TCO1_CNT 0x08 /* TCO Control 1 */
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#define TCO2_CNT 0x08 /* TCO Control 2 */
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#define TCO_MESSAGE1 0x0c /* TCO Message 1 */
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#define TCO_MESSAGE2 0x0d /* TCO Message 2 */
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2017-09-10 12:10:27 +00:00
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#define TCO_WDSTATUS 0x0e /* TCO Watchdog status */
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#define TCO_TMR 0x12 /* TCP Reload value */
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2004-05-11 18:21:38 +00:00
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/* bit definitions for SMI_EN and SMI_STS */
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2017-09-10 11:57:02 +00:00
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#define SMI_TCO_EN 0x2000
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#define SMI_TCO_STS 0x2000
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#define SMI_GBL_EN 0x0001
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2004-05-11 18:21:38 +00:00
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/* timer value mask for TCO_RLD and TCO_TMR */
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2017-09-10 11:57:02 +00:00
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#define TCO_TIMER_MASK 0x1f
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2017-09-10 12:10:27 +00:00
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#define TCO_TIMER_MASK2 0x2f
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2004-05-11 18:21:38 +00:00
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/* status bits for TCO1_STS */
|
2017-09-10 12:10:27 +00:00
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#define TCO_SLVSEL 0x2000 /* TCO Slave Select Soft Strap */
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#define TCO_CPUSERR_STS 0x1000
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#define TCO_CPUSMI_STS 0x0400
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#define TCO_CPUSCI_STS 0x0200
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#define TCO_BIOSWR_STS 0x0100
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#define TCO_NEWCENTURY 0x0080 /* set for RTC year roll over
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(99 to 00) */
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#define TCO_TIMEOUT 0x0008 /* timed out */
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#define TCO_INT_STS 0x0004 /* data out (DO NOT USE) */
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#define TCO_SMI_STS 0x0002 /* data in (DO NOT USE) */
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#define TCO_NMI2SMI_STS 0x0001
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2004-05-11 18:21:38 +00:00
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/* status bits for TCO2_STS */
|
2017-09-10 12:10:27 +00:00
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#define TCO_SMLINK_SLAVE_SMI 0x0010
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#define TCO_BOOT_STS 0x0004 /* failed to come out of reset */
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#define TCO_SECOND_TO_STS 0x0002 /* ran down twice */
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#define TCO_INTRD_DET 0x0001
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2004-05-11 18:21:38 +00:00
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/* control bits for TCO1_CNT */
|
2017-09-10 12:10:27 +00:00
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#define TCO_LOCK 0x1000 /* SMI_BASE.TCO_EN locked */
|
2017-09-10 11:57:02 +00:00
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#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */
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#define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */
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#define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */
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#define TCO_NMI_NOW 0x0100 /* trigger an NMI */
|
2004-05-11 18:21:38 +00:00
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2017-09-10 12:10:27 +00:00
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/* control bits for TCO2_CNT */
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#define TCO_OS_POLICY 0x0030 /* mask */
|
2017-09-10 13:21:54 +00:00
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#define TCO_OS_POLICY_BOOT 0x0000
|
2017-09-10 12:10:27 +00:00
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#define TCO_OS_POLICY_SHUTD 0x0010
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#define TCO_OS_POLICY_NOLOAD 0x0020
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#define TCO_SMB_ALERT_DISABLE 0x0008
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#define TCO_INTRD_SEL 0x0003 /* mask */
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#define TCO_INTRD_SEL_SILENT 0x0000
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#define TCO_INTRD_SEL_INTR 0x0001
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#define TCO_INTRD_SEL_SMI 0x0002
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|
2010-12-08 15:32:54 +00:00
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|
/*
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|
* Masks for the TCO timer value field in TCO_RLD.
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|
* If the datasheets are to be believed, the minimum value actually varies
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* from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
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|
* I suspect this is a bug in the ICH5 datasheet and that the minimum is
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|
* uniformly 2, but I'd rather err on the side of caution.
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*/
|
2017-09-10 11:57:02 +00:00
|
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|
#define TCO_RLD_TMR_MIN 0x0004
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#define TCO_RLD1_TMR_MAX 0x003f
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#define TCO_RLD2_TMR_MAX 0x03ff
|
2010-12-08 15:32:54 +00:00
|
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|
|
2017-09-10 12:10:27 +00:00
|
|
|
/*
|
|
|
|
|
* Approximate length in nanoseconds of one WDT tick (about 0.6 sec)
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|
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|
|
* for TCO v1/v2/v4
|
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|
|
*/
|
2017-09-10 11:57:02 +00:00
|
|
|
#define ICHWD_TICK 600000000
|
2017-09-10 12:10:27 +00:00
|
|
|
/*
|
|
|
|
|
* Approximate length in nanoseconds of one WDT tick (about 1.0 sec)
|
|
|
|
|
* for TCO v3
|
|
|
|
|
*/
|
2017-09-10 11:57:02 +00:00
|
|
|
#define ICHWD_TCO_V3_TICK 1000000000
|
2004-05-11 18:21:38 +00:00
|
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|
#endif
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