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freebsd-dev/sys/i386/include/smptests.h

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Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
/*
* Copyright (c) 1996, by Steve Passe
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. The name of the developer may NOT be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
$Id$ -> $FreeBSD$
1999-08-28 01:08:13 +00:00
* $FreeBSD$
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
*/
#ifndef _MACHINE_SMPTESTS_H_
#define _MACHINE_SMPTESTS_H_
/*
Removed "options SMP_TIMER_NC". Removed TEST_ALTTIMER. Removed APIC_PIN0_TIMER. Removed TIMER_ALL.
1997-07-26 01:47:26 +00:00
* Various 'tests in progress' and configuration parameters.
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
*/
Cleanup.
1997-07-15 03:28:53 +00:00
The improvements to clock statistics by Tor Egge Wrappered and enabled by the define BETTER_CLOCK (on by default in smpyests.h) Reviewed by: smp@csn.net Submitted by: Tor Egge <Tor.Egge@idi.ntnu.no>
1997-12-08 23:00:24 +00:00
/*
* Tor's clock improvements.
*
* When the giant kernel lock disappears, a different strategy should
* probably be used, thus this patch can only be considered a temporary
* measure.
*
* This patch causes (NCPU-1)*(128+100) extra IPIs per second.
* During profiling, the number is (NCPU-1)*(1024+100) extra IPIs/s
* in addition to extra IPIs due to forwarding ASTs to other CPUs.
*
* Having a shared AST flag in an SMP configuration is wrong, and I've
* just kludged around it, based upon the kernel lock blocking other
* processors from entering the kernel while handling an AST for one
* processor. When the giant kernel lock disappers, this kludge breaks.
*
* -- Tor
*/
#define BETTER_CLOCK
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
/*
* Control the "giant lock" pushdown by logical steps.
*/
#define PUSHDOWN_LEVEL_1
#define PUSHDOWN_LEVEL_2
DISABLE LEVEL_3 lock pushdown, somethings seems to have broken!
1997-09-07 23:06:15 +00:00
#define PUSHDOWN_LEVEL_3_NOT
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#define PUSHDOWN_LEVEL_4_NOT
Debug version of simple_lock. This will store the CPU id of the holding CPU along with the lock. When a CPU fails to get the lock it compares its own id to the holder id. If they are the same it panic()s, as simple locks are binary, and this would cause a deadlock. Controlled by smptests.h: SL_DEBUG, ON by default. Some minor cleanup.
1997-08-31 03:17:48 +00:00
/*
* Debug version of simple_lock. This will store the CPU id of the
* holding CPU along with the lock. When a CPU fails to get the lock
* it compares its own id to the holder id. If they are the same it
* panic()s, as simple locks are binary, and this would cause a deadlock.
*
*/
#define SL_DEBUG
Introduce FAST_HI option, ON by default. This options allows a CPU that is blocked spinning for the giant lock to process FAST_INTR() ISRs, eg. siointr().
1997-08-29 17:58:30 +00:00
/*
* Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
* Allow the mp_lock() routines to handle FAST interrupts while spinning.
*/
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#ifdef PUSHDOWN_LEVEL_1
Introduce FAST_HI option, ON by default. This options allows a CPU that is blocked spinning for the giant lock to process FAST_INTR() ISRs, eg. siointr().
1997-08-29 17:58:30 +00:00
#define FAST_HI
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#endif
Introduce FAST_HI option, ON by default. This options allows a CPU that is blocked spinning for the giant lock to process FAST_INTR() ISRs, eg. siointr().
1997-08-29 17:58:30 +00:00
Another round of lock pushdown. Add a simplelock to deal with disable_intr()/enable_intr() as used in UP kernel. UP kernel expects that this is enough to guarantee exclusive access to regions of code bracketed by these 2 functions. Add a simplelock to bracket clock accesses in clock.c: clock_lock. Help from: Bruce Evans <bde@zeta.org.au>
1997-08-30 08:08:10 +00:00
/*
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
* These defines enable critical region locking of areas that were
* protected via cli/sti in the UP kernel.
Another round of lock pushdown. Add a simplelock to deal with disable_intr()/enable_intr() as used in UP kernel. UP kernel expects that this is enough to guarantee exclusive access to regions of code bracketed by these 2 functions. Add a simplelock to bracket clock accesses in clock.c: clock_lock. Help from: Bruce Evans <bde@zeta.org.au>
1997-08-30 08:08:10 +00:00
*
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
* COMLOCK protects the sio/cy drivers.
* known to be incomplete:
* joystick lkm
* ?
Another round of lock pushdown. Add a simplelock to deal with disable_intr()/enable_intr() as used in UP kernel. UP kernel expects that this is enough to guarantee exclusive access to regions of code bracketed by these 2 functions. Add a simplelock to bracket clock accesses in clock.c: clock_lock. Help from: Bruce Evans <bde@zeta.org.au>
1997-08-30 08:08:10 +00:00
*/
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#ifdef PUSHDOWN_LEVEL_1
Debug version of simple_lock. This will store the CPU id of the holding CPU along with the lock. When a CPU fails to get the lock it compares its own id to the holder id. If they are the same it panic()s, as simple locks are binary, and this would cause a deadlock. Controlled by smptests.h: SL_DEBUG, ON by default. Some minor cleanup.
1997-08-31 03:17:48 +00:00
#define USE_COMLOCK
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#endif
Debug version of simple_lock. This will store the CPU id of the holding CPU along with the lock. When a CPU fails to get the lock it compares its own id to the holder id. If they are the same it panic()s, as simple locks are binary, and this would cause a deadlock. Controlled by smptests.h: SL_DEBUG, ON by default. Some minor cleanup.
1997-08-31 03:17:48 +00:00
Introduce FAST_HI option, ON by default. This options allows a CPU that is blocked spinning for the giant lock to process FAST_INTR() ISRs, eg. siointr().
1997-08-29 17:58:30 +00:00
/*
Commit major SMP cleanups and move the BGL (big giant lock) in the syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
2000-03-28 07:16:37 +00:00
* INTR_SIMPLELOCK has been removed, as the interrupt mechanism will likely
* not use this sort of optimization if we move to interrupt threads.
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
*/
#ifdef PUSHDOWN_LEVEL_4
#endif
/*
Commit major SMP cleanups and move the BGL (big giant lock) in the syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
2000-03-28 07:16:37 +00:00
* CPL_AND_CML has been removed. Interrupt threads will eventually not
* use either mechanism so there is no point trying to optimize it.
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
*/
#ifdef PUSHDOWN_LEVEL_3
#endif
/*
Commit major SMP cleanups and move the BGL (big giant lock) in the syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
2000-03-28 07:16:37 +00:00
* SPL_DEBUG_POSTCODE/INTR_SPL/SPL_DEBUG - removed
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
*
Commit major SMP cleanups and move the BGL (big giant lock) in the syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
2000-03-28 07:16:37 +00:00
* These functions were too expensive for the standard case but, more
* importantly, we should be able to come up with a much cleaner way
* to handle the cpl. Having to do any locking at all is a mistake
* for something that is modified as often as cpl is.
Introduce FAST_HI option, ON by default. This options allows a CPU that is blocked spinning for the giant lock to process FAST_INTR() ISRs, eg. siointr().
1997-08-29 17:58:30 +00:00
*/
Preperation for moving cpl into critical region access. Several new fine-grained locks. Control of new FAST_INTR() methods.
1997-08-20 05:22:33 +00:00
/*
Commit major SMP cleanups and move the BGL (big giant lock) in the syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
2000-03-28 07:16:37 +00:00
* FAST_WITHOUTCPL - now made the default (define removed). Text below
* contains the current discussion. I am confident we can find a solution
* that does not require us to process softints from a hard int, which can
* kill serial performance due to the lack of true hardware ipl's.
*
****
*
Preperation for moving cpl into critical region access. Several new fine-grained locks. Control of new FAST_INTR() methods.
1997-08-20 05:22:33 +00:00
* Ignore the ipending bits when exiting FAST_INTR() routines.
Made PEND_INTS default. Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
1997-08-21 05:08:25 +00:00
*
* according to Bruce:
*
* setsoft*() may set ipending. setsofttty() is actually used in the
* FAST_INTR handler in some serial drivers. This is necessary to get
* output completions and other urgent events handled as soon as possible.
* The flag(s) could be set in a variable other than ipending, but they
* needs to be checked against cpl to decide whether the software interrupt
* handler can/should run.
*
* (FAST_INTR used to just return
* in all cases until rev.1.7 of vector.s. This worked OK provided there
* were no user-mode CPU hogs. CPU hogs caused an average latency of 1/2
* clock tick for output completions...)
***
*
* So I need to restore cpl handling someday, but AFTER
* I finish making spl/cpl MP-safe.
Preperation for moving cpl into critical region access. Several new fine-grained locks. Control of new FAST_INTR() methods.
1997-08-20 05:22:33 +00:00
*/
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#ifdef PUSHDOWN_LEVEL_1
#endif
Preperation for moving cpl into critical region access. Several new fine-grained locks. Control of new FAST_INTR() methods.
1997-08-20 05:22:33 +00:00
/*
Commit major SMP cleanups and move the BGL (big giant lock) in the syscall path inward. A system call may select whether it needs the MP lock or not (the default being that it does need it). A great deal of conditional SMP code for various deadended experiments has been removed. 'cil' and 'cml' have been removed entirely, and the locking around the cpl has been removed. The conditional separately-locked fast-interrupt code has been removed, meaning that interrupts must hold the CPL now (but they pretty much had to anyway). Another reason for doing this is that the original separate-lock for interrupts just doesn't apply to the interrupt thread mechanism being contemplated. Modifications to the cpl may now ONLY occur while holding the MP lock. For example, if an otherwise MP safe syscall needs to mess with the cpl, it must hold the MP lock for the duration and must (as usual) save/restore the cpl in a nested fashion. This is precursor work for the real meat coming later: avoiding having to hold the MP lock for common syscalls and I/O's and interrupt threads. It is expected that the spl mechanisms and new interrupt threading mechanisms will be able to run in tandem, allowing a slow piecemeal transition to occur. This patch should result in a moderate performance improvement due to the considerable amount of code that has been removed from the critical path, especially the simplification of the spl*() calls. The real performance gains will come later. Approved by: jkh Reviewed by: current, bde (exception.s) Some work taken from: luoqi's patch
2000-03-28 07:16:37 +00:00
* FAST_SIMPLELOCK no longer exists, because it doesn't help us. The cpu
* is likely to already hold the MP lock and recursive MP locks are now
* very cheap, so we do not need this optimization. Eventually *ALL*
* interrupts will run in their own thread, so there is no sense complicating
* matters now.
Preperation for moving cpl into critical region access. Several new fine-grained locks. Control of new FAST_INTR() methods.
1997-08-20 05:22:33 +00:00
*/
General cleanup of the lock pushdown code. They are grouped and enabled from machine/smptests.h: #define PUSHDOWN_LEVEL_1 #define PUSHDOWN_LEVEL_2 #define PUSHDOWN_LEVEL_3 #define PUSHDOWN_LEVEL_4_NOT
1997-09-07 22:04:09 +00:00
#ifdef PUSHDOWN_LEVEL_1
#endif
Preperation for moving cpl into critical region access. Several new fine-grained locks. Control of new FAST_INTR() methods.
1997-08-20 05:22:33 +00:00
Eliminate frequent silo overflows by restoring the TEST_LOPRIO code. This code was eliminated when the PEND_INTS algorithm was added. But it was discovered that PEND_INTS only worsen latency for FAST_INTR() routines, which can't be marked pending. Noticed & debugged by: dave adkins <adkin003@gold.tc.umn.edu>
1997-08-04 17:31:43 +00:00
/*
* Portions of the old TEST_LOPRIO code, back from the grave!
*/
#define GRAB_LOPRIO
Added a test called 'LATE_START'. This is now the default, it delays most of the MP startup to the function machdep.c:cpu_startup(). It should be possible to move the 2 functions found there (mp_start() & mp_announce()) even further down the path once we know exactly where that should be... Help from: Peter Wemm <peter@spinner.dialix.com.au>
1997-05-26 09:23:30 +00:00
/*
Split TEST_CPUSTOP code into CPUSTOP_ON_DDBBREAK and mainline code.
1997-07-18 21:27:53 +00:00
* Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
New defines to eliminate "magic numbers" in various places.
1997-07-15 02:47:54 +00:00
*/
Major update to the way synchronization is done in the kernel. Highlights include: * Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The alpha port is still in transition and currently uses both.) * Per-CPU idle processes. * Interrupts are run in their own separate kernel threads and can be preempted (i386 only). Partially contributed by: BSDi (BSD/OS) Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh
2000-09-07 01:33:02 +00:00
#define VERBOSE_CPUSTOP_ON_DDBBREAK
Split TEST_CPUSTOP code into CPUSTOP_ON_DDBBREAK and mainline code.
1997-07-18 21:27:53 +00:00
#define CPUSTOP_ON_DDBBREAK
New defines to eliminate "magic numbers" in various places.
1997-07-15 02:47:54 +00:00
/*
* Bracket code/comments relevant to the current 'giant lock' model.
* Everything is now the 'giant lock' model, but we will use this as
* we start to "push down" the lock.
Added a test called 'LATE_START'. This is now the default, it delays most of the MP startup to the function machdep.c:cpu_startup(). It should be possible to move the 2 functions found there (mp_start() & mp_announce()) even further down the path once we know exactly where that should be... Help from: Peter Wemm <peter@spinner.dialix.com.au>
1997-05-26 09:23:30 +00:00
*/
New defines to eliminate "magic numbers" in various places.
1997-07-15 02:47:54 +00:00
#define GIANT_LOCK
Added a test called 'LATE_START'. This is now the default, it delays most of the MP startup to the function machdep.c:cpu_startup(). It should be possible to move the 2 functions found there (mp_start() & mp_announce()) even further down the path once we know exactly where that should be... Help from: Peter Wemm <peter@spinner.dialix.com.au>
1997-05-26 09:23:30 +00:00
When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts.
1998-03-03 22:56:30 +00:00
#ifdef APIC_IO
/*
* Enable extra counters for some selected locations in the interrupt handlers.
* Look in apic_vector.s, apic_ipl.s and ipl.s for APIC_ITRACE or
* APIC_INTR_DIAGNOSTIC.
*/
#undef APIC_INTR_DIAGNOSTIC
/*
* Add extra tracking of a specific interrupt. Look in apic_vector.s,
* apic_ipl.s and ipl.s for APIC_ITRACE and log_intr_event.
* APIC_INTR_DIAGNOSTIC must be defined for this to work.
*/
#ifdef APIC_INTR_DIAGNOSTIC
#define APIC_INTR_DIAGNOSTIC_IRQ 17
#endif
/*
* Don't assume that slow interrupt handler X is called from vector
* X + ICU_OFFSET.
*/
#define APIC_INTR_REORDER
/*
* Redirect clock interrupts to a higher priority (fast intr) vector,
* while still using the slow interrupt handler. Only effective when
* APIC_INTR_REORDER is defined.
*/
Reenable redirection of clock interrupt to a higher priority vector. setidt() now knows about f00f_hack(), and the APs now use the same interrupt descriptor table as the BSP.
1998-03-07 20:48:16 +00:00
#define APIC_INTR_HIGHPRI_CLOCK
When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts.
1998-03-03 22:56:30 +00:00
#endif /* APIC_IO */
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
/*
Made PEND_INTS default. Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
1997-08-21 05:08:25 +00:00
* Misc. counters.
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
*
#define COUNT_XINVLTLB_HITS
*/
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
/**
Made PEND_INTS default. Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
1997-08-21 05:08:25 +00:00
* Hack to "fake-out" kernel into thinking it is running on a 'default config'.
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
*
* value == default type
#define TEST_DEFAULT_CONFIG 6
*/
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
/*
Made PEND_INTS default. Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
1997-08-21 05:08:25 +00:00
* Simple test code for IPI interaction, save for future...
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
*
#define TEST_TEST1
#define IPI_TARGET_TEST1 1
*/
Cleanup.
1997-07-15 03:28:53 +00:00
Removed "options SMP_TIMER_NC". Removed TEST_ALTTIMER. Removed APIC_PIN0_TIMER. Removed TIMER_ALL.
1997-07-26 01:47:26 +00:00
/*
* Address of POST hardware port.
* Defining this enables POSTCODE macros.
*
#define POST_ADDR 0x80
*/
Cleanup.
1997-07-15 03:28:53 +00:00
/*
* POST hardware macros.
*/
#ifdef POST_ADDR
#define ASMPOSTCODE_INC \
pushl %eax ; \
movl _current_postcode, %eax ; \
incl %eax ; \
andl $0xff, %eax ; \
movl %eax, _current_postcode ; \
outb %al, $POST_ADDR ; \
popl %eax
/*
* Overwrite the current_postcode value.
*/
#define ASMPOSTCODE(X) \
pushl %eax ; \
movl $X, %eax ; \
movl %eax, _current_postcode ; \
outb %al, $POST_ADDR ; \
popl %eax
/*
* Overwrite the current_postcode low nibble.
*/
#define ASMPOSTCODE_LO(X) \
pushl %eax ; \
movl _current_postcode, %eax ; \
andl $0xf0, %eax ; \
orl $X, %eax ; \
movl %eax, _current_postcode ; \
outb %al, $POST_ADDR ; \
popl %eax
/*
* Overwrite the current_postcode high nibble.
*/
#define ASMPOSTCODE_HI(X) \
pushl %eax ; \
movl _current_postcode, %eax ; \
andl $0x0f, %eax ; \
orl $(X<<4), %eax ; \
movl %eax, _current_postcode ; \
outb %al, $POST_ADDR ; \
popl %eax
#else
#define ASMPOSTCODE_INC
#define ASMPOSTCODE(X)
#define ASMPOSTCODE_LO(X)
#define ASMPOSTCODE_HI(X)
#endif /* POST_ADDR */
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
/*
Made PEND_INTS default. Made NEW_STRATEGY default. Removed misc. old cruft. Centralized simple locks into mp_machdep.c Centralized simple lock macros into param.h More cleanup in the direction of making splxx()/cpl MP-safe.
1997-08-21 05:08:25 +00:00
* These are all temps for debugging...
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
*
#define GUARD_INTS
*/
Split TEST_CPUSTOP code into CPUSTOP_ON_DDBBREAK and mainline code.
1997-07-18 21:27:53 +00:00
/*
* This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
*/
Many new test defines, including: - TEST_CPUSTOP adds stop_cpus()/restart_cpus(), OFF by default - TEST_ALTTIMER new method for attaching 8259 PIC to APIC this method avoids 'ExtInt' programming, ON by default - TIMER_ALL sends 8259/8254 timer INTs to all CPUs, ON by default - ASMPOSTCODExxx code to display bytes to POST hardware, OFF by default
1997-07-13 01:15:30 +00:00
#ifdef GUARD_INTS
#define GUARD_CPU 1
#define MAYBE_PANIC(irq_num) \
cmpl $GUARD_CPU, _cpuid ; \
jne 9f ; \
cmpl $1, _ok_test1 ; \
jne 9f ; \
pushl lapic_isr3 ; \
pushl lapic_isr2 ; \
pushl lapic_isr1 ; \
pushl lapic_isr0 ; \
pushl lapic_irr3 ; \
pushl lapic_irr2 ; \
pushl lapic_irr1 ; \
pushl lapic_irr0 ; \
pushl $irq_num ; \
pushl _cpuid ; \
pushl $panic_msg ; \
call _printf ; \
addl $44, %esp ; \
9:
#else
#define MAYBE_PANIC(irq_num)
#endif /* GUARD_INTS */
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
1997-04-26 11:46:25 +00:00
#endif /* _MACHINE_SMPTESTS_H_ */
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