2005-01-06 01:43:34 +00:00
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/*-
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2017-11-27 14:52:40 +00:00
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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1999-09-01 21:21:03 +00:00
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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1999-09-05 15:21:05 +00:00
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* $FreeBSD$
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1999-09-01 21:21:03 +00:00
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*/
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2000-12-26 06:38:04 +00:00
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#ifndef SYS_DEV_ED_IF_EDVAR_H
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2013-12-29 19:21:59 +00:00
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#define SYS_DEV_ED_IF_EDVAR_H
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#include <dev/mii/mii_bitbang.h>
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1999-09-01 21:21:03 +00:00
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/*
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* ed_softc: per line info and status
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*/
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struct ed_softc {
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2005-06-10 16:49:24 +00:00
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struct ifnet *ifp;
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2005-08-28 23:56:25 +00:00
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struct ifmedia ifmedia; /* Media info */
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device_t dev;
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struct mtx sc_mtx;
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1999-09-01 21:21:03 +00:00
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char *type_str; /* pointer to type string */
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u_char vendor; /* interface vendor */
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u_char type; /* interface type code */
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2005-02-14 06:25:06 +00:00
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u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */
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u_char isa16bit; /* width of access to card 0=8 or 1=16 */
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u_char mem_shared; /* NIC memory is shared with host */
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u_char xmit_busy; /* transmitter is busy */
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2005-06-10 16:49:24 +00:00
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u_char enaddr[6];
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1999-09-01 21:21:03 +00:00
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int port_used; /* nonzero if ports used */
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struct resource* port_res; /* resource for port range */
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2009-04-20 01:19:59 +00:00
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struct resource* port_res2; /* resource for port range */
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2005-02-22 05:12:25 +00:00
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bus_space_tag_t port_bst;
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bus_space_handle_t port_bsh;
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1999-09-01 21:21:03 +00:00
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int mem_used; /* nonzero if memory used */
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struct resource* mem_res; /* resource for memory range */
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2005-02-22 05:12:25 +00:00
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bus_space_tag_t mem_bst;
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bus_space_handle_t mem_bsh;
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1999-09-01 21:21:03 +00:00
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struct resource* irq_res; /* resource for irq */
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void* irq_handle; /* handle for irq handler */
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2005-09-18 20:51:34 +00:00
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int (*sc_media_ioctl)(struct ed_softc *sc, struct ifreq *ifr,
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u_long command);
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void (*sc_mediachg)(struct ed_softc *);
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2001-03-03 08:31:37 +00:00
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device_t miibus; /* MII bus for cards with MII. */
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2013-12-29 19:21:59 +00:00
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mii_bitbang_ops_t mii_bitbang_ops;
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2005-08-28 23:56:25 +00:00
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struct callout tick_ch;
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2009-11-17 14:23:09 +00:00
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void (*sc_tick)(struct ed_softc *);
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2005-08-28 23:56:25 +00:00
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void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst,
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uint16_t amount);
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2006-01-27 19:10:13 +00:00
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u_short (*sc_write_mbufs)(struct ed_softc *, struct mbuf *, bus_size_t);
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1999-09-01 21:21:03 +00:00
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2009-11-17 14:23:09 +00:00
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int tx_timer;
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2000-08-17 12:15:45 +00:00
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int nic_offset; /* NIC (DS8390) I/O bus address offset */
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int asic_offset; /* ASIC I/O bus address offset */
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1999-09-01 21:21:03 +00:00
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/*
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* The following 'proto' variable is part of a work-around for 8013EBT asics
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* being write-only. It's sort of a prototype/shadow of the real thing.
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*/
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u_char wd_laar_proto;
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u_char cr_proto;
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/*
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* HP PC LAN PLUS card support.
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*/
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u_short hpp_options; /* flags controlling behaviour of the HP card */
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u_short hpp_id; /* software revision and other fields */
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2000-08-17 12:15:45 +00:00
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caddr_t hpp_mem_start; /* Memory-mapped IO register address */
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1999-09-01 21:21:03 +00:00
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2005-08-28 23:56:25 +00:00
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bus_size_t mem_start; /* NIC memory start address */
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bus_size_t mem_end; /* NIC memory end address */
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2005-01-19 07:37:32 +00:00
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uint32_t mem_size; /* total NIC memory size */
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2005-08-28 23:56:25 +00:00
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bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
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1999-09-01 21:21:03 +00:00
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u_char txb_cnt; /* number of transmit buffers */
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u_char txb_inuse; /* number of TX buffers currently in-use */
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u_char txb_new; /* pointer to where new buffer will be added */
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u_char txb_next_tx; /* pointer to next buffer ready to xmit */
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u_short txb_len[8]; /* buffered xmit buffer lengths */
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u_char tx_page_start; /* first page of TX buffer area */
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u_char rec_page_start; /* first page of RX ring-buffer */
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u_char rec_page_stop; /* last page of RX ring-buffer */
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u_char next_packet; /* pointer to next unread RX packet */
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2006-06-12 04:30:42 +00:00
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u_int tx_mem; /* Total amount of RAM for tx */
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u_int rx_mem; /* Total amount of RAM for rx */
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1999-09-01 21:21:03 +00:00
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struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
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};
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1999-10-15 03:12:48 +00:00
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2013-12-29 19:21:59 +00:00
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#define ed_nic_barrier(sc, port, length, flags) \
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bus_space_barrier(sc->port_bst, sc->port_bsh, \
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(sc)->nic_offset + (port), (length), (flags))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_inb(sc, port) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_outb(sc, port, value) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_1(sc->port_bst, sc->port_bsh, \
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(sc)->nic_offset + (port), (value))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_inw(sc, port) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_outw(sc, port, value) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_2(sc->port_bst, sc->port_bsh, \
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(sc)->nic_offset + (port), (value))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_insb(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
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2000-08-17 12:15:45 +00:00
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(sc)->nic_offset + (port), (addr), (count))
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#define ed_nic_outsb(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
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2000-08-17 12:15:45 +00:00
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(sc)->nic_offset + (port), (addr), (count))
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#define ed_nic_insw(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->nic_offset + (port), (uint16_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_outsw(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->nic_offset + (port), (uint16_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_insl(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->nic_offset + (port), (uint32_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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#define ed_nic_outsl(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->nic_offset + (port), (uint32_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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2013-12-29 19:21:59 +00:00
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#define ed_asic_barrier(sc, port, length, flags) \
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bus_space_barrier(sc->port_bst, sc->port_bsh, \
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(sc)->asic_offset + (port), (length), (flags))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_inb(sc, port) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_1(sc->port_bst, sc->port_bsh, \
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(sc)->asic_offset + (port))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_outb(sc, port, value) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_1(sc->port_bst, sc->port_bsh, \
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(sc)->asic_offset + (port), (value))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_inw(sc, port) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_2(sc->port_bst, sc->port_bsh, \
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(sc)->asic_offset + (port))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_outw(sc, port, value) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_2(sc->port_bst, sc->port_bsh, \
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(sc)->asic_offset + (port), (value))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_insb(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
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2000-08-17 12:15:45 +00:00
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(sc)->asic_offset + (port), (addr), (count))
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#define ed_asic_outsb(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
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2000-08-17 12:15:45 +00:00
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(sc)->asic_offset + (port), (addr), (count))
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#define ed_asic_insw(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->asic_offset + (port), (uint16_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_outsw(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->asic_offset + (port), (uint16_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_insl(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->asic_offset + (port), (uint32_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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#define ed_asic_outsl(sc, port, addr, count) \
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2005-02-22 05:12:25 +00:00
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bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
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2005-01-19 07:37:32 +00:00
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(sc)->asic_offset + (port), (uint32_t *)(addr), (count))
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2000-08-17 12:15:45 +00:00
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2005-02-08 05:41:54 +00:00
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void ed_release_resources(device_t);
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int ed_alloc_port(device_t, int, int);
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int ed_alloc_memory(device_t, int, int);
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int ed_alloc_irq(device_t, int, int);
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int ed_probe_generic8390(struct ed_softc *);
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int ed_probe_WD80x3(device_t, int, int);
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2005-02-08 05:59:43 +00:00
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int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]);
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2005-10-05 05:21:07 +00:00
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int ed_probe_RTL80x9(device_t, int, int);
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2005-02-20 18:44:45 +00:00
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#ifdef ED_3C503
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2005-02-08 05:41:54 +00:00
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int ed_probe_3Com(device_t, int, int);
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2005-02-20 18:44:45 +00:00
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#endif
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#ifdef ED_SIC
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2005-02-08 05:41:54 +00:00
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int ed_probe_SIC(device_t, int, int);
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2005-02-20 18:44:45 +00:00
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#endif
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2005-09-07 03:20:33 +00:00
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int ed_probe_Novell_generic(device_t, int);
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2005-02-08 05:41:54 +00:00
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int ed_probe_Novell(device_t, int, int);
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2005-02-14 22:28:51 +00:00
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void ed_Novell_read_mac(struct ed_softc *);
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2005-02-20 18:44:45 +00:00
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#ifdef ED_HPP
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2005-02-08 05:41:54 +00:00
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int ed_probe_HP_pclanp(device_t, int, int);
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2005-02-20 18:44:45 +00:00
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#endif
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2005-02-08 05:41:54 +00:00
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int ed_attach(device_t);
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2005-02-08 05:45:35 +00:00
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int ed_detach(device_t);
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2005-02-08 23:57:43 +00:00
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int ed_clear_memory(device_t);
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2005-02-09 20:03:40 +00:00
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int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */
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2005-02-08 05:41:54 +00:00
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void ed_stop(struct ed_softc *);
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2005-08-28 23:56:25 +00:00
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void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
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void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
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2006-01-27 19:10:13 +00:00
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u_short ed_shmem_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t);
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2005-08-28 23:56:25 +00:00
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void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t);
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2005-02-08 05:59:43 +00:00
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void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t);
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2006-01-27 19:10:13 +00:00
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u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t);
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2005-02-09 20:03:40 +00:00
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2005-02-10 23:48:13 +00:00
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void ed_disable_16bit_access(struct ed_softc *);
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void ed_enable_16bit_access(struct ed_softc *);
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2009-04-07 05:41:38 +00:00
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void ed_gen_ifmedia_init(struct ed_softc *);
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1999-10-15 03:12:48 +00:00
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driver_intr_t edintr;
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2000-12-26 06:38:04 +00:00
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extern devclass_t ed_devclass;
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2005-02-14 22:28:51 +00:00
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/*
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* Vendor types
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*/
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#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
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#define ED_VENDOR_3COM 0x01 /* 3Com */
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#define ED_VENDOR_NOVELL 0x02 /* Novell */
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#define ED_VENDOR_HP 0x03 /* Hewlett Packard */
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#define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */
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/*
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2006-01-27 07:51:26 +00:00
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* Configure time flags
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2005-02-14 22:28:51 +00:00
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*/
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/*
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* this sets the default for enabling/disabling the transceiver
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*/
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#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
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/*
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* This forces the board to be used in 8/16bit mode even if it
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* autoconfigs differently
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*/
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#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
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#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
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/*
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* This disables the use of double transmit buffers.
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*/
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#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
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/*
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* This forces all operations with the NIC memory to use Programmed
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* I/O (i.e. not via shared memory)
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*/
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#define ED_FLAGS_FORCE_PIO 0x0010
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2009-03-28 04:56:56 +00:00
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/*
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* This forces a PC Card, and disables ISA memory range checks
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*/
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#define ED_FLAGS_PCCARD 0x0020
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2005-02-14 22:28:51 +00:00
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/*
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* These are flags describing the chip type.
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*/
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#define ED_FLAGS_TOSH_ETHER 0x10000
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#define ED_FLAGS_GWETHER 0x20000
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#define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000)
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2005-08-28 23:56:25 +00:00
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#define ED_MUTEX(_sc) (&(_sc)->sc_mtx)
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#define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc))
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#define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc))
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#define ED_LOCK_INIT(_sc) \
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mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \
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MTX_NETWORK_LOCK, MTX_DEF)
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#define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc));
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#define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED);
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#define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED);
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2000-12-26 06:38:04 +00:00
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#endif /* SYS_DEV_ED_IF_EDVAR_H */
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