2004-05-14 11:46:45 +00:00
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/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */
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/* $FreeBSD$ */
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#ifndef MACHINE_CPU_H
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#define MACHINE_CPU_H
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#include <machine/armreg.h>
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2013-10-27 01:34:10 +00:00
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#include <machine/frame.h>
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2004-05-14 11:46:45 +00:00
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2012-06-03 18:34:32 +00:00
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void cpu_halt(void);
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void swi_vm(void *);
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2004-05-14 11:46:45 +00:00
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2013-07-28 18:44:17 +00:00
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#ifdef _KERNEL
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2015-01-08 03:59:03 +00:00
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#if __ARM_ARCH >= 6
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#include <machine/cpu-v6.h>
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2016-02-05 09:46:24 +00:00
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#else
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#include <machine/cpu-v4.h>
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2015-11-09 17:57:32 +00:00
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#endif /* __ARM_ARCH >= 6 */
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2004-05-14 11:46:45 +00:00
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static __inline uint64_t
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get_cyclecount(void)
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{
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2019-10-07 07:37:42 +00:00
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#if __ARM_ARCH > 6 || (__ARM_ARCH == 6 && defined(CPU_ARM1176))
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2015-11-09 17:57:32 +00:00
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#if (__ARM_ARCH > 6) && defined(DEV_PMU)
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if (pmu_attched) {
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u_int cpu;
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uint64_t h, h2;
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uint32_t l, r;
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cpu = PCPU_GET(cpuid);
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h = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]);
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l = cp15_pmccntr_get();
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/* In case interrupts are disabled we need to check for overflow. */
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r = cp15_pmovsr_get();
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if (r & PMU_OVSR_C) {
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atomic_add_32(&ccnt_hi[cpu], 1);
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/* Clear the event. */
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cp15_pmovsr_set(PMU_OVSR_C);
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}
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/* Make sure there was no wrap-around while we read the lo half. */
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h2 = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]);
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if (h != h2)
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l = cp15_pmccntr_get();
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return (h2 << 32 | l);
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} else
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#endif
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return cp15_pmccntr_get();
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Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.
The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.
One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.
Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.
Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.
Reviewed by: ian@ (an earlier version)
Tested by: ian@ (same earlier version)
Committed from: WANDBOARD-QUAD
2014-05-14 19:11:15 +00:00
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#else /* No performance counters, so use binuptime(9). This is slooooow */
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2004-11-04 19:15:43 +00:00
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struct bintime bt;
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binuptime(&bt);
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2011-03-14 23:30:14 +00:00
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return ((uint64_t)bt.sec << 56 | bt.frac >> 8);
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Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.
The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.
One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.
Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.
Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.
Reviewed by: ian@ (an earlier version)
Tested by: ian@ (same earlier version)
Committed from: WANDBOARD-QUAD
2014-05-14 19:11:15 +00:00
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#endif
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2004-05-14 11:46:45 +00:00
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}
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2013-07-28 18:44:17 +00:00
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#endif
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2004-05-14 11:46:45 +00:00
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#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
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#define TRAPF_PC(tfp) ((tfp)->tf_pc)
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2012-06-03 18:34:32 +00:00
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#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp)
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#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp))
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2004-08-03 18:44:27 +00:00
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#define cpu_spinwait() /* nothing */
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2018-11-05 21:34:17 +00:00
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#define cpu_lock_delay() DELAY(1)
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2004-05-14 11:46:45 +00:00
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#define ARM_NVEC 8
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#define ARM_VEC_ALL 0xffffffff
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extern vm_offset_t vector_page;
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2014-02-09 15:54:31 +00:00
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/*
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* Params passed into initarm. If you change the size of this you will
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* need to update locore.S to allocate more memory on the stack before
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* it calls initarm.
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*/
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2012-06-03 18:34:32 +00:00
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struct arm_boot_params {
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register_t abp_size; /* Size of this structure */
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register_t abp_r0; /* r0 from the boot loader */
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register_t abp_r1; /* r1 from the boot loader */
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register_t abp_r2; /* r2 from the boot loader */
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register_t abp_r3; /* r3 from the boot loader */
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2014-02-06 20:17:58 +00:00
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vm_offset_t abp_physaddr; /* The kernel physical address */
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2014-02-09 15:54:31 +00:00
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vm_offset_t abp_pagetable; /* The early page table */
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2012-06-03 18:34:32 +00:00
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};
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2005-02-01 06:36:27 +00:00
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void arm_vector_init(vm_offset_t, int);
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void fork_trampoline(void);
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void identify_arm_cpu(void);
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2012-06-03 18:34:32 +00:00
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void *initarm(struct arm_boot_params *);
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2004-05-14 11:46:45 +00:00
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extern char btext[];
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extern char etext[];
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2012-06-03 18:34:32 +00:00
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int badaddr_read(void *, size_t, void *);
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2004-05-14 11:46:45 +00:00
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#endif /* !MACHINE_CPU_H */
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