2004-05-14 11:46:45 +00:00
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/* $NetBSD: frame.h,v 1.6 2003/10/05 19:44:58 matt Exp $ */
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2005-01-05 21:58:49 +00:00
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/*-
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2004-05-14 11:46:45 +00:00
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* Copyright (c) 1994-1997 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ASMACROS_H_
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#define _MACHINE_ASMACROS_H_
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2012-08-15 03:03:03 +00:00
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#include <machine/asm.h>
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2004-05-14 11:46:45 +00:00
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#ifdef _KERNEL
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#ifdef LOCORE
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2012-08-15 03:03:03 +00:00
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#include "opt_global.h"
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2004-05-14 11:46:45 +00:00
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/*
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* ASM macros for pushing and pulling trapframes from the stack
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*
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* These macros are used to handle the irqframe and trapframe structures
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* defined above.
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*/
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/*
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* PUSHFRAME - macro to push a trap frame on the stack in the current mode
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* Since the current mode is used, the SVC lr field is not defined.
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*
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* NOTE: r13 and r14 are stored separately as a work around for the
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* SA110 rev 2 STM^ bug
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*/
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2012-08-15 03:03:03 +00:00
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#ifdef ARM_TP_ADDRESS
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2004-05-14 11:46:45 +00:00
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#define PUSHFRAME \
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str lr, [sp, #-4]!; /* Push the return address */ \
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sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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Close a race.
The RAS implementation would set the end address, then the start
address. These were used by the kernel to restart a RAS sequence if
it was interrupted. When the thread switching code ran, it would
check these values and adjust the PC and clear them if it did.
However, there's a small flaw in this scheme. Thread T1, sets the end
address and gets preempted. Thread T2 runs and also does a RAS
operation. This resets end to zero. Thread T1 now runs again and
sets start and then begins the RAS sequence, but is preempted before
the RAS sequence executes its last instruction. The kernel code that
would ordinarily restart the RAS sequence doesn't because the PC isn't
between start and 0, so the PC isn't set to the start of the sequence.
So when T1 is resumed again, it is at the wrong location for RAS to
produce the correct results. This causes the wrong results for the
atomic sequence.
The window for the first race is 3 instructions. The window for the
second race is 5-10 instructions depending on the atomic operation.
This makes this failure fairly rare and hard to reproduce.
Mutexs are implemented in libthr using atomic operations. When the
above race would occur, a lock could get stuck locked, causing many
downstream problems, as you might expect.
Also, make sure to reset the start and end address when doing a syscall, or
a malicious process could set them before doing a syscall.
Reviewed by: imp, ups (thanks guys)
Pointy hat to: cognet
MFC After: 3 days
2007-12-02 12:49:28 +00:00
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str r0, [sp, #-4]!; \
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2008-02-05 10:22:33 +00:00
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ldr r0, =ARM_RAS_START; \
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Close a race.
The RAS implementation would set the end address, then the start
address. These were used by the kernel to restart a RAS sequence if
it was interrupted. When the thread switching code ran, it would
check these values and adjust the PC and clear them if it did.
However, there's a small flaw in this scheme. Thread T1, sets the end
address and gets preempted. Thread T2 runs and also does a RAS
operation. This resets end to zero. Thread T1 now runs again and
sets start and then begins the RAS sequence, but is preempted before
the RAS sequence executes its last instruction. The kernel code that
would ordinarily restart the RAS sequence doesn't because the PC isn't
between start and 0, so the PC isn't set to the start of the sequence.
So when T1 is resumed again, it is at the wrong location for RAS to
produce the correct results. This causes the wrong results for the
atomic sequence.
The window for the first race is 3 instructions. The window for the
second race is 5-10 instructions depending on the atomic operation.
This makes this failure fairly rare and hard to reproduce.
Mutexs are implemented in libthr using atomic operations. When the
above race would occur, a lock could get stuck locked, causing many
downstream problems, as you might expect.
Also, make sure to reset the start and end address when doing a syscall, or
a malicious process could set them before doing a syscall.
Reviewed by: imp, ups (thanks guys)
Pointy hat to: cognet
MFC After: 3 days
2007-12-02 12:49:28 +00:00
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mov r1, #0; \
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str r1, [r0]; \
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mov r1, #0xffffffff; \
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2011-10-16 17:59:28 +00:00
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str r1, [r0, #4];
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2012-08-15 03:03:03 +00:00
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#else
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#define PUSHFRAME \
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str lr, [sp, #-4]!; /* Push the return address */ \
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sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!;
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#endif
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2004-05-14 11:46:45 +00:00
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/*
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* PULLFRAME - macro to pull a trap frame from the stack in the current mode
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* Since the current mode is used, the SVC lr field is ignored.
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*/
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2012-08-15 03:03:03 +00:00
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#ifdef ARM_TP_ADDRESS
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2004-05-14 11:46:45 +00:00
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#define PULLFRAME \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*17); /* Adjust the stack pointer */ \
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ldr lr, [sp], #0x0004; /* Pull the return address */
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2012-08-15 03:03:03 +00:00
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#else
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#define PULLFRAME \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; \
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clrex; \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*17); /* Adjust the stack pointer */ \
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ldr lr, [sp], #0x0004; /* Pull the return address */
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#endif
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2004-05-14 11:46:45 +00:00
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/*
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* PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
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* This should only be used if the processor is not currently in SVC32
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* mode. The processor mode is switched to SVC mode and the trap frame is
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* stored. The SVC lr field is used to store the previous value of
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2012-06-13 05:02:51 +00:00
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* lr in SVC mode.
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2004-05-14 11:46:45 +00:00
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*
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* NOTE: r13 and r14 are stored separately as a work around for the
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* SA110 rev 2 STM^ bug
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*/
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2012-08-15 03:03:03 +00:00
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#ifdef ARM_TP_ADDRESS
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2004-05-14 11:46:45 +00:00
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#define PUSHFRAMEINSVC \
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stmdb sp, {r0-r3}; /* Save 4 registers */ \
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mov r0, lr; /* Save xxx32 r14 */ \
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mov r1, sp; /* Save xxx32 sp */ \
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mrs r3, spsr; /* Save xxx32 spsr */ \
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mrs r2, cpsr; /* Get the CPSR */ \
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bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
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orr r2, r2, #(PSR_SVC32_MODE); \
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msr cpsr_c, r2; /* Punch into SVC mode */ \
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mov r2, sp; /* Save SVC sp */ \
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str r0, [sp, #-4]!; /* Push return address */ \
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str lr, [sp, #-4]!; /* Push SVC lr */ \
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str r2, [sp, #-4]!; /* Push SVC sp */ \
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msr spsr_all, r3; /* Restore correct spsr */ \
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ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
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sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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2008-02-05 10:22:33 +00:00
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ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \
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2011-10-16 17:59:28 +00:00
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ldr r4, [r5, #4]; /* reset it to point at the */ \
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cmp r4, #0xffffffff; /* end of memory if necessary; */ \
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movne r1, #0xffffffff; /* leave value in r4 for later */ \
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strne r1, [r5, #4]; /* comparision against PC. */ \
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ldr r3, [r5]; /* Retrieve global RAS_START */ \
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cmp r3, #0; /* and reset it if non-zero. */ \
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movne r1, #0; /* If non-zero RAS_START and */ \
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strne r1, [r5]; /* PC was lower than RAS_END, */ \
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ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \
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cmpne r4, r1; /* execution later resumes at */ \
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strhi r3, [r0, #16]; /* the RAS_START location. */ \
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mrs r0, spsr_all; \
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str r0, [sp, #-4]!
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2012-08-15 03:03:03 +00:00
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#else
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#define PUSHFRAMEINSVC \
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stmdb sp, {r0-r3}; /* Save 4 registers */ \
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mov r0, lr; /* Save xxx32 r14 */ \
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mov r1, sp; /* Save xxx32 sp */ \
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mrs r3, spsr; /* Save xxx32 spsr */ \
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mrs r2, cpsr; /* Get the CPSR */ \
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bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
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orr r2, r2, #(PSR_SVC32_MODE); \
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msr cpsr_c, r2; /* Punch into SVC mode */ \
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mov r2, sp; /* Save SVC sp */ \
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str r0, [sp, #-4]!; /* Push return address */ \
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str lr, [sp, #-4]!; /* Push SVC lr */ \
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str r2, [sp, #-4]!; /* Push SVC sp */ \
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msr spsr_all, r3; /* Restore correct spsr */ \
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ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
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sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!
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#endif
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2004-05-14 11:46:45 +00:00
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/*
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* PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
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* in SVC32 mode and restore the saved processor mode and PC.
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* This should be used when the SVC lr register needs to be restored on
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* exit.
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*/
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2012-08-15 03:03:03 +00:00
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#ifdef ARM_TP_ADDRESS
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2004-05-14 11:46:45 +00:00
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#define PULLFRAMEFROMSVCANDEXIT \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; /* restore SPSR */ \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*15); /* Adjust the stack pointer */ \
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ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
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2012-08-15 03:03:03 +00:00
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#else
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#define PULLFRAMEFROMSVCANDEXIT \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; /* restore SPSR */ \
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clrex; \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*15); /* Adjust the stack pointer */ \
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ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
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#endif
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2004-05-14 11:46:45 +00:00
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#define DATA(name) \
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.data ; \
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_ALIGN_DATA ; \
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.globl name ; \
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.type name, %object ; \
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name:
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2012-08-15 03:03:03 +00:00
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#ifdef _ARM_ARCH_6
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#define AST_LOCALS
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#define GET_CURTHREAD_PTR(tmp) \
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mrc p15, 0, tmp, c13, c0, 4; \
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add tmp, tmp, #(PC_CURTHREAD)
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#else
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#define AST_LOCALS ;\
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.Lcurthread: ;\
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.word _C_LABEL(__pcpu) + PC_CURTHREAD
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#define GET_CURTHREAD_PTR(tmp) \
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ldr tmp, .Lcurthread
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#endif
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2004-05-14 11:46:45 +00:00
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2004-09-23 22:05:40 +00:00
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#define DO_AST \
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2004-05-14 11:46:45 +00:00
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ldr r0, [sp] /* Get the SPSR from stack */ ;\
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mrs r4, cpsr /* save CPSR */ ;\
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2006-04-13 14:25:28 +00:00
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orr r1, r4, #(I32_bit|F32_bit) ;\
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2004-09-23 22:05:40 +00:00
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msr cpsr_c, r1 /* Disable interrupts */ ;\
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2004-05-14 11:46:45 +00:00
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and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
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teq r0, #(PSR_USR32_MODE) ;\
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bne 2f /* Nope, get out now */ ;\
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2006-04-13 14:25:28 +00:00
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bic r4, r4, #(I32_bit|F32_bit) ;\
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2012-08-15 03:03:03 +00:00
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1: GET_CURTHREAD_PTR(r5) ;\
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2004-05-14 11:46:45 +00:00
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ldr r5, [r5] ;\
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2004-09-23 22:05:40 +00:00
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ldr r1, [r5, #(TD_FLAGS)] ;\
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and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\
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teq r1, #0x00000000 ;\
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2004-05-14 11:46:45 +00:00
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beq 2f /* Nope. Just bail */ ;\
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msr cpsr_c, r4 /* Restore interrupts */ ;\
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mov r0, sp ;\
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2004-09-23 22:05:40 +00:00
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bl _C_LABEL(ast) /* ast(frame) */ ;\
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2006-04-13 14:25:28 +00:00
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orr r0, r4, #(I32_bit|F32_bit) ;\
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2004-09-23 22:05:40 +00:00
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msr cpsr_c, r0 ;\
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b 1b ;\
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2004-05-14 11:46:45 +00:00
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2:
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#endif /* LOCORE */
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#endif /* _KERNEL */
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#endif /* !_MACHINE_ASMACROS_H_ */
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