2014-03-30 15:22:36 +00:00
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Samsung Exynos 5 Inter-Integrated Circuit (I2C)
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* Chapter 13, Exynos 5 Dual User's Manual Public Rev 1.00
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/samsung/exynos/exynos5_common.h>
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#define I2CCON 0x00 /* Control register */
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#define ACKGEN (1 << 7) /* Acknowledge Enable */
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/*
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* Source Clock of I2C-bus Transmit Clock Prescaler
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*
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* 0 = I2CCLK = fPCLK/16
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* 1 = I2CCLK = fPCLK/512
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*/
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#define I2CCLK (1 << 6)
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#define IRQ_EN (1 << 5) /* Tx/Rx Interrupt Enable/Disable */
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#define IPEND (1 << 4) /* Tx/Rx Interrupt Pending Flag */
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#define CLKVAL_M 0xf /* Transmit Clock Prescaler Mask */
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#define CLKVAL_S 0
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#define I2CSTAT 0x04 /* Control/status register */
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#define I2CMODE_M 0x3 /* Master/Slave Tx/Rx Mode Select */
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#define I2CMODE_S 6
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#define I2CMODE_SR 0x0 /* Slave Receive Mode */
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#define I2CMODE_ST 0x1 /* Slave Transmit Mode */
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#define I2CMODE_MR 0x2 /* Master Receive Mode */
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#define I2CMODE_MT 0x3 /* Master Transmit Mode */
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#define I2CSTAT_BSY (1 << 5) /* Busy Signal Status bit */
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#define I2C_START_STOP (1 << 5) /* Busy Signal Status bit */
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#define RXTX_EN (1 << 4) /* Data Output Enable/Disable */
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#define ARBST (1 << 3) /* Arbitration status flag */
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#define ADDAS (1 << 2) /* Address-as-slave Status Flag */
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#define ADDZERO (1 << 1) /* Address Zero Status Flag */
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#define ACKRECVD (1 << 0) /* Last-received Bit Status Flag */
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#define I2CADD 0x08 /* Address register */
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#define I2CDS 0x0C /* Transmit/receive data shift */
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#define I2CLC 0x10 /* Multi-master line control */
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#define FILTER_EN (1 << 2) /* Filter Enable bit */
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#define SDAOUT_DELAY_M 0x3 /* SDA Line Delay Length */
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#define SDAOUT_DELAY_S 0
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#ifdef DEBUG
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#define DPRINTF(fmt, args...) \
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printf(fmt, ##args)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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static int i2c_start(device_t, u_char, int);
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static int i2c_stop(device_t);
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static int i2c_reset(device_t, u_char, u_char, u_char *);
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static int i2c_read(device_t, char *, int, int *, int, int);
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static int i2c_write(device_t, const char *, int, int *, int);
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struct i2c_softc {
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struct resource *res[2];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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device_t iicbus;
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struct mtx mutex;
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void *ih;
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int intr;
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};
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static struct resource_spec i2c_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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i2c_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "exynos,i2c"))
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return (ENXIO);
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device_set_desc(dev, "Samsung Exynos 5 I2C controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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clear_ipend(struct i2c_softc *sc)
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{
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int reg;
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reg = READ1(sc, I2CCON);
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reg &= ~(IPEND);
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WRITE1(sc, I2CCON, reg);
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return (0);
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}
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static int
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i2c_attach(device_t dev)
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{
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struct i2c_softc *sc;
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int reg;
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sc = device_get_softc(dev);
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sc->dev = dev;
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mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
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if (bus_alloc_resources(dev, i2c_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "could not add iicbus child");
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mtx_destroy(&sc->mutex);
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return (ENXIO);
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}
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WRITE1(sc, I2CSTAT, 0);
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WRITE1(sc, I2CADD, 0x00);
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/* Mode */
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reg = (RXTX_EN);
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reg |= (I2CMODE_MT << I2CMODE_S);
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WRITE1(sc, I2CSTAT, reg);
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bus_generic_attach(dev);
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return (0);
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}
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static int
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wait_for_iif(struct i2c_softc *sc)
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{
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int retry;
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int reg;
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retry = 1000;
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while (retry --) {
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reg = READ1(sc, I2CCON);
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if (reg & IPEND) {
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return (IIC_NOERR);
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}
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DELAY(50);
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}
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return (IIC_ETIMEOUT);
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}
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static int
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wait_for_nibb(struct i2c_softc *sc)
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{
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int retry;
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retry = 1000;
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while (retry --) {
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if ((READ1(sc, I2CSTAT) & I2CSTAT_BSY) == 0)
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return (IIC_NOERR);
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DELAY(10);
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}
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return (IIC_ETIMEOUT);
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}
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static int
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is_ack(struct i2c_softc *sc)
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{
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int stat;
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stat = READ1(sc, I2CSTAT);
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if (!(stat & 1)) {
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/* ACK received */
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return (1);
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}
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return (0);
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}
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static int
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i2c_start(device_t dev, u_char slave, int timeout)
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{
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struct i2c_softc *sc;
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int error;
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int reg;
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sc = device_get_softc(dev);
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DPRINTF("i2c start\n");
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mtx_lock(&sc->mutex);
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#if 0
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DPRINTF("I2CCON == 0x%08x\n", READ1(sc, I2CCON));
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DPRINTF("I2CSTAT == 0x%08x\n", READ1(sc, I2CSTAT));
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#endif
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if (slave & 1) {
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slave &= ~(1);
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slave <<= 1;
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slave |= 1;
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} else {
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slave <<= 1;
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}
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error = wait_for_nibb(sc);
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if (error) {
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mtx_unlock(&sc->mutex);
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2015-10-09 22:49:50 +00:00
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DPRINTF("cant i2c start: IIC_EBUSERR\n");
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return (IIC_EBUSERR);
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2014-03-30 15:22:36 +00:00
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}
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reg = READ1(sc, I2CCON);
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reg |= (IRQ_EN | ACKGEN);
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WRITE1(sc, I2CCON, reg);
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WRITE1(sc, I2CDS, slave);
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DELAY(50);
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reg = (RXTX_EN);
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reg |= I2C_START_STOP;
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reg |= (I2CMODE_MT << I2CMODE_S);
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WRITE1(sc, I2CSTAT, reg);
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error = wait_for_iif(sc);
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if (error) {
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DPRINTF("cant i2c start: iif error\n");
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mtx_unlock(&sc->mutex);
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return (error);
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}
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if (!is_ack(sc)) {
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DPRINTF("cant i2c start: no ack\n");
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mtx_unlock(&sc->mutex);
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return (IIC_ENOACK);
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2016-04-10 23:07:00 +00:00
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}
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2014-03-30 15:22:36 +00:00
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static int
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i2c_stop(device_t dev)
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{
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struct i2c_softc *sc;
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int reg;
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int error;
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sc = device_get_softc(dev);
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DPRINTF("i2c stop\n");
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mtx_lock(&sc->mutex);
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reg = READ1(sc, I2CSTAT);
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int mode = (reg >> I2CMODE_S) & I2CMODE_M;
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reg = (RXTX_EN);
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reg |= (mode << I2CMODE_S);
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WRITE1(sc, I2CSTAT, reg);
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clear_ipend(sc);
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error = wait_for_nibb(sc);
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if (error) {
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DPRINTF("cant i2c stop: nibb error\n");
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return (error);
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}
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static int
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i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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DPRINTF("i2c reset\n");
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mtx_lock(&sc->mutex);
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/* TODO */
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static int
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i2c_read(device_t dev, char *buf, int len,
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int *read, int last, int delay)
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{
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struct i2c_softc *sc;
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int error;
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int reg;
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uint8_t d;
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sc = device_get_softc(dev);
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DPRINTF("i2c read\n");
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reg = (RXTX_EN);
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reg |= (I2CMODE_MR << I2CMODE_S);
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reg |= I2C_START_STOP;
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WRITE1(sc, I2CSTAT, reg);
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*read = 0;
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mtx_lock(&sc->mutex);
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/* dummy read */
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2014-06-01 08:45:27 +00:00
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clear_ipend(sc);
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error = wait_for_iif(sc);
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if (error) {
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DPRINTF("cant i2c read: iif error\n");
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mtx_unlock(&sc->mutex);
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return (error);
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}
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2014-03-30 15:22:36 +00:00
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READ1(sc, I2CDS);
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|
DPRINTF("Read ");
|
|
|
|
while (*read < len) {
|
|
|
|
/* Do not ack last read */
|
|
|
|
if (*read == (len - 1)) {
|
|
|
|
reg = READ1(sc, I2CCON);
|
|
|
|
reg &= ~(ACKGEN);
|
|
|
|
WRITE1(sc, I2CCON, reg);
|
2016-04-10 23:07:00 +00:00
|
|
|
}
|
2014-03-30 15:22:36 +00:00
|
|
|
|
|
|
|
clear_ipend(sc);
|
|
|
|
|
|
|
|
error = wait_for_iif(sc);
|
|
|
|
if (error) {
|
|
|
|
DPRINTF("cant i2c read: iif error\n");
|
|
|
|
mtx_unlock(&sc->mutex);
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
|
|
|
d = READ1(sc, I2CDS);
|
|
|
|
DPRINTF("0x%02x ", d);
|
|
|
|
*buf++ = d;
|
|
|
|
(*read)++;
|
|
|
|
}
|
|
|
|
DPRINTF("\n");
|
|
|
|
|
|
|
|
mtx_unlock(&sc->mutex);
|
|
|
|
return (IIC_NOERR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
|
|
|
|
{
|
|
|
|
struct i2c_softc *sc;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
DPRINTF("i2c write\n");
|
|
|
|
|
|
|
|
*sent = 0;
|
|
|
|
|
|
|
|
mtx_lock(&sc->mutex);
|
|
|
|
|
|
|
|
DPRINTF("writing ");
|
|
|
|
while (*sent < len) {
|
|
|
|
uint8_t d = *buf++;
|
|
|
|
DPRINTF("0x%02x ", d);
|
|
|
|
|
|
|
|
WRITE1(sc, I2CDS, d);
|
|
|
|
DELAY(50);
|
|
|
|
|
|
|
|
clear_ipend(sc);
|
|
|
|
|
|
|
|
error = wait_for_iif(sc);
|
|
|
|
if (error) {
|
|
|
|
DPRINTF("cant i2c write: iif error\n");
|
|
|
|
mtx_unlock(&sc->mutex);
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!is_ack(sc)) {
|
|
|
|
DPRINTF("cant i2c write: no ack\n");
|
|
|
|
mtx_unlock(&sc->mutex);
|
|
|
|
return (IIC_ENOACK);
|
2016-04-10 23:07:00 +00:00
|
|
|
}
|
2014-03-30 15:22:36 +00:00
|
|
|
|
|
|
|
(*sent)++;
|
|
|
|
}
|
|
|
|
DPRINTF("\n");
|
|
|
|
|
|
|
|
mtx_unlock(&sc->mutex);
|
|
|
|
return (IIC_NOERR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t i2c_methods[] = {
|
|
|
|
DEVMETHOD(device_probe, i2c_probe),
|
|
|
|
DEVMETHOD(device_attach, i2c_attach),
|
|
|
|
|
|
|
|
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
|
|
|
DEVMETHOD(iicbus_start, i2c_start),
|
|
|
|
DEVMETHOD(iicbus_stop, i2c_stop),
|
|
|
|
DEVMETHOD(iicbus_reset, i2c_reset),
|
|
|
|
DEVMETHOD(iicbus_read, i2c_read),
|
|
|
|
DEVMETHOD(iicbus_write, i2c_write),
|
|
|
|
DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t i2c_driver = {
|
|
|
|
"i2c",
|
|
|
|
i2c_methods,
|
|
|
|
sizeof(struct i2c_softc),
|
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t i2c_devclass;
|
|
|
|
|
|
|
|
DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
|
|
|
|
DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
|